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68 #ifndef _VL53L1_REGISTER_MAP_H_
69 #define _VL53L1_REGISTER_MAP_H_
75 #define VL53L1_SOFT_RESET 0x0000
82 #define VL53L1_I2C_SLAVE__DEVICE_ADDRESS 0x0001
97 #define VL53L1_ANA_CONFIG__VHV_REF_SEL_VDDPIX 0x0002
112 #define VL53L1_ANA_CONFIG__VHV_REF_SEL_VQUENCH 0x0003
127 #define VL53L1_ANA_CONFIG__REG_AVDD1V2_SEL 0x0004
142 #define VL53L1_ANA_CONFIG__FAST_OSC__TRIM 0x0005
157 #define VL53L1_OSC_MEASURED__FAST_OSC__FREQUENCY 0x0006
172 #define VL53L1_OSC_MEASURED__FAST_OSC__FREQUENCY_HI 0x0006
179 #define VL53L1_OSC_MEASURED__FAST_OSC__FREQUENCY_LO 0x0007
186 #define VL53L1_VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND 0x0008
202 #define VL53L1_VHV_CONFIG__COUNT_THRESH 0x0009
217 #define VL53L1_VHV_CONFIG__OFFSET 0x000A
232 #define VL53L1_VHV_CONFIG__INIT 0x000B
248 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_0 0x000D
263 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_1 0x000E
278 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_2 0x000F
293 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_3 0x0010
308 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_4 0x0011
323 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_REF_5 0x0012
338 #define VL53L1_GLOBAL_CONFIG__REF_EN_START_SELECT 0x0013
353 #define VL53L1_REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS 0x0014
368 #define VL53L1_REF_SPAD_MAN__REF_LOCATION 0x0015
383 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS 0x0016
398 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI 0x0016
405 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO 0x0017
412 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS 0x0018
427 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI 0x0018
434 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO 0x0019
441 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS 0x001A
456 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI 0x001A
463 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO 0x001B
470 #define VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS 0x001C
485 #define VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_HI 0x001C
492 #define VL53L1_REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_LO 0x001D
499 #define VL53L1_ALGO__PART_TO_PART_RANGE_OFFSET_MM 0x001E
514 #define VL53L1_ALGO__PART_TO_PART_RANGE_OFFSET_MM_HI 0x001E
521 #define VL53L1_ALGO__PART_TO_PART_RANGE_OFFSET_MM_LO 0x001F
528 #define VL53L1_MM_CONFIG__INNER_OFFSET_MM 0x0020
543 #define VL53L1_MM_CONFIG__INNER_OFFSET_MM_HI 0x0020
550 #define VL53L1_MM_CONFIG__INNER_OFFSET_MM_LO 0x0021
557 #define VL53L1_MM_CONFIG__OUTER_OFFSET_MM 0x0022
572 #define VL53L1_MM_CONFIG__OUTER_OFFSET_MM_HI 0x0022
579 #define VL53L1_MM_CONFIG__OUTER_OFFSET_MM_LO 0x0023
586 #define VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS 0x0024
601 #define VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_HI 0x0024
608 #define VL53L1_DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_LO 0x0025
615 #define VL53L1_DEBUG__CTRL 0x0026
630 #define VL53L1_TEST_MODE__CTRL 0x0027
645 #define VL53L1_CLK_GATING__CTRL 0x0028
663 #define VL53L1_NVM_BIST__CTRL 0x0029
679 #define VL53L1_NVM_BIST__NUM_NVM_WORDS 0x002A
694 #define VL53L1_NVM_BIST__START_ADDRESS 0x002B
709 #define VL53L1_HOST_IF__STATUS 0x002C
724 #define VL53L1_PAD_I2C_HV__CONFIG 0x002D
744 #define VL53L1_PAD_I2C_HV__EXTSUP_CONFIG 0x002E
759 #define VL53L1_GPIO_HV_PAD__CTRL 0x002F
775 #define VL53L1_GPIO_HV_MUX__CTRL 0x0030
791 #define VL53L1_GPIO__TIO_HV_STATUS 0x0031
807 #define VL53L1_GPIO__FIO_HV_STATUS 0x0032
822 #define VL53L1_ANA_CONFIG__SPAD_SEL_PSWIDTH 0x0033
837 #define VL53L1_ANA_CONFIG__VCSEL_PULSE_WIDTH_OFFSET 0x0034
852 #define VL53L1_ANA_CONFIG__FAST_OSC__CONFIG_CTRL 0x0035
867 #define VL53L1_SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS 0x0036
882 #define VL53L1_SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS 0x0037
897 #define VL53L1_SIGMA_ESTIMATOR__SIGMA_REF_MM 0x0038
912 #define VL53L1_ALGO__CROSSTALK_COMPENSATION_VALID_HEIGHT_MM 0x0039
927 #define VL53L1_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_0 0x003A
942 #define VL53L1_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_1 0x003B
957 #define VL53L1_ALGO__RANGE_IGNORE_THRESHOLD_MCPS 0x003C
972 #define VL53L1_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_HI 0x003C
979 #define VL53L1_ALGO__RANGE_IGNORE_THRESHOLD_MCPS_LO 0x003D
986 #define VL53L1_ALGO__RANGE_IGNORE_VALID_HEIGHT_MM 0x003E
1001 #define VL53L1_ALGO__RANGE_MIN_CLIP 0x003F
1017 #define VL53L1_ALGO__CONSISTENCY_CHECK__TOLERANCE 0x0040
1032 #define VL53L1_SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_2 0x0041
1047 #define VL53L1_SD_CONFIG__RESET_STAGES_MSB 0x0042
1062 #define VL53L1_SD_CONFIG__RESET_STAGES_LSB 0x0043
1078 #define VL53L1_GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE 0x0044
1093 #define VL53L1_GLOBAL_CONFIG__STREAM_DIVIDER 0x0045
1108 #define VL53L1_SYSTEM__INTERRUPT_CONFIG_GPIO 0x0046
1128 #define VL53L1_CAL_CONFIG__VCSEL_START 0x0047
1143 #define VL53L1_CAL_CONFIG__REPEAT_RATE 0x0048
1158 #define VL53L1_CAL_CONFIG__REPEAT_RATE_HI 0x0048
1165 #define VL53L1_CAL_CONFIG__REPEAT_RATE_LO 0x0049
1172 #define VL53L1_GLOBAL_CONFIG__VCSEL_WIDTH 0x004A
1187 #define VL53L1_PHASECAL_CONFIG__TIMEOUT_MACROP 0x004B
1202 #define VL53L1_PHASECAL_CONFIG__TARGET 0x004C
1217 #define VL53L1_PHASECAL_CONFIG__OVERRIDE 0x004D
1232 #define VL53L1_DSS_CONFIG__ROI_MODE_CONTROL 0x004F
1248 #define VL53L1_SYSTEM__THRESH_RATE_HIGH 0x0050
1263 #define VL53L1_SYSTEM__THRESH_RATE_HIGH_HI 0x0050
1270 #define VL53L1_SYSTEM__THRESH_RATE_HIGH_LO 0x0051
1277 #define VL53L1_SYSTEM__THRESH_RATE_LOW 0x0052
1292 #define VL53L1_SYSTEM__THRESH_RATE_LOW_HI 0x0052
1299 #define VL53L1_SYSTEM__THRESH_RATE_LOW_LO 0x0053
1306 #define VL53L1_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0054
1321 #define VL53L1_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0054
1328 #define VL53L1_DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0055
1335 #define VL53L1_DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0056
1350 #define VL53L1_DSS_CONFIG__APERTURE_ATTENUATION 0x0057
1365 #define VL53L1_DSS_CONFIG__MAX_SPADS_LIMIT 0x0058
1380 #define VL53L1_DSS_CONFIG__MIN_SPADS_LIMIT 0x0059
1395 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_HI 0x005A
1410 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_A_LO 0x005B
1425 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_B_HI 0x005C
1440 #define VL53L1_MM_CONFIG__TIMEOUT_MACROP_B_LO 0x005D
1455 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x005E
1470 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x005F
1485 #define VL53L1_RANGE_CONFIG__VCSEL_PERIOD_A 0x0060
1500 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0061
1515 #define VL53L1_RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0062
1530 #define VL53L1_RANGE_CONFIG__VCSEL_PERIOD_B 0x0063
1545 #define VL53L1_RANGE_CONFIG__SIGMA_THRESH 0x0064
1560 #define VL53L1_RANGE_CONFIG__SIGMA_THRESH_HI 0x0064
1567 #define VL53L1_RANGE_CONFIG__SIGMA_THRESH_LO 0x0065
1574 #define VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0066
1589 #define VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0066
1596 #define VL53L1_RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0067
1603 #define VL53L1_RANGE_CONFIG__VALID_PHASE_LOW 0x0068
1618 #define VL53L1_RANGE_CONFIG__VALID_PHASE_HIGH 0x0069
1633 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD 0x006C
1648 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_3 0x006C
1655 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_2 0x006D
1662 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_1 0x006E
1669 #define VL53L1_SYSTEM__INTERMEASUREMENT_PERIOD_0 0x006F
1676 #define VL53L1_SYSTEM__FRACTIONAL_ENABLE 0x0070
1691 #define VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_0 0x0071
1707 #define VL53L1_SYSTEM__THRESH_HIGH 0x0072
1722 #define VL53L1_SYSTEM__THRESH_HIGH_HI 0x0072
1729 #define VL53L1_SYSTEM__THRESH_HIGH_LO 0x0073
1736 #define VL53L1_SYSTEM__THRESH_LOW 0x0074
1751 #define VL53L1_SYSTEM__THRESH_LOW_HI 0x0074
1758 #define VL53L1_SYSTEM__THRESH_LOW_LO 0x0075
1765 #define VL53L1_SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x0076
1780 #define VL53L1_SYSTEM__SEED_CONFIG 0x0077
1796 #define VL53L1_SD_CONFIG__WOI_SD0 0x0078
1811 #define VL53L1_SD_CONFIG__WOI_SD1 0x0079
1826 #define VL53L1_SD_CONFIG__INITIAL_PHASE_SD0 0x007A
1841 #define VL53L1_SD_CONFIG__INITIAL_PHASE_SD1 0x007B
1856 #define VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD_1 0x007C
1872 #define VL53L1_SD_CONFIG__FIRST_ORDER_SELECT 0x007D
1888 #define VL53L1_SD_CONFIG__QUANTIFIER 0x007E
1903 #define VL53L1_ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x007F
1918 #define VL53L1_ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x0080
1933 #define VL53L1_SYSTEM__SEQUENCE_CONFIG 0x0081
1955 #define VL53L1_SYSTEM__GROUPED_PARAMETER_HOLD 0x0082
1971 #define VL53L1_POWER_MANAGEMENT__GO1_POWER_FORCE 0x0083
1986 #define VL53L1_SYSTEM__STREAM_COUNT_CTRL 0x0084
2001 #define VL53L1_FIRMWARE__ENABLE 0x0085
2016 #define VL53L1_SYSTEM__INTERRUPT_CLEAR 0x0086
2032 #define VL53L1_SYSTEM__MODE_START 0x0087
2052 #define VL53L1_RESULT__INTERRUPT_STATUS 0x0088
2069 #define VL53L1_RESULT__RANGE_STATUS 0x0089
2087 #define VL53L1_RESULT__REPORT_STATUS 0x008A
2102 #define VL53L1_RESULT__STREAM_COUNT 0x008B
2117 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x008C
2132 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x008C
2139 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x008D
2146 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x008E
2161 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x008E
2168 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x008F
2175 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0090
2190 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0090
2197 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0091
2204 #define VL53L1_RESULT__SIGMA_SD0 0x0092
2219 #define VL53L1_RESULT__SIGMA_SD0_HI 0x0092
2226 #define VL53L1_RESULT__SIGMA_SD0_LO 0x0093
2233 #define VL53L1_RESULT__PHASE_SD0 0x0094
2248 #define VL53L1_RESULT__PHASE_SD0_HI 0x0094
2255 #define VL53L1_RESULT__PHASE_SD0_LO 0x0095
2262 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0096
2277 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0096
2284 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0097
2291 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0098
2306 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0098
2313 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0099
2320 #define VL53L1_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009A
2335 #define VL53L1_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009A
2342 #define VL53L1_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009B
2349 #define VL53L1_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x009C
2364 #define VL53L1_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x009C
2371 #define VL53L1_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x009D
2378 #define VL53L1_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x009E
2393 #define VL53L1_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x009E
2400 #define VL53L1_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x009F
2407 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x00A0
2422 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x00A0
2429 #define VL53L1_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x00A1
2436 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x00A2
2451 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x00A2
2458 #define VL53L1_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x00A3
2465 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x00A4
2480 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x00A4
2487 #define VL53L1_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x00A5
2494 #define VL53L1_RESULT__SIGMA_SD1 0x00A6
2509 #define VL53L1_RESULT__SIGMA_SD1_HI 0x00A6
2516 #define VL53L1_RESULT__SIGMA_SD1_LO 0x00A7
2523 #define VL53L1_RESULT__PHASE_SD1 0x00A8
2538 #define VL53L1_RESULT__PHASE_SD1_HI 0x00A8
2545 #define VL53L1_RESULT__PHASE_SD1_LO 0x00A9
2552 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x00AA
2567 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x00AA
2574 #define VL53L1_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x00AB
2581 #define VL53L1_RESULT__SPARE_0_SD1 0x00AC
2596 #define VL53L1_RESULT__SPARE_0_SD1_HI 0x00AC
2603 #define VL53L1_RESULT__SPARE_0_SD1_LO 0x00AD
2610 #define VL53L1_RESULT__SPARE_1_SD1 0x00AE
2625 #define VL53L1_RESULT__SPARE_1_SD1_HI 0x00AE
2632 #define VL53L1_RESULT__SPARE_1_SD1_LO 0x00AF
2639 #define VL53L1_RESULT__SPARE_2_SD1 0x00B0
2654 #define VL53L1_RESULT__SPARE_2_SD1_HI 0x00B0
2661 #define VL53L1_RESULT__SPARE_2_SD1_LO 0x00B1
2668 #define VL53L1_RESULT__SPARE_3_SD1 0x00B2
2683 #define VL53L1_RESULT__THRESH_INFO 0x00B3
2699 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x00B4
2714 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x00B4
2721 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x00B5
2728 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x00B6
2735 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x00B7
2742 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x00B8
2757 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x00B8
2764 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x00B9
2771 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x00BA
2778 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x00BB
2785 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x00BC
2800 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x00BC
2807 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x00BD
2814 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x00BE
2821 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x00BF
2828 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x00C0
2843 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x00C0
2850 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x00C1
2857 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x00C2
2864 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x00C3
2871 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x00C4
2886 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x00C4
2893 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x00C5
2900 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x00C6
2907 #define VL53L1_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x00C7
2914 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x00C8
2929 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x00C8
2936 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x00C9
2943 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x00CA
2950 #define VL53L1_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x00CB
2957 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x00CC
2972 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x00CC
2979 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x00CD
2986 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x00CE
2993 #define VL53L1_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x00CF
3000 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x00D0
3015 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x00D0
3022 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x00D1
3029 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x00D2
3036 #define VL53L1_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x00D3
3043 #define VL53L1_RESULT_CORE__SPARE_0 0x00D4
3058 #define VL53L1_PHASECAL_RESULT__REFERENCE_PHASE 0x00D6
3073 #define VL53L1_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x00D6
3080 #define VL53L1_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x00D7
3087 #define VL53L1_PHASECAL_RESULT__VCSEL_START 0x00D8
3102 #define VL53L1_REF_SPAD_CHAR_RESULT__NUM_ACTUAL_REF_SPADS 0x00D9
3117 #define VL53L1_REF_SPAD_CHAR_RESULT__REF_LOCATION 0x00DA
3132 #define VL53L1_VHV_RESULT__COLDBOOT_STATUS 0x00DB
3147 #define VL53L1_VHV_RESULT__SEARCH_RESULT 0x00DC
3162 #define VL53L1_VHV_RESULT__LATEST_SETTING 0x00DD
3177 #define VL53L1_RESULT__OSC_CALIBRATE_VAL 0x00DE
3192 #define VL53L1_RESULT__OSC_CALIBRATE_VAL_HI 0x00DE
3199 #define VL53L1_RESULT__OSC_CALIBRATE_VAL_LO 0x00DF
3206 #define VL53L1_ANA_CONFIG__POWERDOWN_GO1 0x00E0
3222 #define VL53L1_ANA_CONFIG__REF_BG_CTRL 0x00E1
3238 #define VL53L1_ANA_CONFIG__REGDVDD1V2_CTRL 0x00E2
3255 #define VL53L1_ANA_CONFIG__OSC_SLOW_CTRL 0x00E3
3272 #define VL53L1_TEST_MODE__STATUS 0x00E4
3287 #define VL53L1_FIRMWARE__SYSTEM_STATUS 0x00E5
3303 #define VL53L1_FIRMWARE__MODE_STATUS 0x00E6
3318 #define VL53L1_FIRMWARE__SECONDARY_MODE_STATUS 0x00E7
3333 #define VL53L1_FIRMWARE__CAL_REPEAT_RATE_COUNTER 0x00E8
3348 #define VL53L1_FIRMWARE__CAL_REPEAT_RATE_COUNTER_HI 0x00E8
3355 #define VL53L1_FIRMWARE__CAL_REPEAT_RATE_COUNTER_LO 0x00E9
3362 #define VL53L1_FIRMWARE__HISTOGRAM_BIN 0x00EA
3369 #define VL53L1_GPH__SYSTEM__THRESH_HIGH 0x00EC
3384 #define VL53L1_GPH__SYSTEM__THRESH_HIGH_HI 0x00EC
3391 #define VL53L1_GPH__SYSTEM__THRESH_HIGH_LO 0x00ED
3398 #define VL53L1_GPH__SYSTEM__THRESH_LOW 0x00EE
3413 #define VL53L1_GPH__SYSTEM__THRESH_LOW_HI 0x00EE
3420 #define VL53L1_GPH__SYSTEM__THRESH_LOW_LO 0x00EF
3427 #define VL53L1_GPH__SYSTEM__ENABLE_XTALK_PER_QUADRANT 0x00F0
3442 #define VL53L1_GPH__SPARE_0 0x00F1
3459 #define VL53L1_GPH__SD_CONFIG__WOI_SD0 0x00F2
3474 #define VL53L1_GPH__SD_CONFIG__WOI_SD1 0x00F3
3489 #define VL53L1_GPH__SD_CONFIG__INITIAL_PHASE_SD0 0x00F4
3504 #define VL53L1_GPH__SD_CONFIG__INITIAL_PHASE_SD1 0x00F5
3519 #define VL53L1_GPH__SD_CONFIG__FIRST_ORDER_SELECT 0x00F6
3535 #define VL53L1_GPH__SD_CONFIG__QUANTIFIER 0x00F7
3550 #define VL53L1_GPH__ROI_CONFIG__USER_ROI_CENTRE_SPAD 0x00F8
3565 #define VL53L1_GPH__ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE 0x00F9
3580 #define VL53L1_GPH__SYSTEM__SEQUENCE_CONFIG 0x00FA
3602 #define VL53L1_GPH__GPH_ID 0x00FB
3617 #define VL53L1_SYSTEM__INTERRUPT_SET 0x00FC
3633 #define VL53L1_INTERRUPT_MANAGER__ENABLES 0x00FD
3652 #define VL53L1_INTERRUPT_MANAGER__CLEAR 0x00FE
3671 #define VL53L1_INTERRUPT_MANAGER__STATUS 0x00FF
3690 #define VL53L1_MCU_TO_HOST_BANK__WR_ACCESS_EN 0x0100
3705 #define VL53L1_POWER_MANAGEMENT__GO1_RESET_STATUS 0x0101
3720 #define VL53L1_PAD_STARTUP_MODE__VALUE_RO 0x0102
3736 #define VL53L1_PAD_STARTUP_MODE__VALUE_CTRL 0x0103
3754 #define VL53L1_PLL_PERIOD_US 0x0104
3769 #define VL53L1_PLL_PERIOD_US_3 0x0104
3776 #define VL53L1_PLL_PERIOD_US_2 0x0105
3783 #define VL53L1_PLL_PERIOD_US_1 0x0106
3790 #define VL53L1_PLL_PERIOD_US_0 0x0107
3797 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT 0x0108
3812 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_3 0x0108
3819 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_2 0x0109
3826 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_1 0x010A
3833 #define VL53L1_INTERRUPT_SCHEDULER__DATA_OUT_0 0x010B
3840 #define VL53L1_NVM_BIST__COMPLETE 0x010C
3855 #define VL53L1_NVM_BIST__STATUS 0x010D
3870 #define VL53L1_IDENTIFICATION__MODEL_ID 0x010F
3885 #define VL53L1_IDENTIFICATION__MODULE_TYPE 0x0110
3900 #define VL53L1_IDENTIFICATION__REVISION_ID 0x0111
3916 #define VL53L1_IDENTIFICATION__MODULE_ID 0x0112
3931 #define VL53L1_IDENTIFICATION__MODULE_ID_HI 0x0112
3938 #define VL53L1_IDENTIFICATION__MODULE_ID_LO 0x0113
3945 #define VL53L1_ANA_CONFIG__FAST_OSC__TRIM_MAX 0x0114
3960 #define VL53L1_ANA_CONFIG__FAST_OSC__FREQ_SET 0x0115
3975 #define VL53L1_ANA_CONFIG__VCSEL_TRIM 0x0116
3990 #define VL53L1_ANA_CONFIG__VCSEL_SELION 0x0117
4005 #define VL53L1_ANA_CONFIG__VCSEL_SELION_MAX 0x0118
4020 #define VL53L1_PROTECTED_LASER_SAFETY__LOCK_BIT 0x0119
4035 #define VL53L1_LASER_SAFETY__KEY 0x011A
4050 #define VL53L1_LASER_SAFETY__KEY_RO 0x011B
4065 #define VL53L1_LASER_SAFETY__CLIP 0x011C
4080 #define VL53L1_LASER_SAFETY__MULT 0x011D
4095 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_0 0x011E
4110 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_1 0x011F
4125 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_2 0x0120
4140 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_3 0x0121
4155 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_4 0x0122
4170 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_5 0x0123
4185 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_6 0x0124
4200 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_7 0x0125
4215 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_8 0x0126
4230 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_9 0x0127
4245 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_10 0x0128
4260 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_11 0x0129
4275 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_12 0x012A
4290 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_13 0x012B
4305 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_14 0x012C
4320 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_15 0x012D
4335 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_16 0x012E
4350 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_17 0x012F
4365 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_18 0x0130
4380 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_19 0x0131
4395 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_20 0x0132
4410 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_21 0x0133
4425 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_22 0x0134
4440 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_23 0x0135
4455 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_24 0x0136
4470 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_25 0x0137
4485 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_26 0x0138
4500 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_27 0x0139
4515 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_28 0x013A
4530 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_29 0x013B
4545 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_30 0x013C
4560 #define VL53L1_GLOBAL_CONFIG__SPAD_ENABLES_RTN_31 0x013D
4575 #define VL53L1_ROI_CONFIG__MODE_ROI_CENTRE_SPAD 0x013E
4590 #define VL53L1_ROI_CONFIG__MODE_ROI_XY_SIZE 0x013F
4605 #define VL53L1_GO2_HOST_BANK_ACCESS__OVERRIDE 0x0300
4612 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND 0x0400
4619 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_3 0x0400
4626 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_2 0x0401
4633 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_1 0x0402
4640 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLICAND_0 0x0403
4647 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER 0x0404
4654 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_3 0x0404
4661 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_2 0x0405
4668 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_1 0x0406
4675 #define VL53L1_MCU_UTIL_MULTIPLIER__MULTIPLIER_0 0x0407
4682 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI 0x0408
4689 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_3 0x0408
4696 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_2 0x0409
4703 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_1 0x040A
4710 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_HI_0 0x040B
4717 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO 0x040C
4724 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_3 0x040C
4731 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_2 0x040D
4738 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_1 0x040E
4745 #define VL53L1_MCU_UTIL_MULTIPLIER__PRODUCT_LO_0 0x040F
4752 #define VL53L1_MCU_UTIL_MULTIPLIER__START 0x0410
4759 #define VL53L1_MCU_UTIL_MULTIPLIER__STATUS 0x0411
4766 #define VL53L1_MCU_UTIL_DIVIDER__START 0x0412
4773 #define VL53L1_MCU_UTIL_DIVIDER__STATUS 0x0413
4780 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND 0x0414
4787 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_3 0x0414
4794 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_2 0x0415
4801 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_1 0x0416
4808 #define VL53L1_MCU_UTIL_DIVIDER__DIVIDEND_0 0x0417
4815 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR 0x0418
4822 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_3 0x0418
4829 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_2 0x0419
4836 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_1 0x041A
4843 #define VL53L1_MCU_UTIL_DIVIDER__DIVISOR_0 0x041B
4850 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT 0x041C
4857 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_3 0x041C
4864 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_2 0x041D
4871 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_1 0x041E
4878 #define VL53L1_MCU_UTIL_DIVIDER__QUOTIENT_0 0x041F
4885 #define VL53L1_TIMER0__VALUE_IN 0x0420
4892 #define VL53L1_TIMER0__VALUE_IN_3 0x0420
4899 #define VL53L1_TIMER0__VALUE_IN_2 0x0421
4906 #define VL53L1_TIMER0__VALUE_IN_1 0x0422
4913 #define VL53L1_TIMER0__VALUE_IN_0 0x0423
4920 #define VL53L1_TIMER1__VALUE_IN 0x0424
4927 #define VL53L1_TIMER1__VALUE_IN_3 0x0424
4934 #define VL53L1_TIMER1__VALUE_IN_2 0x0425
4941 #define VL53L1_TIMER1__VALUE_IN_1 0x0426
4948 #define VL53L1_TIMER1__VALUE_IN_0 0x0427
4955 #define VL53L1_TIMER0__CTRL 0x0428
4962 #define VL53L1_TIMER1__CTRL 0x0429
4969 #define VL53L1_MCU_GENERAL_PURPOSE__GP_0 0x042C
4984 #define VL53L1_MCU_GENERAL_PURPOSE__GP_1 0x042D
4999 #define VL53L1_MCU_GENERAL_PURPOSE__GP_2 0x042E
5014 #define VL53L1_MCU_GENERAL_PURPOSE__GP_3 0x042F
5029 #define VL53L1_MCU_RANGE_CALC__CONFIG 0x0430
5050 #define VL53L1_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE 0x0432
5065 #define VL53L1_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_HI 0x0432
5072 #define VL53L1_MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_LO 0x0433
5079 #define VL53L1_MCU_RANGE_CALC__SPARE_4 0x0434
5094 #define VL53L1_MCU_RANGE_CALC__SPARE_4_3 0x0434
5101 #define VL53L1_MCU_RANGE_CALC__SPARE_4_2 0x0435
5108 #define VL53L1_MCU_RANGE_CALC__SPARE_4_1 0x0436
5115 #define VL53L1_MCU_RANGE_CALC__SPARE_4_0 0x0437
5122 #define VL53L1_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC 0x0438
5137 #define VL53L1_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_HI 0x0438
5144 #define VL53L1_MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_LO 0x0439
5151 #define VL53L1_MCU_RANGE_CALC__ALGO_VCSEL_PERIOD 0x043C
5166 #define VL53L1_MCU_RANGE_CALC__SPARE_5 0x043D
5181 #define VL53L1_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS 0x043E
5196 #define VL53L1_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_HI 0x043E
5203 #define VL53L1_MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_LO 0x043F
5210 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE 0x0440
5225 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_3 0x0440
5232 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_2 0x0441
5239 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_1 0x0442
5246 #define VL53L1_MCU_RANGE_CALC__ALGO_ACCUM_PHASE_0 0x0443
5253 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS 0x0444
5268 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_3 0x0444
5275 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_2 0x0445
5282 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_1 0x0446
5289 #define VL53L1_MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_0 0x0447
5296 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS 0x0448
5311 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_3 0x0448
5318 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_2 0x0449
5325 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_1 0x044A
5332 #define VL53L1_MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_0 0x044B
5339 #define VL53L1_MCU_RANGE_CALC__SPARE_6 0x044C
5354 #define VL53L1_MCU_RANGE_CALC__SPARE_6_HI 0x044C
5361 #define VL53L1_MCU_RANGE_CALC__SPARE_6_LO 0x044D
5368 #define VL53L1_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD 0x044E
5383 #define VL53L1_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_HI 0x044E
5390 #define VL53L1_MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_LO 0x044F
5397 #define VL53L1_MCU_RANGE_CALC__NUM_SPADS 0x0450
5412 #define VL53L1_MCU_RANGE_CALC__NUM_SPADS_HI 0x0450
5419 #define VL53L1_MCU_RANGE_CALC__NUM_SPADS_LO 0x0451
5426 #define VL53L1_MCU_RANGE_CALC__PHASE_OUTPUT 0x0452
5441 #define VL53L1_MCU_RANGE_CALC__PHASE_OUTPUT_HI 0x0452
5448 #define VL53L1_MCU_RANGE_CALC__PHASE_OUTPUT_LO 0x0453
5455 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS 0x0454
5470 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_3 0x0454
5477 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_2 0x0455
5484 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_1 0x0456
5491 #define VL53L1_MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_0 0x0457
5498 #define VL53L1_MCU_RANGE_CALC__SPARE_7 0x0458
5513 #define VL53L1_MCU_RANGE_CALC__SPARE_8 0x0459
5528 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS 0x045A
5543 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_HI 0x045A
5550 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_LO 0x045B
5557 #define VL53L1_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS 0x045C
5572 #define VL53L1_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_HI 0x045C
5579 #define VL53L1_MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_LO 0x045D
5586 #define VL53L1_MCU_RANGE_CALC__AMBIENT_RATE_MCPS 0x045E
5601 #define VL53L1_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_HI 0x045E
5608 #define VL53L1_MCU_RANGE_CALC__AMBIENT_RATE_MCPS_LO 0x045F
5615 #define VL53L1_MCU_RANGE_CALC__XTALK 0x0460
5630 #define VL53L1_MCU_RANGE_CALC__XTALK_HI 0x0460
5637 #define VL53L1_MCU_RANGE_CALC__XTALK_LO 0x0461
5644 #define VL53L1_MCU_RANGE_CALC__CALC_STATUS 0x0462
5659 #define VL53L1_MCU_RANGE_CALC__DEBUG 0x0463
5674 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS 0x0464
5689 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI 0x0464
5696 #define VL53L1_MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO 0x0465
5703 #define VL53L1_MCU_RANGE_CALC__SPARE_0 0x0468
5718 #define VL53L1_MCU_RANGE_CALC__SPARE_1 0x0469
5733 #define VL53L1_MCU_RANGE_CALC__SPARE_2 0x046A
5748 #define VL53L1_MCU_RANGE_CALC__SPARE_3 0x046B
5763 #define VL53L1_PATCH__CTRL 0x0470
5770 #define VL53L1_PATCH__JMP_ENABLES 0x0472
5777 #define VL53L1_PATCH__JMP_ENABLES_HI 0x0472
5784 #define VL53L1_PATCH__JMP_ENABLES_LO 0x0473
5791 #define VL53L1_PATCH__DATA_ENABLES 0x0474
5798 #define VL53L1_PATCH__DATA_ENABLES_HI 0x0474
5805 #define VL53L1_PATCH__DATA_ENABLES_LO 0x0475
5812 #define VL53L1_PATCH__OFFSET_0 0x0476
5819 #define VL53L1_PATCH__OFFSET_0_HI 0x0476
5826 #define VL53L1_PATCH__OFFSET_0_LO 0x0477
5833 #define VL53L1_PATCH__OFFSET_1 0x0478
5840 #define VL53L1_PATCH__OFFSET_1_HI 0x0478
5847 #define VL53L1_PATCH__OFFSET_1_LO 0x0479
5854 #define VL53L1_PATCH__OFFSET_2 0x047A
5861 #define VL53L1_PATCH__OFFSET_2_HI 0x047A
5868 #define VL53L1_PATCH__OFFSET_2_LO 0x047B
5875 #define VL53L1_PATCH__OFFSET_3 0x047C
5882 #define VL53L1_PATCH__OFFSET_3_HI 0x047C
5889 #define VL53L1_PATCH__OFFSET_3_LO 0x047D
5896 #define VL53L1_PATCH__OFFSET_4 0x047E
5903 #define VL53L1_PATCH__OFFSET_4_HI 0x047E
5910 #define VL53L1_PATCH__OFFSET_4_LO 0x047F
5917 #define VL53L1_PATCH__OFFSET_5 0x0480
5924 #define VL53L1_PATCH__OFFSET_5_HI 0x0480
5931 #define VL53L1_PATCH__OFFSET_5_LO 0x0481
5938 #define VL53L1_PATCH__OFFSET_6 0x0482
5945 #define VL53L1_PATCH__OFFSET_6_HI 0x0482
5952 #define VL53L1_PATCH__OFFSET_6_LO 0x0483
5959 #define VL53L1_PATCH__OFFSET_7 0x0484
5966 #define VL53L1_PATCH__OFFSET_7_HI 0x0484
5973 #define VL53L1_PATCH__OFFSET_7_LO 0x0485
5980 #define VL53L1_PATCH__OFFSET_8 0x0486
5987 #define VL53L1_PATCH__OFFSET_8_HI 0x0486
5994 #define VL53L1_PATCH__OFFSET_8_LO 0x0487
6001 #define VL53L1_PATCH__OFFSET_9 0x0488
6008 #define VL53L1_PATCH__OFFSET_9_HI 0x0488
6015 #define VL53L1_PATCH__OFFSET_9_LO 0x0489
6022 #define VL53L1_PATCH__OFFSET_10 0x048A
6029 #define VL53L1_PATCH__OFFSET_10_HI 0x048A
6036 #define VL53L1_PATCH__OFFSET_10_LO 0x048B
6043 #define VL53L1_PATCH__OFFSET_11 0x048C
6050 #define VL53L1_PATCH__OFFSET_11_HI 0x048C
6057 #define VL53L1_PATCH__OFFSET_11_LO 0x048D
6064 #define VL53L1_PATCH__OFFSET_12 0x048E
6071 #define VL53L1_PATCH__OFFSET_12_HI 0x048E
6078 #define VL53L1_PATCH__OFFSET_12_LO 0x048F
6085 #define VL53L1_PATCH__OFFSET_13 0x0490
6092 #define VL53L1_PATCH__OFFSET_13_HI 0x0490
6099 #define VL53L1_PATCH__OFFSET_13_LO 0x0491
6106 #define VL53L1_PATCH__OFFSET_14 0x0492
6113 #define VL53L1_PATCH__OFFSET_14_HI 0x0492
6120 #define VL53L1_PATCH__OFFSET_14_LO 0x0493
6127 #define VL53L1_PATCH__OFFSET_15 0x0494
6134 #define VL53L1_PATCH__OFFSET_15_HI 0x0494
6141 #define VL53L1_PATCH__OFFSET_15_LO 0x0495
6148 #define VL53L1_PATCH__ADDRESS_0 0x0496
6155 #define VL53L1_PATCH__ADDRESS_0_HI 0x0496
6162 #define VL53L1_PATCH__ADDRESS_0_LO 0x0497
6169 #define VL53L1_PATCH__ADDRESS_1 0x0498
6176 #define VL53L1_PATCH__ADDRESS_1_HI 0x0498
6183 #define VL53L1_PATCH__ADDRESS_1_LO 0x0499
6190 #define VL53L1_PATCH__ADDRESS_2 0x049A
6197 #define VL53L1_PATCH__ADDRESS_2_HI 0x049A
6204 #define VL53L1_PATCH__ADDRESS_2_LO 0x049B
6211 #define VL53L1_PATCH__ADDRESS_3 0x049C
6218 #define VL53L1_PATCH__ADDRESS_3_HI 0x049C
6225 #define VL53L1_PATCH__ADDRESS_3_LO 0x049D
6232 #define VL53L1_PATCH__ADDRESS_4 0x049E
6239 #define VL53L1_PATCH__ADDRESS_4_HI 0x049E
6246 #define VL53L1_PATCH__ADDRESS_4_LO 0x049F
6253 #define VL53L1_PATCH__ADDRESS_5 0x04A0
6260 #define VL53L1_PATCH__ADDRESS_5_HI 0x04A0
6267 #define VL53L1_PATCH__ADDRESS_5_LO 0x04A1
6274 #define VL53L1_PATCH__ADDRESS_6 0x04A2
6281 #define VL53L1_PATCH__ADDRESS_6_HI 0x04A2
6288 #define VL53L1_PATCH__ADDRESS_6_LO 0x04A3
6295 #define VL53L1_PATCH__ADDRESS_7 0x04A4
6302 #define VL53L1_PATCH__ADDRESS_7_HI 0x04A4
6309 #define VL53L1_PATCH__ADDRESS_7_LO 0x04A5
6316 #define VL53L1_PATCH__ADDRESS_8 0x04A6
6323 #define VL53L1_PATCH__ADDRESS_8_HI 0x04A6
6330 #define VL53L1_PATCH__ADDRESS_8_LO 0x04A7
6337 #define VL53L1_PATCH__ADDRESS_9 0x04A8
6344 #define VL53L1_PATCH__ADDRESS_9_HI 0x04A8
6351 #define VL53L1_PATCH__ADDRESS_9_LO 0x04A9
6358 #define VL53L1_PATCH__ADDRESS_10 0x04AA
6365 #define VL53L1_PATCH__ADDRESS_10_HI 0x04AA
6372 #define VL53L1_PATCH__ADDRESS_10_LO 0x04AB
6379 #define VL53L1_PATCH__ADDRESS_11 0x04AC
6386 #define VL53L1_PATCH__ADDRESS_11_HI 0x04AC
6393 #define VL53L1_PATCH__ADDRESS_11_LO 0x04AD
6400 #define VL53L1_PATCH__ADDRESS_12 0x04AE
6407 #define VL53L1_PATCH__ADDRESS_12_HI 0x04AE
6414 #define VL53L1_PATCH__ADDRESS_12_LO 0x04AF
6421 #define VL53L1_PATCH__ADDRESS_13 0x04B0
6428 #define VL53L1_PATCH__ADDRESS_13_HI 0x04B0
6435 #define VL53L1_PATCH__ADDRESS_13_LO 0x04B1
6442 #define VL53L1_PATCH__ADDRESS_14 0x04B2
6449 #define VL53L1_PATCH__ADDRESS_14_HI 0x04B2
6456 #define VL53L1_PATCH__ADDRESS_14_LO 0x04B3
6463 #define VL53L1_PATCH__ADDRESS_15 0x04B4
6470 #define VL53L1_PATCH__ADDRESS_15_HI 0x04B4
6477 #define VL53L1_PATCH__ADDRESS_15_LO 0x04B5
6484 #define VL53L1_SPI_ASYNC_MUX__CTRL 0x04C0
6491 #define VL53L1_CLK__CONFIG 0x04C4
6506 #define VL53L1_GPIO_LV_MUX__CTRL 0x04CC
6522 #define VL53L1_GPIO_LV_PAD__CTRL 0x04CD
6537 #define VL53L1_PAD_I2C_LV__CONFIG 0x04D0
6544 #define VL53L1_PAD_STARTUP_MODE__VALUE_RO_GO1 0x04D4
6559 #define VL53L1_HOST_IF__STATUS_GO1 0x04D5
6574 #define VL53L1_MCU_CLK_GATING__CTRL 0x04D8
6592 #define VL53L1_TEST__BIST_ROM_CTRL 0x04E0
6599 #define VL53L1_TEST__BIST_ROM_RESULT 0x04E1
6606 #define VL53L1_TEST__BIST_ROM_MCU_SIG 0x04E2
6613 #define VL53L1_TEST__BIST_ROM_MCU_SIG_HI 0x04E2
6620 #define VL53L1_TEST__BIST_ROM_MCU_SIG_LO 0x04E3
6627 #define VL53L1_TEST__BIST_RAM_CTRL 0x04E4
6634 #define VL53L1_TEST__BIST_RAM_RESULT 0x04E5
6641 #define VL53L1_TEST__TMC 0x04E8
6648 #define VL53L1_TEST__PLL_BIST_MIN_THRESHOLD 0x04F0
6655 #define VL53L1_TEST__PLL_BIST_MIN_THRESHOLD_HI 0x04F0
6662 #define VL53L1_TEST__PLL_BIST_MIN_THRESHOLD_LO 0x04F1
6669 #define VL53L1_TEST__PLL_BIST_MAX_THRESHOLD 0x04F2
6676 #define VL53L1_TEST__PLL_BIST_MAX_THRESHOLD_HI 0x04F2
6683 #define VL53L1_TEST__PLL_BIST_MAX_THRESHOLD_LO 0x04F3
6690 #define VL53L1_TEST__PLL_BIST_COUNT_OUT 0x04F4
6697 #define VL53L1_TEST__PLL_BIST_COUNT_OUT_HI 0x04F4
6704 #define VL53L1_TEST__PLL_BIST_COUNT_OUT_LO 0x04F5
6711 #define VL53L1_TEST__PLL_BIST_GONOGO 0x04F6
6718 #define VL53L1_TEST__PLL_BIST_CTRL 0x04F7
6725 #define VL53L1_RANGING_CORE__DEVICE_ID 0x0680
6732 #define VL53L1_RANGING_CORE__REVISION_ID 0x0681
6739 #define VL53L1_RANGING_CORE__CLK_CTRL1 0x0683
6746 #define VL53L1_RANGING_CORE__CLK_CTRL2 0x0684
6753 #define VL53L1_RANGING_CORE__WOI_1 0x0685
6760 #define VL53L1_RANGING_CORE__WOI_REF_1 0x0686
6767 #define VL53L1_RANGING_CORE__START_RANGING 0x0687
6774 #define VL53L1_RANGING_CORE__LOW_LIMIT_1 0x0690
6781 #define VL53L1_RANGING_CORE__HIGH_LIMIT_1 0x0691
6788 #define VL53L1_RANGING_CORE__LOW_LIMIT_REF_1 0x0692
6795 #define VL53L1_RANGING_CORE__HIGH_LIMIT_REF_1 0x0693
6802 #define VL53L1_RANGING_CORE__QUANTIFIER_1_MSB 0x0694
6809 #define VL53L1_RANGING_CORE__QUANTIFIER_1_LSB 0x0695
6816 #define VL53L1_RANGING_CORE__QUANTIFIER_REF_1_MSB 0x0696
6823 #define VL53L1_RANGING_CORE__QUANTIFIER_REF_1_LSB 0x0697
6830 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_1_MSB 0x0698
6837 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_1_LSB 0x0699
6844 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_REF_1_MSB 0x069A
6851 #define VL53L1_RANGING_CORE__AMBIENT_OFFSET_REF_1_LSB 0x069B
6858 #define VL53L1_RANGING_CORE__FILTER_STRENGTH_1 0x069C
6865 #define VL53L1_RANGING_CORE__FILTER_STRENGTH_REF_1 0x069D
6872 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_MSB 0x069E
6879 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_1_LSB 0x069F
6886 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_MSB 0x06A0
6893 #define VL53L1_RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_LSB 0x06A1
6900 #define VL53L1_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_MSB 0x06A4
6907 #define VL53L1_RANGING_CORE__TIMEOUT_OVERALL_PERIODS_LSB 0x06A5
6914 #define VL53L1_RANGING_CORE__INVERT_HW 0x06A6
6921 #define VL53L1_RANGING_CORE__FORCE_HW 0x06A7
6928 #define VL53L1_RANGING_CORE__STATIC_HW_VALUE 0x06A8
6935 #define VL53L1_RANGING_CORE__FORCE_CONTINUOUS_AMBIENT 0x06A9
6942 #define VL53L1_RANGING_CORE__TEST_PHASE_SELECT_TO_FILTER 0x06AA
6949 #define VL53L1_RANGING_CORE__TEST_PHASE_SELECT_TO_TIMING_GEN 0x06AB
6956 #define VL53L1_RANGING_CORE__INITIAL_PHASE_VALUE_1 0x06AC
6963 #define VL53L1_RANGING_CORE__INITIAL_PHASE_VALUE_REF_1 0x06AD
6970 #define VL53L1_RANGING_CORE__FORCE_UP_IN 0x06AE
6977 #define VL53L1_RANGING_CORE__FORCE_DN_IN 0x06AF
6984 #define VL53L1_RANGING_CORE__STATIC_UP_VALUE_1 0x06B0
6991 #define VL53L1_RANGING_CORE__STATIC_UP_VALUE_REF_1 0x06B1
6998 #define VL53L1_RANGING_CORE__STATIC_DN_VALUE_1 0x06B2
7005 #define VL53L1_RANGING_CORE__STATIC_DN_VALUE_REF_1 0x06B3
7012 #define VL53L1_RANGING_CORE__MONITOR_UP_DN 0x06B4
7019 #define VL53L1_RANGING_CORE__INVERT_UP_DN 0x06B5
7026 #define VL53L1_RANGING_CORE__CPUMP_1 0x06B6
7033 #define VL53L1_RANGING_CORE__CPUMP_2 0x06B7
7040 #define VL53L1_RANGING_CORE__CPUMP_3 0x06B8
7047 #define VL53L1_RANGING_CORE__OSC_1 0x06B9
7054 #define VL53L1_RANGING_CORE__PLL_1 0x06BB
7061 #define VL53L1_RANGING_CORE__PLL_2 0x06BC
7068 #define VL53L1_RANGING_CORE__REFERENCE_1 0x06BD
7075 #define VL53L1_RANGING_CORE__REFERENCE_3 0x06BF
7082 #define VL53L1_RANGING_CORE__REFERENCE_4 0x06C0
7089 #define VL53L1_RANGING_CORE__REFERENCE_5 0x06C1
7096 #define VL53L1_RANGING_CORE__REGAVDD1V2 0x06C3
7103 #define VL53L1_RANGING_CORE__CALIB_1 0x06C4
7110 #define VL53L1_RANGING_CORE__CALIB_2 0x06C5
7117 #define VL53L1_RANGING_CORE__CALIB_3 0x06C6
7124 #define VL53L1_RANGING_CORE__TST_MUX_SEL1 0x06C9
7131 #define VL53L1_RANGING_CORE__TST_MUX_SEL2 0x06CA
7138 #define VL53L1_RANGING_CORE__TST_MUX 0x06CB
7145 #define VL53L1_RANGING_CORE__GPIO_OUT_TESTMUX 0x06CC
7152 #define VL53L1_RANGING_CORE__CUSTOM_FE 0x06CD
7159 #define VL53L1_RANGING_CORE__CUSTOM_FE_2 0x06CE
7166 #define VL53L1_RANGING_CORE__SPAD_READOUT 0x06CF
7173 #define VL53L1_RANGING_CORE__SPAD_READOUT_1 0x06D0
7180 #define VL53L1_RANGING_CORE__SPAD_READOUT_2 0x06D1
7187 #define VL53L1_RANGING_CORE__SPAD_PS 0x06D2
7194 #define VL53L1_RANGING_CORE__LASER_SAFETY_2 0x06D4
7201 #define VL53L1_RANGING_CORE__NVM_CTRL__MODE 0x0780
7208 #define VL53L1_RANGING_CORE__NVM_CTRL__PDN 0x0781
7215 #define VL53L1_RANGING_CORE__NVM_CTRL__PROGN 0x0782
7222 #define VL53L1_RANGING_CORE__NVM_CTRL__READN 0x0783
7229 #define VL53L1_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB 0x0784
7236 #define VL53L1_RANGING_CORE__NVM_CTRL__PULSE_WIDTH_LSB 0x0785
7243 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_RISE_MSB 0x0786
7250 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_RISE_LSB 0x0787
7257 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_FALL_MSB 0x0788
7264 #define VL53L1_RANGING_CORE__NVM_CTRL__HV_FALL_LSB 0x0789
7271 #define VL53L1_RANGING_CORE__NVM_CTRL__TST 0x078A
7278 #define VL53L1_RANGING_CORE__NVM_CTRL__TESTREAD 0x078B
7285 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_MMM 0x078C
7292 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_LMM 0x078D
7299 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_LLM 0x078E
7306 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAIN_LLL 0x078F
7313 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_MMM 0x0790
7320 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_LMM 0x0791
7327 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_LLM 0x0792
7334 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_LLL 0x0793
7341 #define VL53L1_RANGING_CORE__NVM_CTRL__ADDR 0x0794
7348 #define VL53L1_RANGING_CORE__NVM_CTRL__DATAOUT_ECC 0x0795
7355 #define VL53L1_RANGING_CORE__RET_SPAD_EN_0 0x0796
7362 #define VL53L1_RANGING_CORE__RET_SPAD_EN_1 0x0797
7369 #define VL53L1_RANGING_CORE__RET_SPAD_EN_2 0x0798
7376 #define VL53L1_RANGING_CORE__RET_SPAD_EN_3 0x0799
7383 #define VL53L1_RANGING_CORE__RET_SPAD_EN_4 0x079A
7390 #define VL53L1_RANGING_CORE__RET_SPAD_EN_5 0x079B
7397 #define VL53L1_RANGING_CORE__RET_SPAD_EN_6 0x079C
7404 #define VL53L1_RANGING_CORE__RET_SPAD_EN_7 0x079D
7411 #define VL53L1_RANGING_CORE__RET_SPAD_EN_8 0x079E
7418 #define VL53L1_RANGING_CORE__RET_SPAD_EN_9 0x079F
7425 #define VL53L1_RANGING_CORE__RET_SPAD_EN_10 0x07A0
7432 #define VL53L1_RANGING_CORE__RET_SPAD_EN_11 0x07A1
7439 #define VL53L1_RANGING_CORE__RET_SPAD_EN_12 0x07A2
7446 #define VL53L1_RANGING_CORE__RET_SPAD_EN_13 0x07A3
7453 #define VL53L1_RANGING_CORE__RET_SPAD_EN_14 0x07A4
7460 #define VL53L1_RANGING_CORE__RET_SPAD_EN_15 0x07A5
7467 #define VL53L1_RANGING_CORE__RET_SPAD_EN_16 0x07A6
7474 #define VL53L1_RANGING_CORE__RET_SPAD_EN_17 0x07A7
7481 #define VL53L1_RANGING_CORE__SPAD_SHIFT_EN 0x07BA
7488 #define VL53L1_RANGING_CORE__SPAD_DISABLE_CTRL 0x07BB
7495 #define VL53L1_RANGING_CORE__SPAD_EN_SHIFT_OUT_DEBUG 0x07BC
7502 #define VL53L1_RANGING_CORE__SPI_MODE 0x07BD
7509 #define VL53L1_RANGING_CORE__GPIO_DIR 0x07BE
7516 #define VL53L1_RANGING_CORE__VCSEL_PERIOD 0x0880
7523 #define VL53L1_RANGING_CORE__VCSEL_START 0x0881
7530 #define VL53L1_RANGING_CORE__VCSEL_STOP 0x0882
7537 #define VL53L1_RANGING_CORE__VCSEL_1 0x0885
7544 #define VL53L1_RANGING_CORE__VCSEL_STATUS 0x088D
7551 #define VL53L1_RANGING_CORE__STATUS 0x0980
7558 #define VL53L1_RANGING_CORE__LASER_CONTINUITY_STATE 0x0981
7565 #define VL53L1_RANGING_CORE__RANGE_1_MMM 0x0982
7572 #define VL53L1_RANGING_CORE__RANGE_1_LMM 0x0983
7579 #define VL53L1_RANGING_CORE__RANGE_1_LLM 0x0984
7586 #define VL53L1_RANGING_CORE__RANGE_1_LLL 0x0985
7593 #define VL53L1_RANGING_CORE__RANGE_REF_1_MMM 0x0986
7600 #define VL53L1_RANGING_CORE__RANGE_REF_1_LMM 0x0987
7607 #define VL53L1_RANGING_CORE__RANGE_REF_1_LLM 0x0988
7614 #define VL53L1_RANGING_CORE__RANGE_REF_1_LLL 0x0989
7621 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_MMM 0x098A
7628 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LMM 0x098B
7635 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLM 0x098C
7642 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLL 0x098D
7649 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_MMM 0x098E
7656 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LMM 0x098F
7663 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLM 0x0990
7670 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLL 0x0991
7677 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_MMM 0x0992
7684 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LMM 0x0993
7691 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLM 0x0994
7698 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLL 0x0995
7705 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_MM 0x0996
7712 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LM 0x0997
7719 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LL 0x0998
7726 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_MM 0x0999
7733 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_LM 0x099A
7740 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_LL 0x099B
7747 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_MMM 0x099C
7754 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LMM 0x099D
7761 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLM 0x099E
7768 #define VL53L1_RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLL 0x099F
7775 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_MMM 0x09A0
7782 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LMM 0x09A1
7789 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLM 0x09A2
7796 #define VL53L1_RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLL 0x09A3
7803 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_MMM 0x09A4
7810 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LMM 0x09A5
7817 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLM 0x09A6
7824 #define VL53L1_RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLL 0x09A7
7831 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_MM 0x09A8
7838 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LM 0x09A9
7845 #define VL53L1_RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LL 0x09AA
7852 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_REF_MM 0x09AB
7859 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_REF_LM 0x09AC
7866 #define VL53L1_RANGING_CORE__AMBIENT_MISMATCH_REF_LL 0x09AD
7873 #define VL53L1_RANGING_CORE__GPIO_CONFIG__A0 0x0A00
7880 #define VL53L1_RANGING_CORE__RESET_CONTROL__A0 0x0A01
7887 #define VL53L1_RANGING_CORE__INTR_MANAGER__A0 0x0A02
7894 #define VL53L1_RANGING_CORE__POWER_FSM_TIME_OSC__A0 0x0A06
7901 #define VL53L1_RANGING_CORE__VCSEL_ATEST__A0 0x0A07
7908 #define VL53L1_RANGING_CORE__VCSEL_PERIOD_CLIPPED__A0 0x0A08
7915 #define VL53L1_RANGING_CORE__VCSEL_STOP_CLIPPED__A0 0x0A09
7922 #define VL53L1_RANGING_CORE__CALIB_2__A0 0x0A0A
7929 #define VL53L1_RANGING_CORE__STOP_CONDITION__A0 0x0A0B
7936 #define VL53L1_RANGING_CORE__STATUS_RESET__A0 0x0A0C
7943 #define VL53L1_RANGING_CORE__READOUT_CFG__A0 0x0A0D
7950 #define VL53L1_RANGING_CORE__WINDOW_SETTING__A0 0x0A0E
7957 #define VL53L1_RANGING_CORE__VCSEL_DELAY__A0 0x0A1A
7964 #define VL53L1_RANGING_CORE__REFERENCE_2__A0 0x0A1B
7971 #define VL53L1_RANGING_CORE__REGAVDD1V2__A0 0x0A1D
7978 #define VL53L1_RANGING_CORE__TST_MUX__A0 0x0A1F
7985 #define VL53L1_RANGING_CORE__CUSTOM_FE_2__A0 0x0A20
7992 #define VL53L1_RANGING_CORE__SPAD_READOUT__A0 0x0A21
7999 #define VL53L1_RANGING_CORE__CPUMP_1__A0 0x0A22
8006 #define VL53L1_RANGING_CORE__SPARE_REGISTER__A0 0x0A23
8013 #define VL53L1_RANGING_CORE__VCSEL_CONT_STAGE5_BYPASS__A0 0x0A24
8020 #define VL53L1_RANGING_CORE__RET_SPAD_EN_18 0x0A25
8027 #define VL53L1_RANGING_CORE__RET_SPAD_EN_19 0x0A26
8034 #define VL53L1_RANGING_CORE__RET_SPAD_EN_20 0x0A27
8041 #define VL53L1_RANGING_CORE__RET_SPAD_EN_21 0x0A28
8048 #define VL53L1_RANGING_CORE__RET_SPAD_EN_22 0x0A29
8055 #define VL53L1_RANGING_CORE__RET_SPAD_EN_23 0x0A2A
8062 #define VL53L1_RANGING_CORE__RET_SPAD_EN_24 0x0A2B
8069 #define VL53L1_RANGING_CORE__RET_SPAD_EN_25 0x0A2C
8076 #define VL53L1_RANGING_CORE__RET_SPAD_EN_26 0x0A2D
8083 #define VL53L1_RANGING_CORE__RET_SPAD_EN_27 0x0A2E
8090 #define VL53L1_RANGING_CORE__RET_SPAD_EN_28 0x0A2F
8097 #define VL53L1_RANGING_CORE__RET_SPAD_EN_29 0x0A30
8104 #define VL53L1_RANGING_CORE__RET_SPAD_EN_30 0x0A31
8111 #define VL53L1_RANGING_CORE__RET_SPAD_EN_31 0x0A32
8118 #define VL53L1_RANGING_CORE__REF_SPAD_EN_0__EWOK 0x0A33
8125 #define VL53L1_RANGING_CORE__REF_SPAD_EN_1__EWOK 0x0A34
8132 #define VL53L1_RANGING_CORE__REF_SPAD_EN_2__EWOK 0x0A35
8139 #define VL53L1_RANGING_CORE__REF_SPAD_EN_3__EWOK 0x0A36
8146 #define VL53L1_RANGING_CORE__REF_SPAD_EN_4__EWOK 0x0A37
8153 #define VL53L1_RANGING_CORE__REF_SPAD_EN_5__EWOK 0x0A38
8160 #define VL53L1_RANGING_CORE__REF_EN_START_SELECT 0x0A39
8167 #define VL53L1_RANGING_CORE__REGDVDD1V2_ATEST__EWOK 0x0A41
8174 #define VL53L1_SOFT_RESET_GO1 0x0B00
8181 #define VL53L1_PRIVATE__PATCH_BASE_ADDR_RSLV 0x0E00
8188 #define VL53L1_PREV_SHADOW_RESULT__INTERRUPT_STATUS 0x0ED0
8205 #define VL53L1_PREV_SHADOW_RESULT__RANGE_STATUS 0x0ED1
8223 #define VL53L1_PREV_SHADOW_RESULT__REPORT_STATUS 0x0ED2
8238 #define VL53L1_PREV_SHADOW_RESULT__STREAM_COUNT 0x0ED3
8253 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0ED4
8268 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0ED4
8275 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0ED5
8282 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0ED6
8297 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0ED6
8304 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0ED7
8311 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0ED8
8326 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0ED8
8333 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0ED9
8340 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD0 0x0EDA
8355 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD0_HI 0x0EDA
8362 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD0_LO 0x0EDB
8369 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD0 0x0EDC
8384 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD0_HI 0x0EDC
8391 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD0_LO 0x0EDD
8398 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0EDE
8413 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0EDE
8420 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0EDF
8427 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0EE0
8442 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0EE0
8449 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0EE1
8456 #define VL53L1_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE2
8471 #define VL53L1_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE2
8478 #define VL53L1_PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE3
8485 #define VL53L1_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0EE4
8500 #define VL53L1_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0EE4
8507 #define VL53L1_PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0EE5
8514 #define VL53L1_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0EE6
8529 #define VL53L1_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0EE6
8536 #define VL53L1_PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0EE7
8543 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0EE8
8558 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0EE8
8565 #define VL53L1_PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0EE9
8572 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0EEA
8587 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0EEA
8594 #define VL53L1_PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0EEB
8601 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0EEC
8616 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0EEC
8623 #define VL53L1_PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0EED
8630 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD1 0x0EEE
8645 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD1_HI 0x0EEE
8652 #define VL53L1_PREV_SHADOW_RESULT__SIGMA_SD1_LO 0x0EEF
8659 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD1 0x0EF0
8674 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD1_HI 0x0EF0
8681 #define VL53L1_PREV_SHADOW_RESULT__PHASE_SD1_LO 0x0EF1
8688 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0EF2
8703 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0EF2
8710 #define VL53L1_PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0EF3
8717 #define VL53L1_PREV_SHADOW_RESULT__SPARE_0_SD1 0x0EF4
8732 #define VL53L1_PREV_SHADOW_RESULT__SPARE_0_SD1_HI 0x0EF4
8739 #define VL53L1_PREV_SHADOW_RESULT__SPARE_0_SD1_LO 0x0EF5
8746 #define VL53L1_PREV_SHADOW_RESULT__SPARE_1_SD1 0x0EF6
8761 #define VL53L1_PREV_SHADOW_RESULT__SPARE_1_SD1_HI 0x0EF6
8768 #define VL53L1_PREV_SHADOW_RESULT__SPARE_1_SD1_LO 0x0EF7
8775 #define VL53L1_PREV_SHADOW_RESULT__SPARE_2_SD1 0x0EF8
8790 #define VL53L1_PREV_SHADOW_RESULT__SPARE_2_SD1_HI 0x0EF8
8797 #define VL53L1_PREV_SHADOW_RESULT__SPARE_2_SD1_LO 0x0EF9
8804 #define VL53L1_PREV_SHADOW_RESULT__SPARE_3_SD1 0x0EFA
8819 #define VL53L1_PREV_SHADOW_RESULT__SPARE_3_SD1_HI 0x0EFA
8826 #define VL53L1_PREV_SHADOW_RESULT__SPARE_3_SD1_LO 0x0EFB
8833 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0EFC
8848 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0EFC
8855 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0EFD
8862 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0EFE
8869 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0EFF
8876 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0F00
8891 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0F00
8898 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0F01
8905 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0F02
8912 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0F03
8919 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0F04
8934 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0F04
8941 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0F05
8948 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0F06
8955 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0F07
8962 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0F08
8977 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0F08
8984 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0F09
8991 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0F0A
8998 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0F0B
9005 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0F0C
9020 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0F0C
9027 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0F0D
9034 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0F0E
9041 #define VL53L1_PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0F0F
9048 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0F10
9063 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0F10
9070 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0F11
9077 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0F12
9084 #define VL53L1_PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0F13
9091 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0F14
9106 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0F14
9113 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0F15
9120 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0F16
9127 #define VL53L1_PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0F17
9134 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0F18
9149 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0F18
9156 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0F19
9163 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0F1A
9170 #define VL53L1_PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0F1B
9177 #define VL53L1_PREV_SHADOW_RESULT_CORE__SPARE_0 0x0F1C
9192 #define VL53L1_RESULT__DEBUG_STATUS 0x0F20
9207 #define VL53L1_RESULT__DEBUG_STAGE 0x0F21
9222 #define VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH 0x0F24
9237 #define VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH_HI 0x0F24
9244 #define VL53L1_GPH__SYSTEM__THRESH_RATE_HIGH_LO 0x0F25
9251 #define VL53L1_GPH__SYSTEM__THRESH_RATE_LOW 0x0F26
9266 #define VL53L1_GPH__SYSTEM__THRESH_RATE_LOW_HI 0x0F26
9273 #define VL53L1_GPH__SYSTEM__THRESH_RATE_LOW_LO 0x0F27
9280 #define VL53L1_GPH__SYSTEM__INTERRUPT_CONFIG_GPIO 0x0F28
9300 #define VL53L1_GPH__DSS_CONFIG__ROI_MODE_CONTROL 0x0F2F
9316 #define VL53L1_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT 0x0F30
9331 #define VL53L1_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI 0x0F30
9338 #define VL53L1_GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO 0x0F31
9345 #define VL53L1_GPH__DSS_CONFIG__MANUAL_BLOCK_SELECT 0x0F32
9360 #define VL53L1_GPH__DSS_CONFIG__MAX_SPADS_LIMIT 0x0F33
9375 #define VL53L1_GPH__DSS_CONFIG__MIN_SPADS_LIMIT 0x0F34
9390 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI 0x0F36
9405 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_A_LO 0x0F37
9420 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_B_HI 0x0F38
9435 #define VL53L1_GPH__MM_CONFIG__TIMEOUT_MACROP_B_LO 0x0F39
9450 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_HI 0x0F3A
9465 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_LO 0x0F3B
9480 #define VL53L1_GPH__RANGE_CONFIG__VCSEL_PERIOD_A 0x0F3C
9495 #define VL53L1_GPH__RANGE_CONFIG__VCSEL_PERIOD_B 0x0F3D
9510 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_HI 0x0F3E
9525 #define VL53L1_GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_LO 0x0F3F
9540 #define VL53L1_GPH__RANGE_CONFIG__SIGMA_THRESH 0x0F40
9555 #define VL53L1_GPH__RANGE_CONFIG__SIGMA_THRESH_HI 0x0F40
9562 #define VL53L1_GPH__RANGE_CONFIG__SIGMA_THRESH_LO 0x0F41
9569 #define VL53L1_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS 0x0F42
9584 #define VL53L1_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI 0x0F42
9591 #define VL53L1_GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO 0x0F43
9598 #define VL53L1_GPH__RANGE_CONFIG__VALID_PHASE_LOW 0x0F44
9613 #define VL53L1_GPH__RANGE_CONFIG__VALID_PHASE_HIGH 0x0F45
9628 #define VL53L1_FIRMWARE__INTERNAL_STREAM_COUNT_DIV 0x0F46
9643 #define VL53L1_FIRMWARE__INTERNAL_STREAM_COUNTER_VAL 0x0F47
9658 #define VL53L1_DSS_CALC__ROI_CTRL 0x0F54
9674 #define VL53L1_DSS_CALC__SPARE_1 0x0F55
9689 #define VL53L1_DSS_CALC__SPARE_2 0x0F56
9704 #define VL53L1_DSS_CALC__SPARE_3 0x0F57
9719 #define VL53L1_DSS_CALC__SPARE_4 0x0F58
9734 #define VL53L1_DSS_CALC__SPARE_5 0x0F59
9749 #define VL53L1_DSS_CALC__SPARE_6 0x0F5A
9764 #define VL53L1_DSS_CALC__SPARE_7 0x0F5B
9779 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_0 0x0F5C
9794 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_1 0x0F5D
9809 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_2 0x0F5E
9824 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_3 0x0F5F
9839 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_4 0x0F60
9854 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_5 0x0F61
9869 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_6 0x0F62
9884 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_7 0x0F63
9899 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_8 0x0F64
9914 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_9 0x0F65
9929 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_10 0x0F66
9944 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_11 0x0F67
9959 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_12 0x0F68
9974 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_13 0x0F69
9989 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_14 0x0F6A
10004 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_15 0x0F6B
10019 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_16 0x0F6C
10034 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_17 0x0F6D
10049 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_18 0x0F6E
10064 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_19 0x0F6F
10079 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_20 0x0F70
10094 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_21 0x0F71
10109 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_22 0x0F72
10124 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_23 0x0F73
10139 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_24 0x0F74
10154 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_25 0x0F75
10169 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_26 0x0F76
10184 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_27 0x0F77
10199 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_28 0x0F78
10214 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_29 0x0F79
10229 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_30 0x0F7A
10244 #define VL53L1_DSS_CALC__USER_ROI_SPAD_EN_31 0x0F7B
10259 #define VL53L1_DSS_CALC__USER_ROI_0 0x0F7C
10274 #define VL53L1_DSS_CALC__USER_ROI_1 0x0F7D
10289 #define VL53L1_DSS_CALC__MODE_ROI_0 0x0F7E
10304 #define VL53L1_DSS_CALC__MODE_ROI_1 0x0F7F
10319 #define VL53L1_SIGMA_ESTIMATOR_CALC__SPARE_0 0x0F80
10334 #define VL53L1_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS 0x0F82
10349 #define VL53L1_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_HI 0x0F82
10356 #define VL53L1_VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_LO 0x0F83
10363 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF 0x0F84
10378 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_3 0x0F84
10385 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_2 0x0F85
10392 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_1 0x0F86
10399 #define VL53L1_VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_0 0x0F87
10406 #define VL53L1_PHASECAL_RESULT__PHASE_OUTPUT_REF 0x0F88
10421 #define VL53L1_PHASECAL_RESULT__PHASE_OUTPUT_REF_HI 0x0F88
10428 #define VL53L1_PHASECAL_RESULT__PHASE_OUTPUT_REF_LO 0x0F89
10435 #define VL53L1_DSS_RESULT__TOTAL_RATE_PER_SPAD 0x0F8A
10450 #define VL53L1_DSS_RESULT__TOTAL_RATE_PER_SPAD_HI 0x0F8A
10457 #define VL53L1_DSS_RESULT__TOTAL_RATE_PER_SPAD_LO 0x0F8B
10464 #define VL53L1_DSS_RESULT__ENABLED_BLOCKS 0x0F8C
10479 #define VL53L1_DSS_RESULT__NUM_REQUESTED_SPADS 0x0F8E
10494 #define VL53L1_DSS_RESULT__NUM_REQUESTED_SPADS_HI 0x0F8E
10501 #define VL53L1_DSS_RESULT__NUM_REQUESTED_SPADS_LO 0x0F8F
10508 #define VL53L1_MM_RESULT__INNER_INTERSECTION_RATE 0x0F92
10523 #define VL53L1_MM_RESULT__INNER_INTERSECTION_RATE_HI 0x0F92
10530 #define VL53L1_MM_RESULT__INNER_INTERSECTION_RATE_LO 0x0F93
10537 #define VL53L1_MM_RESULT__OUTER_COMPLEMENT_RATE 0x0F94
10552 #define VL53L1_MM_RESULT__OUTER_COMPLEMENT_RATE_HI 0x0F94
10559 #define VL53L1_MM_RESULT__OUTER_COMPLEMENT_RATE_LO 0x0F95
10566 #define VL53L1_MM_RESULT__TOTAL_OFFSET 0x0F96
10581 #define VL53L1_MM_RESULT__TOTAL_OFFSET_HI 0x0F96
10588 #define VL53L1_MM_RESULT__TOTAL_OFFSET_LO 0x0F97
10595 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS 0x0F98
10610 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_3 0x0F98
10617 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_2 0x0F99
10624 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_1 0x0F9A
10631 #define VL53L1_XTALK_CALC__XTALK_FOR_ENABLED_SPADS_0 0x0F9B
10638 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS 0x0F9C
10653 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_3 0x0F9C
10660 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_2 0x0F9D
10667 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_1 0x0F9E
10674 #define VL53L1_XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_0 0x0F9F
10681 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS 0x0FA0
10696 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_3 0x0FA0
10703 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_2 0x0FA1
10710 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_1 0x0FA2
10717 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_0 0x0FA3
10724 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS 0x0FA4
10739 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_3 0x0FA4
10746 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_2 0x0FA5
10753 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_1 0x0FA6
10760 #define VL53L1_XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_0 0x0FA7
10767 #define VL53L1_RANGE_RESULT__ACCUM_PHASE 0x0FA8
10782 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_3 0x0FA8
10789 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_2 0x0FA9
10796 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_1 0x0FAA
10803 #define VL53L1_RANGE_RESULT__ACCUM_PHASE_0 0x0FAB
10810 #define VL53L1_RANGE_RESULT__OFFSET_CORRECTED_RANGE 0x0FAC
10825 #define VL53L1_RANGE_RESULT__OFFSET_CORRECTED_RANGE_HI 0x0FAC
10832 #define VL53L1_RANGE_RESULT__OFFSET_CORRECTED_RANGE_LO 0x0FAD
10839 #define VL53L1_SHADOW_PHASECAL_RESULT__VCSEL_START 0x0FAE
10854 #define VL53L1_SHADOW_RESULT__INTERRUPT_STATUS 0x0FB0
10871 #define VL53L1_SHADOW_RESULT__RANGE_STATUS 0x0FB1
10889 #define VL53L1_SHADOW_RESULT__REPORT_STATUS 0x0FB2
10904 #define VL53L1_SHADOW_RESULT__STREAM_COUNT 0x0FB3
10919 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FB4
10934 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FB4
10941 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FB5
10948 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FB6
10963 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FB6
10970 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FB7
10977 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0 0x0FB8
10992 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI 0x0FB8
10999 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO 0x0FB9
11006 #define VL53L1_SHADOW_RESULT__SIGMA_SD0 0x0FBA
11021 #define VL53L1_SHADOW_RESULT__SIGMA_SD0_HI 0x0FBA
11028 #define VL53L1_SHADOW_RESULT__SIGMA_SD0_LO 0x0FBB
11035 #define VL53L1_SHADOW_RESULT__PHASE_SD0 0x0FBC
11050 #define VL53L1_SHADOW_RESULT__PHASE_SD0_HI 0x0FBC
11057 #define VL53L1_SHADOW_RESULT__PHASE_SD0_LO 0x0FBD
11064 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0 0x0FBE
11079 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI 0x0FBE
11086 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO 0x0FBF
11093 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0 0x0FC0
11108 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI 0x0FC0
11115 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO 0x0FC1
11122 #define VL53L1_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC2
11137 #define VL53L1_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC2
11144 #define VL53L1_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC3
11151 #define VL53L1_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0 0x0FC4
11166 #define VL53L1_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI 0x0FC4
11173 #define VL53L1_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO 0x0FC5
11180 #define VL53L1_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0 0x0FC6
11195 #define VL53L1_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI 0x0FC6
11202 #define VL53L1_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO 0x0FC7
11209 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1 0x0FC8
11224 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI 0x0FC8
11231 #define VL53L1_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO 0x0FC9
11238 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1 0x0FCA
11253 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI 0x0FCA
11260 #define VL53L1_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO 0x0FCB
11267 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1 0x0FCC
11282 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI 0x0FCC
11289 #define VL53L1_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO 0x0FCD
11296 #define VL53L1_SHADOW_RESULT__SIGMA_SD1 0x0FCE
11311 #define VL53L1_SHADOW_RESULT__SIGMA_SD1_HI 0x0FCE
11318 #define VL53L1_SHADOW_RESULT__SIGMA_SD1_LO 0x0FCF
11325 #define VL53L1_SHADOW_RESULT__PHASE_SD1 0x0FD0
11340 #define VL53L1_SHADOW_RESULT__PHASE_SD1_HI 0x0FD0
11347 #define VL53L1_SHADOW_RESULT__PHASE_SD1_LO 0x0FD1
11354 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1 0x0FD2
11369 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI 0x0FD2
11376 #define VL53L1_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO 0x0FD3
11383 #define VL53L1_SHADOW_RESULT__SPARE_0_SD1 0x0FD4
11398 #define VL53L1_SHADOW_RESULT__SPARE_0_SD1_HI 0x0FD4
11405 #define VL53L1_SHADOW_RESULT__SPARE_0_SD1_LO 0x0FD5
11412 #define VL53L1_SHADOW_RESULT__SPARE_1_SD1 0x0FD6
11427 #define VL53L1_SHADOW_RESULT__SPARE_1_SD1_HI 0x0FD6
11434 #define VL53L1_SHADOW_RESULT__SPARE_1_SD1_LO 0x0FD7
11441 #define VL53L1_SHADOW_RESULT__SPARE_2_SD1 0x0FD8
11456 #define VL53L1_SHADOW_RESULT__SPARE_2_SD1_HI 0x0FD8
11463 #define VL53L1_SHADOW_RESULT__SPARE_2_SD1_LO 0x0FD9
11470 #define VL53L1_SHADOW_RESULT__SPARE_3_SD1 0x0FDA
11485 #define VL53L1_SHADOW_RESULT__THRESH_INFO 0x0FDB
11501 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0 0x0FDC
11516 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3 0x0FDC
11523 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2 0x0FDD
11530 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1 0x0FDE
11537 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0 0x0FDF
11544 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0 0x0FE0
11559 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3 0x0FE0
11566 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2 0x0FE1
11573 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1 0x0FE2
11580 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0 0x0FE3
11587 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0 0x0FE4
11602 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3 0x0FE4
11609 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2 0x0FE5
11616 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1 0x0FE6
11623 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0 0x0FE7
11630 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0 0x0FE8
11645 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3 0x0FE8
11652 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2 0x0FE9
11659 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1 0x0FEA
11666 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0 0x0FEB
11673 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1 0x0FEC
11688 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3 0x0FEC
11695 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2 0x0FED
11702 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1 0x0FEE
11709 #define VL53L1_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0 0x0FEF
11716 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1 0x0FF0
11731 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3 0x0FF0
11738 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2 0x0FF1
11745 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1 0x0FF2
11752 #define VL53L1_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0 0x0FF3
11759 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1 0x0FF4
11774 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3 0x0FF4
11781 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2 0x0FF5
11788 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1 0x0FF6
11795 #define VL53L1_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0 0x0FF7
11802 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1 0x0FF8
11817 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3 0x0FF8
11824 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2 0x0FF9
11831 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1 0x0FFA
11838 #define VL53L1_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0 0x0FFB
11845 #define VL53L1_SHADOW_RESULT_CORE__SPARE_0 0x0FFC
11860 #define VL53L1_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI 0x0FFE
11875 #define VL53L1_SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO 0x0FFF
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autogenerated on Fri Aug 2 2024 08:35:54