pmu_11xx.h

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/*
 * @brief LPC11xx PMU chip driver
 *
 * @note
 * Copyright(C) NXP Semiconductors, 2012
 * All rights reserved.
 *
 * @par
 * Software that is described herein is for illustrative purposes only
 * which provides customers with programming information regarding the
 * LPC products.  This software is supplied "AS IS" without any warranties of
 * any kind, and NXP Semiconductors and its licensor disclaim any and
 * all warranties, express or implied, including all implied warranties of
 * merchantability, fitness for a particular purpose and non-infringement of
 * intellectual property rights.  NXP Semiconductors assumes no responsibility
 * or liability for the use of the software, conveys no license or rights under any
 * patent, copyright, mask work right, or any other intellectual property rights in
 * or to any products. NXP Semiconductors reserves the right to make changes
 * in the software without notification. NXP Semiconductors also makes no
 * representation or warranty that such application will be suitable for the
 * specified use without further testing or modification.
 *
 * @par
 * Permission to use, copy, modify, and distribute this software and its
 * documentation is hereby granted, under NXP Semiconductors' and its
 * licensor's relevant copyrights in the software, without fee, provided that it
 * is used in conjunction with NXP Semiconductors microcontrollers.  This
 * copyright, permission, and disclaimer notice must appear in all copies of
 * this code.
 */
 
#ifndef __PMU_11XX_H_
#define __PMU_11XX_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX) || defined(CHIP_LPC1125)
#if defined(CHIP_LPC1125)
#error "LPC1125 support for the PMU driver is not ready"
#endif
 
typedef struct {
        __IO uint32_t PCON;             
        __IO uint32_t GPREG[4]; 
} LPC_PMU_T;
 
typedef enum CHIP_PMU_MCUPOWER {
        PMU_MCU_SLEEP = 0,                      
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
        PMU_MCU_DEEP_SLEEP,                     
        PMU_MCU_POWER_DOWN,                     
        PMU_MCU_DEEP_PWRDOWN            
#elif defined(CHIP_LPC11CXX)
        PMU_MCU_DEEP_PWRDOWN = 3        
#endif
} CHIP_PMU_MCUPOWER_T;
 
#define PMU_PCON_PM_SLEEP                       (0x0)           
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
#define PMU_PCON_PM_DEEPSLEEP           (0x1)           
#define PMU_PCON_PM_POWERDOWN           (0x2)           
#define PMU_PCON_PM_DEEPPOWERDOWN       (0x3)           
#elif defined(CHIP_LPC11CXX)
#define PMU_PCON_PM_DEEPPOWERDOWN   (0x2)
#endif
#define PMU_PCON_SLEEPFLAG                      (1 << 8)        
#define PMU_PCON_DPDFLAG                        (1 << 11)       
STATIC INLINE void Chip_PMU_WriteGPREG(LPC_PMU_T *pPMU, uint8_t regIndex, uint32_t value)
{
        pPMU->GPREG[regIndex] = value;
}
 
STATIC INLINE uint32_t Chip_PMU_ReadGPREG(LPC_PMU_T *pPMU, uint8_t regIndex)
{
        return pPMU->GPREG[regIndex];
}
 
void Chip_PMU_SleepState(LPC_PMU_T *pPMU);
 
#if defined(CHIP_LPC11AXX) || defined(CHIP_LPC11EXX) || defined(CHIP_LPC11UXX)
 
void Chip_PMU_DeepSleepState(LPC_PMU_T *pPMU);
 
void Chip_PMU_PowerDownState(LPC_PMU_T *pPMU);
#endif
 
void Chip_PMU_DeepPowerDownState(LPC_PMU_T *pPMU);
 
void Chip_PMU_Sleep(LPC_PMU_T *pPMU, CHIP_PMU_MCUPOWER_T SleepMode);
 
STATIC INLINE uint32_t Chip_PMU_GetSleepFlags(LPC_PMU_T *pPMU)
{
        return (pPMU->PCON & (PMU_PCON_SLEEPFLAG | PMU_PCON_DPDFLAG));
}
 
STATIC INLINE void Chip_PMU_ClearSleepFlags(LPC_PMU_T *pPMU, uint32_t flags)
{
        pPMU->PCON &= ~flags;
}
 
#endif /* defined(CHIP_LPC11AXX) || defined(CHIP_LPC11CXX) || ... */
 
#ifdef __cplusplus
}
#endif
 
#endif /* __PMU_11XX_H_ */