lw_emac.c
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17  * $Id: lw_emac.c 348 2012-10-18 16:41:14Z rtlfrm $
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22 
23 #include <bsp.h>
24 #include <kern.h>
25 #include <config.h>
26 #include <bfin_dma.h>
27 #include <string.h>
28 
29 #include "lw_emac.h"
30 
31 /* MII standard registers.
32  See IEEE Std 802.3-2005 clause 22:
33  "Reconciliation Sublayer (RS) and Media Independent Interface (MII)",
34  section 2.4.1 to 3.
35  http://standards.ieee.org/getieee802/download/802.3-2005_section2.pdf */
36 #define MII_BMCR 0x00 /* Basic Mode Control Register */
37 #define MII_BMSR 0x01 /* Basic Mode Status Register */
38 #define MII_PHYIDR1 0x02 /* PHY Identifier Register 1 */
39 #define MII_PHYIDR2 0x03 /* PHY Identifier Register 2 */
40 #define MII_LPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */
41 
42 /* MII basic mode control register */
43 #define MII_BMCR_RST BIT (15)
44 #define MII_BMCR_ANEG_EN BIT (12)
45 #define MII_BMCR_ANEG_RST BIT (9)
46 
47 /* MII basic mode status register */
48 #define MII_BMSR_ANEGACK BIT (5)
49 #define MII_BMSR_LINK BIT (2)
50 
51 /* MII auto-negotiation advertisement register */
52 #define MII_ANAR_100_FD BIT (8) /* Can do 100BASE-TX full duplex */
53 #define MII_ANAR_10_FD BIT (6) /* Can do 10BASE-T full duplex */
54 
55 /* Management Data Clock (MDC) frequency.
56  * 2.5Mz corresponds to the minimum period for MDC as defined by the standard.
57  * This is independent of whether the PHY is in 10Mbit/s or 100Mbit/s mode.
58  * See Std. IEEE 802.3 (Ethernet) Clause 22.2.2.11 ("management data clock"). */
59 #define PHY_MDC_Hz 2500000
60 #define PHY_RETRIES 3000
61 /* TODO: This might need changing for different boards. Fix? */
62 #define PHY_ADDR 0
63 
64 #define ETH_RX_BUF_SIZE 2
65 #define ETH_TX_BUF_SIZE 1
66 #define ETH_FRAME_SIZE 0x614
67 
68 /* Ethernet MAC register structure */
69 typedef struct bfin_emac_regs
70 {
71  /* Control-Status Register Group */
72  uint32_t opmode; /* operating mode */
73  uint32_t addrlo; /* address low */
74  uint32_t addrhi; /* address high */
75  uint32_t hashlo; /* multicast hash table low */
76  uint32_t hashhi; /* multicast hash table high */
77  uint32_t staadd; /* station management address */
78  uint32_t stadat; /* station management data */
79  uint32_t flc; /* flow control */
80  uint32_t vlan1; /* VLAN1 tag */
81  uint32_t vlan2; /* VLAN2 tag */
83  uint32_t wkup_ctl; /* wakeup frame control and status */
84  uint32_t wkup_ffmsk[4]; /* wakeup frame n byte mask (n == 0,..,3) */
85  uint32_t wkup_ffcmd; /* wakeup frame filter commands */
86  uint32_t wkup_ffoff; /* wakeup frame filter offsets */
87  uint32_t wkup_ffcrc0; /* wakeup frame filter CRC0/1 */
88  uint32_t wkup_ffcrc1; /* wakeup frame filter CRC2/3 */
90  /* System Interface Register Group */
91  uint32_t sysctl; /* system control */
92  uint32_t systat; /* system status */
93  /* Ethernet Frame Status Register Group */
94  uint32_t rx_stat; /* RX Current Frame Status */
95  uint32_t rx_stky; /* RX Sticky Frame Status */
96  uint32_t rx_irqe; /* RX Frame Status Interrupt Enable */
97  uint32_t tx_stat; /* TX Current Frame Status Register */
98  uint32_t tx_stky; /* TT Sticky Frame Status */
99  uint32_t tx_irqe; /* TX Frame Status Interrupt Enable */
100  /* MAC Management Counter Register Group */
101  uint32_t mmc_ctl; /* Management Counters Control */
102  uint32_t mmc_rirqs; /* MMC RX Interrupt Status */
103  uint32_t mmc_rirqe; /* MMC RX Interrupt Enable */
104  uint32_t mmc_tirqs; /* MMC TX Interrupt Status */
105  uint32_t mmc_tirqe; /* MMC TX Interrupt Enable */
107  uint32_t mmc_rxc_ok; /* FramesReceivedOK */
108  uint32_t mmc_rxc_fcs; /* FrameCheckSequenceErrors */
109  uint32_t mmc_rxc_align; /* AlignmentErrors */
110  uint32_t mmc_rxc_octet; /* OctetsReceivedOK */
111  uint32_t mmc_rxc_dmaovf; /* FramesLostDueToIntMACRcvError */
112  uint32_t mmc_rxc_unicst; /* UnicastFramesReceivedOK */
113  uint32_t mmc_rxc_multi; /* MulticastFramesReceivedOK */
114  uint32_t mmc_rxc_broad; /* BroadcastFramesReceivedOK */
115  uint32_t mmc_rxc_lnerri; /* InRangeLengthErrors */
116  uint32_t mmc_rxc_lnerro; /* OutOfRangeLengthField */
117  uint32_t mmc_rxc_long; /* FrameTooLongErrors */
118  uint32_t mmc_rxc_macctl; /* MACControlFramesReceived */
119  uint32_t mmc_rxc_opcode; /* UnsupportedOpcodesReceived */
120  uint32_t mmc_rxc_pause; /* PAUSEMACCtrlFramesReceived */
121  uint32_t mmc_rxc_allfrm; /* FramesReceivedAll */
122  uint32_t mmc_rxc_alloct; /* OctetsReceivedAll */
123  uint32_t mmc_rxc_typed; /* TypedFramesReceived */
124  uint32_t mmc_rxc_short; /* FramesLenLt64Received */
125  uint32_t mmc_rxc_eq64; /* FramesLenEq64Received */
126  uint32_t mmc_rxc_lt128; /* FramesLen65_127Received */
127  uint32_t mmc_rxc_lt256; /* FramesLen128_255Received */
128  uint32_t mmc_rxc_lt512; /* FramesLen256_511Received */
129  uint32_t mmc_rxc_lt1024; /* FramesLen512_1023Received */
130  uint32_t mmc_rxc_ge1024; /* FramesLen1024_MaxReceived */
131  /* TODO: add all registers */
133 
134 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, opmode) == 0x0);
135 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, staadd) == 0x14);
136 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, wkup_ctl) == 0x2c);
137 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, wkup_ffcrc1) == 0x4c);
138 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, sysctl) == 0x60);
139 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, rx_stat) == 0x68);
140 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_ctl) == 0x80);
141 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_tirqe) == 0x90);
142 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_rxc_ok) == 0x100);
143 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_rxc_dmaovf) == 0x110);
144 COMPILETIME_ASSERT (offsetof (bfin_emac_regs_t, mmc_rxc_ge1024) == 0x15c);
145 
146 /* 32-bit aligned struct for ethernet data */
147 typedef struct ethernet_data {
148  uint16_t length; /* When TX = frame data length in bytes, not including 'length'
149  * When RX = 0x0000 padding when using RXDWA
150  */
151  uint8_t data[ETH_FRAME_SIZE]; /* Hold the ethernet frame */
152  uint16_t padding; /* To make the struct 32-bit aligned */
154 
155 COMPILETIME_ASSERT (sizeof (ethernet_data_t) == 0x618) ;
156 
157 static volatile bfin_emac_regs_t * pEth = (bfin_emac_regs_t *) EMAC_OPMODE;
158 
159 /* Buffers for rx and tx DMA operations */
160 static ethernet_data_t rxBuffer[ETH_RX_BUF_SIZE] __attribute__((section(".dma")));
161 static ethernet_data_t txBuffer[ETH_TX_BUF_SIZE] __attribute__((section(".dma")));
162 static volatile uint32_t rxStatusWord[ETH_RX_BUF_SIZE] __attribute__((section(".dma")));
163 static volatile uint32_t txStatusWord[ETH_TX_BUF_SIZE] __attribute__((section(".dma")));
164 static bfin_dma_descriptor_t rxDMADesc[ETH_RX_BUF_SIZE * 2] __attribute__((section(".dma")));
165 static bfin_dma_descriptor_t txDMADesc[ETH_TX_BUF_SIZE * 2] __attribute__((section(".dma")));
166 
167 /* Hold the current index of rx and tx buffers */
169 
170 
171 /* Internal function that writes to a PHY register */
172 static void lw_emac_write_phy_reg(uint8_t phy_addr, uint8_t reg_addr, uint32_t data) {
173  /* Set the flags that should be set reg_addr on PHY */
174  pEth->stadat = data;
175 
176  /* Wait for our turn then initiate writing of stadat to PHY register */
177  pEth->staadd = SET_PHYAD(phy_addr) | SET_REGAD(reg_addr) | STAOP | STABUSY;
178  while (pEth->staadd & STABUSY) ;
179 }
180 
181 /* Internal function that reads from; and returns a PHY register */
182 static uint32_t lw_emac_read_phy_reg(uint8_t phy_addr, uint8_t reg_addr) {
183  pEth->staadd = SET_PHYAD(phy_addr) | SET_REGAD(reg_addr) | STABUSY;
184  while (pEth->staadd & STABUSY) ;
185 
186  return pEth->stadat;
187 }
188 
189 /* Internal function that sets the MAC address */
190 static void lw_emac_set_mac_addr(uint8_t * ethAddr)
191 {
192  pEth->addrlo =
193  ethAddr[0] |
194  ethAddr[1] << 8 |
195  ethAddr[2] << 16 |
196  ethAddr[3] << 24;
197  pEth->addrhi =
198  ethAddr[4] |
199  ethAddr[5] << 8;
200 }
201 
203  uint32_t clock_divisor, sysctl_mdcdiv, phy_stadat, counter;
204 
205  /* CONFIGURE MAC MII PINS */
206 
207  /* Enable PHY Clock Output */
208  *(volatile uint16_t *) VR_CTL |= PHYCLKOE;
209 
210  /* Set all bits to 1 to use MII mode */
211  *(uint16_t *) PORTH_FER = 0xFFFF;
212 
213  /* CONFIGURE MAC REGISTERS */
214 
215  /*
216  * Set the MMC (MAC Management Counter) control register
217  * RTSC = Clear all counters
218  *
219  * Note that counters are not enabled at this time
220  */
221  pEth->mmc_ctl = RSTC;
222 
223  /* Set MAC address */
224  lw_emac_set_mac_addr (ethAddr);
225 
226  clock_divisor = SCLK / PHY_MDC_Hz;
227  sysctl_mdcdiv = clock_divisor / 2 - 1;
228  ASSERT (sysctl_mdcdiv <= 0x3f);
229 
230  rprintp ("PHY ID: %04x %04x\n",
233  );
234 
235  /*
236  * Set the system control register
237  * SET_MDCDIV(x) = Set MDC to 2.5 MHz
238  * RXDWA = Pad incoming frame with 0x0000 as to make the data-part 32-bit aligned
239  * RXCKS = Enable Receive Frame TCP/UDP Checksum Computation
240  */
241  pEth->sysctl = SET_MDCDIV(sysctl_mdcdiv) | RXDWA ;
242 
243  /* CONFIGURE PHY */
244 
245  /*
246  * Set the PHY basic control register
247  * MII_BMCR_ANEG_EN = Auto negotiation on
248  * MII_BMCR_ANEG_RST = Restart the auto-neg process by setting
249  * Speed handled by auto negotiation
250  */
251  phy_stadat = MII_BMCR_ANEG_EN | MII_BMCR_ANEG_RST;
253 
254  /* Loop until link is up or time out after PHY_RETRIES */
255  counter = 0;
256  do {
257  if (counter > PHY_RETRIES) {
258  rprintp("Ethernet link is down\n");
259  return -1;
260  }
261 
262  task_delay (tick_from_ms (10));
263  phy_stadat = lw_emac_read_phy_reg(PHY_ADDR, MII_BMSR);
264 
265  ++counter;
266  } while (!(phy_stadat & MII_BMSR_LINK)) ;
267 
268  /* Check whether link partner can do full duplex or not */
269  phy_stadat = lw_emac_read_phy_reg(PHY_ADDR, MII_LPAR);
270 
271  if (phy_stadat & (MII_ANAR_100_FD | MII_ANAR_10_FD) ) {
272  pEth->opmode = FDMODE;
273  }
274  else {
275  pEth->opmode = 0;
276  }
277 
278  /*
279  * Setup DMA MAC receive/transfer channels with XCOUNT 0 (which we use
280  * together with description based DMA) and XMODIFY 4 (bytes per transfer)
281  */
282  bfin_dma_channel_init(DMA_CHANNEL_EMAC_RX, 0, 4);
283  bfin_dma_channel_init(DMA_CHANNEL_EMAC_TX, 0, 4);
284 
285  return 0;
286 }
287 
288 int bfin_EMAC_init (uint8_t *ethAddr)
289 {
290  rxIdx = txIdx = 0;
291 
292  if (lw_emac_init_registers(ethAddr) != 0) {
293  return -1;
294  }
295 
296  // Reset status words
297  memset ((uint8_t *)rxStatusWord, 0, sizeof(rxStatusWord));
298  memset ((uint8_t *)txStatusWord, 0, sizeof(txStatusWord));
299 
300  txDMADesc[0].next = &txDMADesc[1];
301  txDMADesc[0].start_addr = &txBuffer[0];
302  txDMADesc[0].config = DMA_CONFIG_DMA_EN |
303  DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
304  DMA_CONFIG_NDSIZE(5) |
305  DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
306 
307  txDMADesc[1].next = &txDMADesc[0];
308  txDMADesc[1].start_addr = &txStatusWord[0];
309  txDMADesc[1].config = DMA_CONFIG_DMA_EN |
310  DMA_CONFIG_WNR |
311  DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
312  DMA_CONFIG_NDSIZE(0) |
313  DMA_CONFIG_FLOW(DMA_FLOW_STOP);
314 
315  rxDMADesc[0].next = &rxDMADesc[1];
316  rxDMADesc[0].start_addr = &rxBuffer[0];
317  rxDMADesc[0].config = DMA_CONFIG_DMA_EN |
318  DMA_CONFIG_WNR |
319  DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
320  DMA_CONFIG_NDSIZE(5) |
321  DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
322 
323  rxDMADesc[1].next = &rxDMADesc[2];
324  rxDMADesc[1].start_addr = &rxStatusWord[0];
325  rxDMADesc[1].config = DMA_CONFIG_DMA_EN |
326  DMA_CONFIG_WNR |
327  DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
328  DMA_CONFIG_NDSIZE(5) |
329  DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
330 
331  rxDMADesc[2].next = &rxDMADesc[3];
332  rxDMADesc[2].start_addr = &rxBuffer[1];
333  rxDMADesc[2].config = DMA_CONFIG_DMA_EN |
334  DMA_CONFIG_WNR |
335  DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
336  DMA_CONFIG_NDSIZE(5) |
337  DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
338 
339  rxDMADesc[3].next = &rxDMADesc[0];
340  rxDMADesc[3].start_addr = &rxStatusWord[1];
341  rxDMADesc[3].config = DMA_CONFIG_DMA_EN |
342  DMA_CONFIG_WNR |
343  DMA_CONFIG_WDSIZE(DMA_WDSIZE_32BIT) |
344  DMA_CONFIG_NDSIZE(5) |
345  DMA_CONFIG_FLOW(DMA_FLOW_DESCRIPTOR_LIST_LARGE);
346 
347  bfin_dma_channel_enable(DMA_CHANNEL_EMAC_RX, &rxDMADesc[0]);
348 
349  /* Enable Receiving, Automatic Pad Stripping and receiving of frames with length < 64 butes */
350  pEth->opmode |= ASTP | PSF | RE;
351 
352  return 0;
353 }
354 int bfin_EMAC_send (void *packet, int length)
355 {
356  UASSERT(length > 0, EARG);
357  UASSERT(length < ETH_FRAME_SIZE, EARG);
358 
359  /* TODO: Check DMA Error in IRQ status */
360 
361  while (bfin_dma_channel_interrupt_is_active (DMA_CHANNEL_EMAC_TX));
362 
363  txBuffer[txIdx].length = length;
364  memcpy(txBuffer[txIdx].data, packet, length);
365 
366  bfin_dma_channel_enable(DMA_CHANNEL_EMAC_TX, txDMADesc);
367  pEth->opmode |= TE;
368 
369  while ((txStatusWord[txIdx] & TX_COMP) == 0);
370 
371  ASSERT(txStatusWord[txIdx] & TX_OK);
372 
373  txStatusWord[txIdx] = 0;
374 
375  ++txIdx;
376 
377  if (txIdx == ETH_TX_BUF_SIZE) {
378  txIdx = 0;
379  }
380 
381  return 0;
382 }
383 
384 int bfin_EMAC_recv (uint8_t * packet, size_t size)
385 {
386  uint32_t length;
387  uint32_t status = rxStatusWord[rxIdx];
388 
389  /* Check if rx frame is completed */
390  if ((status & RX_COMP) == 0) {
391  return -1;
392  }
393  else if ((status & RX_OK) == 0) {
394  ASSERT(0);
395  /* TODO: Handle error */
396  return -1;
397  }
398  else if (status & RX_DMAO) {
399  ASSERT(0);
400  /* TODO: Handle overrun */
401  return -1;
402  }
403 
404  length = status & RX_FRLEN;
405 
406  if (size < length) {
407  length = size;
408  }
409 
410  memcpy(packet, rxBuffer[rxIdx].data, length);
411 
412  bfin_dma_channel_interrupt_clear (DMA_CHANNEL_EMAC_RX);
413  rxStatusWord[rxIdx] = 0;
414 
415  ++rxIdx;
416 
417  if (rxIdx == ETH_RX_BUF_SIZE) {
418  rxIdx = 0;
419  }
420 
421  return length;
422 }
423 
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soem
Author(s): Arthur Ketels and M.J.G. van den Molengraft
autogenerated on Wed Mar 2 2022 01:01:49