stm32h7xx_hal_ospi.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_OSPI_H
22 #define STM32H7xx_HAL_OSPI_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
31 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)
32 
41 /* Exported types ------------------------------------------------------------*/
49 typedef struct
50 {
51  uint32_t FifoThreshold;
55  uint32_t DualQuad;
58  uint32_t MemoryType;
60  uint32_t DeviceSize;
64  uint32_t ChipSelectHighTime;
67  uint32_t FreeRunningClock;
69  uint32_t ClockMode;
71  uint32_t WrapSize;
73  uint32_t ClockPrescaler;
76  uint32_t SampleShifting;
79  uint32_t DelayHoldQuarterCycle;
81  uint32_t ChipSelectBoundary;
84  uint32_t ClkChipSelectHighTime;
87  uint32_t DelayBlockBypass;
90  uint32_t MaxTran;
94  uint32_t Refresh;
97 }OSPI_InitTypeDef;
98 
102 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
103 typedef struct __OSPI_HandleTypeDef
104 #else
105 typedef struct
106 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
107 {
108  OCTOSPI_TypeDef *Instance;
109  OSPI_InitTypeDef Init;
110  uint8_t *pBuffPtr;
111  __IO uint32_t XferSize;
112  __IO uint32_t XferCount;
113  MDMA_HandleTypeDef *hmdma;
114  __IO uint32_t State;
115  __IO uint32_t ErrorCode;
116  uint32_t Timeout;
117 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
118  void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi);
119  void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
120  void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);
121  void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
122  void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
123  void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
124  void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
125  void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi);
126  void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi);
127  void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi);
128 
129  void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi);
130  void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi);
131 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
132 }OSPI_HandleTypeDef;
133 
137 typedef struct
138 {
139  uint32_t OperationType;
143  uint32_t FlashId;
146  uint32_t Instruction;
148  uint32_t InstructionMode;
150  uint32_t InstructionSize;
152  uint32_t InstructionDtrMode;
154  uint32_t Address;
156  uint32_t AddressMode;
158  uint32_t AddressSize;
160  uint32_t AddressDtrMode;
162  uint32_t AlternateBytes;
164  uint32_t AlternateBytesMode;
166  uint32_t AlternateBytesSize;
168  uint32_t AlternateBytesDtrMode;
170  uint32_t DataMode;
172  uint32_t NbData;
175  uint32_t DataDtrMode;
177  uint32_t DummyCycles;
179  uint32_t DQSMode;
181  uint32_t SIOOMode;
183 }OSPI_RegularCmdTypeDef;
184 
188 typedef struct
189 {
190  uint32_t RWRecoveryTime;
192  uint32_t AccessTime;
194  uint32_t WriteZeroLatency;
196  uint32_t LatencyMode;
198 }OSPI_HyperbusCfgTypeDef;
199 
203 typedef struct
204 {
205  uint32_t AddressSpace;
207  uint32_t Address;
209  uint32_t AddressSize;
211  uint32_t NbData;
215  uint32_t DQSMode;
217 }OSPI_HyperbusCmdTypeDef;
218 
222 typedef struct
223 {
224  uint32_t Match;
226  uint32_t Mask;
228  uint32_t MatchMode;
230  uint32_t AutomaticStop;
232  uint32_t Interval;
234 }OSPI_AutoPollingTypeDef;
235 
239 typedef struct
240 {
241  uint32_t TimeOutActivation;
243  uint32_t TimeOutPeriod;
245 }OSPI_MemoryMappedTypeDef;
246 
250 typedef struct
251 {
252  uint32_t ClkPort;
254  uint32_t DQSPort;
256  uint32_t NCSPort;
258  uint32_t IOLowPort;
260  uint32_t IOHighPort;
262  uint32_t Req2AckTime;
265 }OSPIM_CfgTypeDef;
266 
267 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
268 
271 typedef enum
272 {
273  HAL_OSPI_ERROR_CB_ID = 0x00U,
274  HAL_OSPI_ABORT_CB_ID = 0x01U,
275  HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U,
276  HAL_OSPI_CMD_CPLT_CB_ID = 0x03U,
277  HAL_OSPI_RX_CPLT_CB_ID = 0x04U,
278  HAL_OSPI_TX_CPLT_CB_ID = 0x05U,
279  HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U,
280  HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U,
281  HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U,
282  HAL_OSPI_TIMEOUT_CB_ID = 0x09U,
284  HAL_OSPI_MSP_INIT_CB_ID = 0x0AU,
285  HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU
286 }HAL_OSPI_CallbackIDTypeDef;
287 
291 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);
292 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
293 
297 /* Exported constants --------------------------------------------------------*/
305 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U)
306 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U)
307 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U)
308 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U)
309 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U)
310 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U)
311 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U)
312 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U)
313 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U)
314 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U)
315 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U)
316 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U)
317 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U)
325 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U)
326 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U)
327 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U)
328 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U)
329 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U)
330 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U)
331 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
332 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)
333 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/
334 
341 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U)
342 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM)
350 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U)
351 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0)
352 #define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1)
353 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0))
354 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2)
362 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U)
363 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK)
371 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U)
372 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE)
380 #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U)
381 #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1)
382 #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1))
383 #define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2)
384 #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2))
392 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U)
393 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT)
401 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U)
402 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC)
410 #define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U)
411 #define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP)
419 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U)
420 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U)
421 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U)
422 #define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U)
430 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
431 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL)
439 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U)
440 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0)
441 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1)
442 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1))
443 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2)
451 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U)
452 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0)
453 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1)
454 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE)
462 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U)
463 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR)
471 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U)
472 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0)
473 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1)
474 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1))
475 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2)
483 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U)
484 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0)
485 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1)
486 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE)
494 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U)
495 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR)
503 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U)
504 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0)
505 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1)
506 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1))
507 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2)
515 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U)
516 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0)
517 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1)
518 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE)
526 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U)
527 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR)
535 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U)
536 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0)
537 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1)
538 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1))
539 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2)
547 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U)
548 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR)
556 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U)
557 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE)
565 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U)
566 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO)
574 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U)
575 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL)
583 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U)
584 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM)
592 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U)
593 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0)
601 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U)
602 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM)
610 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U)
611 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS)
619 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U)
620 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN)
628 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY
629 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF
630 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF
631 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF
632 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF
633 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF
641 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE
642 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE
643 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE
644 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE
645 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE
653 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */
654 
661 #define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U)
662 #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U))
663 #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U))
664 #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U))
665 #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U))
666 #define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U))
667 #define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U))
668 #define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U))
669 #define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U))
670 #define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U))
671 #define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U))
672 #define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U))
673 #define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U))
674 #define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U))
675 #define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U))
676 #define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U))
677 #define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U))
685 /* Exported macros -----------------------------------------------------------*/
686 
693 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
694 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
695  (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \
696  (__HANDLE__)->MspInitCallback = NULL; \
697  (__HANDLE__)->MspDeInitCallback = NULL; \
698  } while(0)
699 #else
700 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)
701 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
702 
707 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
708 
713 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)
714 
726 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
727 
728 
740 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
741 
753 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\
754  == (__INTERRUPT__))
755 
769 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \
770  != 0U) ? SET : RESET)
771 
782 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
783 
788 /* Exported functions --------------------------------------------------------*/
793 /* Initialization/de-initialization functions ********************************/
797 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi);
798 void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi);
799 HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi);
800 void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi);
801 
806 /* IO operation functions *****************************************************/
810 /* OSPI IRQ handler function */
811 void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi);
812 
813 /* OSPI command configuration functions */
814 HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);
815 HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);
816 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);
817 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);
818 
819 /* OSPI indirect mode functions */
820 HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
821 HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);
822 HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
823 HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData);
824 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
825 HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData);
826 
827 /* OSPI status flag polling mode functions */
828 HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
829 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);
830 
831 /* OSPI memory-mapped mode functions */
832 HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);
833 
834 /* Callback functions in non-blocking modes ***********************************/
835 void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi);
836 void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi);
837 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);
838 
839 /* OSPI indirect mode functions */
840 void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi);
841 void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi);
842 void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi);
843 void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
844 void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi);
845 
846 /* OSPI status flag polling mode functions */
847 void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi);
848 
849 /* OSPI memory-mapped mode functions */
850 void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi);
851 
852 #if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)
853 /* OSPI callback registering/unregistering */
854 HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID,
855  pOSPI_CallbackTypeDef pCallback);
856 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);
857 #endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */
858 
862 /* Peripheral Control and State functions ************************************/
866 HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi);
867 HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi);
868 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold);
869 uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi);
870 HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout);
871 uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi);
872 uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi);
873 
878 /* OSPI IO Manager configuration function ************************************/
882 HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);
883 
891 /* End of exported functions -------------------------------------------------*/
892 
893 /* Private macros ------------------------------------------------------------*/
897 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U))
898 
899 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \
900  ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))
901 
902 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \
903  ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \
904  ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \
905  ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \
906  ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))
907 
908 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U))
909 
910 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U))
911 
912 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \
913  ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE))
914 
915 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \
916  ((MODE) == HAL_OSPI_CLOCK_MODE_3))
917 
918 #define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \
919  ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \
920  ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \
921  ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \
922  ((SIZE) == HAL_OSPI_WRAP_128_BYTES))
923 
924 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U))
925 
926 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \
927  ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE))
928 
929 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \
930  ((CYCLE) == HAL_OSPI_DHQC_ENABLE))
931 
932 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \
933  ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \
934  ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG) || \
935  ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG))
936 
937 #define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \
938  ((FLASHID) == HAL_OSPI_FLASH_ID_2))
939 
940 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \
941  ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \
942  ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \
943  ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \
944  ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))
945 
946 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \
947  ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \
948  ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \
949  ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS))
950 
951 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \
952  ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))
953 
954 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \
955  ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \
956  ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \
957  ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \
958  ((MODE) == HAL_OSPI_ADDRESS_8_LINES))
959 
960 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \
961  ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \
962  ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \
963  ((SIZE) == HAL_OSPI_ADDRESS_32_BITS))
964 
965 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \
966  ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))
967 
968 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \
969  ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \
970  ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \
971  ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \
972  ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))
973 
974 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \
975  ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \
976  ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \
977  ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS))
978 
979 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \
980  ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))
981 
982 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \
983  ((MODE) == HAL_OSPI_DATA_1_LINE) || \
984  ((MODE) == HAL_OSPI_DATA_2_LINES) || \
985  ((MODE) == HAL_OSPI_DATA_4_LINES) || \
986  ((MODE) == HAL_OSPI_DATA_8_LINES))
987 
988 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U)
989 
990 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \
991  ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))
992 
993 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U)
994 
995 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \
996  ((MODE) == HAL_OSPI_DQS_ENABLE))
997 
998 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \
999  ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))
1000 
1001 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U)
1002 
1003 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U)
1004 
1005 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \
1006  ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))
1007 
1008 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \
1009  ((MODE) == HAL_OSPI_FIXED_LATENCY))
1010 
1011 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \
1012  ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE))
1013 
1014 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \
1015  ((MODE) == HAL_OSPI_MATCH_MODE_OR))
1016 
1017 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \
1018  ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))
1019 
1020 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU)
1021 
1022 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
1023 
1024 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \
1025  ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))
1026 
1027 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
1028 
1029 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U)
1030 
1031 #define IS_OSPI_CKCSHT(CLK_NB) ((CLK_NB) <= 7U)
1032 
1033 #define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \
1034  ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))
1035 
1036 #define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U)
1037 
1038 #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
1039 
1040 #define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U)
1041 
1042 #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \
1043  ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \
1044  ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \
1045  ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \
1046  ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \
1047  ((PORT) == HAL_OSPIM_IOPORT_3_LOW) || \
1048  ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \
1049  ((PORT) == HAL_OSPIM_IOPORT_4_LOW) || \
1050  ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \
1051  ((PORT) == HAL_OSPIM_IOPORT_5_LOW) || \
1052  ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \
1053  ((PORT) == HAL_OSPIM_IOPORT_6_LOW) || \
1054  ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \
1055  ((PORT) == HAL_OSPIM_IOPORT_7_LOW) || \
1056  ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \
1057  ((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \
1058  ((PORT) == HAL_OSPIM_IOPORT_8_HIGH))
1059 
1060 #define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U))
1061 
1065 /* End of private macros -----------------------------------------------------*/
1066 
1075 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */
1076 
1077 #ifdef __cplusplus
1078 }
1079 #endif
1080 
1081 #endif /* STM32H7xx_HAL_OSPI_H */
1082 
1083 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
Init
napi_value Init(napi_env env, napi_value exports)
Definition: porcupine/demo/c/pvrecorder/node/pv_recorder_napi.c:197
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
__MDMA_HandleTypeDef
MDMA handle Structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h:203
OCTOSPI_TypeDef
OCTO Serial Peripheral Interface.
Definition: stm32h735xx.h:1960

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:54