stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_FLASH_EX_H
22 #define STM32H7xx_HAL_FLASH_EX_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t TypeErase;
52  uint32_t Banks;
55  uint32_t Sector;
58  uint32_t NbSectors;
61  uint32_t VoltageRange;
64 } FLASH_EraseInitTypeDef;
65 
66 
70 typedef struct
71 {
72  uint32_t OptionType;
75  uint32_t WRPState;
78  uint32_t WRPSector;
81  uint32_t RDPLevel;
84  uint32_t BORLevel;
87  uint32_t USERType;
90  uint32_t USERConfig;
93  uint32_t Banks;
96  uint32_t PCROPConfig;
100  uint32_t PCROPStartAddr;
103  uint32_t PCROPEndAddr;
106  uint32_t BootConfig;
109  uint32_t BootAddr0;
112  uint32_t BootAddr1;
114 #if defined(DUAL_CORE)
115  uint32_t CM4BootConfig;
119  uint32_t CM4BootAddr0;
122  uint32_t CM4BootAddr1;
124 #endif /*DUAL_CORE*/
125 
126  uint32_t SecureAreaConfig;
130  uint32_t SecureAreaStartAddr;
133  uint32_t SecureAreaEndAddr;
136 #if defined (FLASH_OTPBL_LOCKBL)
137  uint32_t OTPBlockLock;
139 #endif /* FLASH_OTPBL_LOCKBL */
140 
141 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
142  uint32_t SharedRamConfig;
144 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
145 
146 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
147  uint32_t FreqBoostState;
149 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
150 
151 } FLASH_OBProgramInitTypeDef;
152 
156 typedef struct
157 {
158  uint32_t TypeCRC;
161  uint32_t BurstSize;
164  uint32_t Bank;
167  uint32_t Sector;
170  uint32_t NbSectors;
173  uint32_t CRCStartAddr;
176  uint32_t CRCEndAddr;
179 } FLASH_CRCInitTypeDef;
180 
184 /* Exported constants --------------------------------------------------------*/
185 
193 #define FLASH_TYPEERASE_SECTORS 0x00U
194 #define FLASH_TYPEERASE_MASSERASE 0x01U
199 #if defined (FLASH_CR_PSIZE)
200 
203 #define FLASH_VOLTAGE_RANGE_1 0x00000000U
204 #define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0
205 #define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1
206 #define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE
210 #endif /* FLASH_CR_PSIZE */
211 
215 #define OB_WRPSTATE_DISABLE 0x00000000U
216 #define OB_WRPSTATE_ENABLE 0x00000001U
224 #define OPTIONBYTE_WRP 0x01U
225 #define OPTIONBYTE_RDP 0x02U
226 #define OPTIONBYTE_USER 0x04U
227 #define OPTIONBYTE_PCROP 0x08U
228 #define OPTIONBYTE_BOR 0x10U
229 #define OPTIONBYTE_SECURE_AREA 0x20U
230 #if defined (DUAL_CORE)
231 #define OPTIONBYTE_CM7_BOOTADD 0x40U
232 #define OPTIONBYTE_CM4_BOOTADD 0x80U
233 #define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD
234 #else /* Single core */
235 #define OPTIONBYTE_BOOTADD 0x40U
236 #endif /*DUAL_CORE*/
237 #if defined (FLASH_OTPBL_LOCKBL)
238 #define OPTIONBYTE_OTP_LOCK 0x80U
239 #endif /* FLASH_OTPBL_LOCKBL */
240 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
241 #define OPTIONBYTE_SHARED_RAM 0x100U
242 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
243 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
244 #define OPTIONBYTE_FREQ_BOOST 0x200U
245 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
246 
247 #if defined (DUAL_CORE)
248 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
249  OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
250  OPTIONBYTE_CM7_BOOTADD | OPTIONBYTE_CM4_BOOTADD)
251 #elif defined (FLASH_OTPBL_LOCKBL)
252 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
253  OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
254  OPTIONBYTE_BOOTADD | OPTIONBYTE_OTP_LOCK)
255 #elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
256 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
257  OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
258  OPTIONBYTE_BOOTADD | OPTIONBYTE_SHARED_RAM | OPTIONBYTE_FREQ_BOOST)
259 #else
260 #define OPTIONBYTE_ALL (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
261  OPTIONBYTE_PCROP | OPTIONBYTE_BOR | OPTIONBYTE_SECURE_AREA |\
262  OPTIONBYTE_BOOTADD)
263 #endif /* DUAL_CORE */
264 
271 #define OB_RDP_LEVEL_0 0xAA00U
272 #define OB_RDP_LEVEL_1 0x5500U
273 #define OB_RDP_LEVEL_2 0xCC00U
282 #define OB_WWDG_SW 0x10U
283 #define OB_WWDG_HW 0x00U
292 #define OB_IWDG_SW OB_IWDG1_SW
293 #define OB_IWDG_HW OB_IWDG1_HW
301 #define OB_STOP_NO_RST 0x40U
302 #define OB_STOP_RST 0x00U
310 #define OB_STDBY_NO_RST 0x80U
311 #define OB_STDBY_RST 0x00U
319 #define OB_IWDG_STOP_FREEZE 0x00000000U
320 #define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP
328 #define OB_IWDG_STDBY_FREEZE 0x00000000U
329 #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY
337 #define OB_BOR_LEVEL0 0x00000000U
338 #define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0
339 #define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1
340 #define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0)
350 #define OB_BOOTADDR_ITCM_RAM 0x0000U
351 #define OB_BOOTADDR_SYSTEM 0x0040U
352 #define OB_BOOTADDR_ITCM_FLASH 0x0080U
353 #define OB_BOOTADDR_AXIM_FLASH 0x2000U
354 #define OB_BOOTADDR_DTCM_RAM 0x8000U
355 #define OB_BOOTADDR_SRAM1 0x8004U
356 #define OB_BOOTADDR_SRAM2 0x8013U
364 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
365 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
366 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
367 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
368 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
369 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
370 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
371 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
372 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
373 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
374 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
375 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
376 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
377 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
378 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
379 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
387 #define FLASH_BANK_1 0x01U
388 #if defined (DUAL_BANK)
389 #define FLASH_BANK_2 0x02U
390 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2)
391 #endif /* DUAL_BANK */
392 
399 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U
401 #define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP
411 #if (FLASH_SECTOR_TOTAL == 128)
412 #define OB_WRP_SECTOR_0TO3 0x00000001U
413 #define OB_WRP_SECTOR_4TO7 0x00000002U
414 #define OB_WRP_SECTOR_8TO11 0x00000004U
415 #define OB_WRP_SECTOR_12TO15 0x00000008U
416 #define OB_WRP_SECTOR_16TO19 0x00000010U
417 #define OB_WRP_SECTOR_20TO23 0x00000020U
418 #define OB_WRP_SECTOR_24TO27 0x00000040U
419 #define OB_WRP_SECTOR_28TO31 0x00000080U
420 #define OB_WRP_SECTOR_32TO35 0x00000100U
421 #define OB_WRP_SECTOR_36TO39 0x00000200U
422 #define OB_WRP_SECTOR_40TO43 0x00000400U
423 #define OB_WRP_SECTOR_44TO47 0x00000800U
424 #define OB_WRP_SECTOR_48TO51 0x00001000U
425 #define OB_WRP_SECTOR_52TO55 0x00002000U
426 #define OB_WRP_SECTOR_56TO59 0x00004000U
427 #define OB_WRP_SECTOR_60TO63 0x00008000U
428 #define OB_WRP_SECTOR_64TO67 0x00010000U
429 #define OB_WRP_SECTOR_68TO71 0x00020000U
430 #define OB_WRP_SECTOR_72TO75 0x00040000U
431 #define OB_WRP_SECTOR_76TO79 0x00080000U
432 #define OB_WRP_SECTOR_80TO83 0x00100000U
433 #define OB_WRP_SECTOR_84TO87 0x00200000U
434 #define OB_WRP_SECTOR_88TO91 0x00400000U
435 #define OB_WRP_SECTOR_92TO95 0x00800000U
436 #define OB_WRP_SECTOR_96TO99 0x01000000U
437 #define OB_WRP_SECTOR_100TO103 0x02000000U
438 #define OB_WRP_SECTOR_104TO107 0x04000000U
439 #define OB_WRP_SECTOR_108TO111 0x08000000U
440 #define OB_WRP_SECTOR_112TO115 0x10000000U
441 #define OB_WRP_SECTOR_116TO119 0x20000000U
442 #define OB_WRP_SECTOR_120TO123 0x40000000U
443 #define OB_WRP_SECTOR_124TO127 0x80000000U
444 #define OB_WRP_SECTOR_ALL 0xFFFFFFFFU
445 #else
446 #define OB_WRP_SECTOR_0 0x00000001U
447 #define OB_WRP_SECTOR_1 0x00000002U
448 #define OB_WRP_SECTOR_2 0x00000004U
449 #define OB_WRP_SECTOR_3 0x00000008U
450 #define OB_WRP_SECTOR_4 0x00000010U
451 #define OB_WRP_SECTOR_5 0x00000020U
452 #define OB_WRP_SECTOR_6 0x00000040U
453 #define OB_WRP_SECTOR_7 0x00000080U
454 #define OB_WRP_SECTOR_ALL 0x000000FFU
455 #endif /* FLASH_SECTOR_TOTAL == 128 */
456 
463 #define OB_SECURITY_DISABLE 0x00000000U
464 #define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY
472 #define OB_ST_RAM_SIZE_2KB 0x00000000U
473 #define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0
474 #define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1
475 #define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE
480 #if defined(DUAL_CORE)
481 
484 #define OB_BCM7_DISABLE 0x00000000U
485 #define OB_BCM7_ENABLE FLASH_OPTSR_BCM7
494 #define OB_BCM4_DISABLE 0x00000000U
495 #define OB_BCM4_ENABLE FLASH_OPTSR_BCM4
499 #endif /* DUAL_CORE */
500 
504 #define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW
505 #define OB_IWDG1_HW 0x00000000U
510 #if defined(DUAL_CORE)
511 
514 #define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW
515 #define OB_IWDG2_HW 0x00000000U
519 #endif
520 
524 #define OB_STOP_RST_D1 0x00000000U
525 #define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1
533 #define OB_STDBY_RST_D1 0x00000000U
534 #define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1
539 #if defined (FLASH_OPTSR_NRST_STOP_D2)
540 
543 #define OB_STOP_RST_D2 0x00000000U
544 #define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2
552 #define OB_STDBY_RST_D2 0x00000000U
553 #define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2
557 #endif /* FLASH_OPTSR_NRST_STOP_D2 */
558 
562 #define OB_SWAP_BANK_DISABLE 0x00000000U
563 #define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT
571 #define OB_IOHSLV_DISABLE 0x00000000U
572 #define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV
577 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
578 
581 #define OB_VDDMMC_HSLV_DISABLE 0x00000000U
582 #define OB_VDDMMC_HSLV_ENABLE FLASH_OPTSR_VDDMMC_HSLV
586 #endif /* FLASH_OPTSR_VDDMMC_HSLV */
587 
588 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
589 
592 #define OB_CPUFREQ_BOOST_DISABLE 0x00000000U
593 #define OB_CPUFREQ_BOOST_ENABLE FLASH_OPTSR2_CPUFREQ_BOOST
597 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
598 
599 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
600 
603 #define OB_TCM_AXI_SHARED_ITCM64KB 0x00000000U
604 #define OB_TCM_AXI_SHARED_ITCM128KB FLASH_OPTSR2_TCM_AXI_SHARED_0
605 #define OB_TCM_AXI_SHARED_ITCM192KB FLASH_OPTSR2_TCM_AXI_SHARED_1
606 #define OB_TCM_AXI_SHARED_ITCM256KB FLASH_OPTSR2_TCM_AXI_SHARED
610 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
611 
615 #define OB_USER_IWDG1_SW 0x0001U
616 #define OB_USER_NRST_STOP_D1 0x0002U
617 #define OB_USER_NRST_STDBY_D1 0x0004U
618 #define OB_USER_IWDG_STOP 0x0008U
619 #define OB_USER_IWDG_STDBY 0x0010U
620 #define OB_USER_ST_RAM_SIZE 0x0020U
621 #define OB_USER_SECURITY 0x0040U
622 #define OB_USER_IOHSLV 0x0080U
623 #if defined (DUAL_BANK)
624 #define OB_USER_SWAP_BANK 0x0100U
625 #endif /* DUAL_BANK */
626 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
627 #define OB_USER_VDDMMC_HSLV 0x0200U
628 #endif /* FLASH_OPTSR_VDDMMC_HSLV */
629 #if defined (DUAL_CORE)
630 #define OB_USER_IWDG2_SW 0x0200U
631 #define OB_USER_BCM4 0x0400U
632 #define OB_USER_BCM7 0x0800U
633 #endif /*DUAL_CORE*/
634 #if defined (FLASH_OPTSR_NRST_STOP_D2)
635 #define OB_USER_NRST_STOP_D2 0x1000U
636 #define OB_USER_NRST_STDBY_D2 0x2000U
637 #endif /* FLASH_OPTSR_NRST_STOP_D2 */
638 
639 #if defined (DUAL_CORE)
640 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
641  OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
642  OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
643  OB_USER_IWDG2_SW | OB_USER_BCM4 | OB_USER_BCM7 |\
644  OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
645 #elif defined (FLASH_OPTSR_VDDMMC_HSLV)
646 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
647  OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
648  OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK |\
649  OB_USER_VDDMMC_HSLV)
650 #elif defined (FLASH_OPTSR2_TCM_AXI_SHARED)
651 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
652  OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
653  OB_USER_SECURITY | OB_USER_IOHSLV |\
654  OB_USER_NRST_STOP_D2 | OB_USER_NRST_STDBY_D2)
655 #else
656 #define OB_USER_ALL (OB_USER_IWDG1_SW | OB_USER_NRST_STOP_D1 | OB_USER_NRST_STDBY_D1 |\
657  OB_USER_IWDG_STOP | OB_USER_IWDG_STDBY | OB_USER_ST_RAM_SIZE |\
658  OB_USER_SECURITY | OB_USER_IOHSLV | OB_USER_SWAP_BANK )
659 #endif /* DUAL_CORE */
660 
667 #define OB_BOOT_ADD0 0x01U
668 #define OB_BOOT_ADD1 0x02U
669 #define OB_BOOT_ADD_BOTH 0x03U
677 #define OB_SECURE_RDP_NOT_ERASE 0x00000000U
679 #define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES
688 #define FLASH_CRC_ADDR 0x00000000U
689 #define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT
690 #define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT)
698 #define FLASH_CRC_BURST_SIZE_4 0x00000000U
699 #define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0
700 #define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1
701 #define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST
709 #define FLASH_PROGRAMMING_DELAY_0 0x00000000U
710 #define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0
711 #define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1
712 #define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ
717 #if defined (FLASH_OTPBL_LOCKBL)
718 
721 #define FLASH_OTP_BLOCK_0 0x00000001U
722 #define FLASH_OTP_BLOCK_1 0x00000002U
723 #define FLASH_OTP_BLOCK_2 0x00000004U
724 #define FLASH_OTP_BLOCK_3 0x00000008U
725 #define FLASH_OTP_BLOCK_4 0x00000010U
726 #define FLASH_OTP_BLOCK_5 0x00000020U
727 #define FLASH_OTP_BLOCK_6 0x00000040U
728 #define FLASH_OTP_BLOCK_7 0x00000080U
729 #define FLASH_OTP_BLOCK_8 0x00000100U
730 #define FLASH_OTP_BLOCK_9 0x00000200U
731 #define FLASH_OTP_BLOCK_10 0x00000400U
732 #define FLASH_OTP_BLOCK_11 0x00000800U
733 #define FLASH_OTP_BLOCK_12 0x00001000U
734 #define FLASH_OTP_BLOCK_13 0x00002000U
735 #define FLASH_OTP_BLOCK_14 0x00004000U
736 #define FLASH_OTP_BLOCK_15 0x00008000U
737 #define FLASH_OTP_BLOCK_ALL 0x0000FFFFU
741 #endif /* FLASH_OTPBL_LOCKBL */
742 
743 /* Exported macro ------------------------------------------------------------*/
753 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
754 
758 #if defined (FLASH_CR_PSIZE)
759 
766 #if defined (DUAL_BANK)
767 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \
768  MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \
769  MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))
770 #else
771 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__))
772 #endif /* DUAL_BANK */
773 
780 #if defined (DUAL_BANK)
781 #define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
782  READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \
783  READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
784 #else
785 #define __HAL_FLASH_GET_PSIZE(__BANK__) READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)
786 #endif /* DUAL_BANK */
787 
788 #endif /* FLASH_CR_PSIZE */
789 
796 #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
797 
803 #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
804 
805 /* Exported functions --------------------------------------------------------*/
813 /* Extension Program operation functions *************************************/
814 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
815 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
816 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
817 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
818 
819 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
820 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
821 #if defined (DUAL_BANK)
822 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
823 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
824 #endif /* DUAL_BANK */
825 
826 HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);
827 
835 /* Private types -------------------------------------------------------------*/
836 /* Private variables ---------------------------------------------------------*/
837 /* Private constants ---------------------------------------------------------*/
838 /* Private macros ------------------------------------------------------------*/
847 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
848  ((VALUE) == FLASH_TYPEERASE_MASSERASE))
849 
850 #if defined (FLASH_CR_PSIZE)
851 #define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
852  ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
853  ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
854  ((RANGE) == FLASH_VOLTAGE_RANGE_4))
855 #endif /* FLASH_CR_PSIZE */
856 
857 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
858  ((VALUE) == OB_WRPSTATE_ENABLE))
859 
860 #define IS_OPTIONBYTE(VALUE) ((((VALUE) & OPTIONBYTE_ALL) != 0U) && \
861  (((VALUE) & ~OPTIONBYTE_ALL) == 0U))
862 
863 #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
864 
865 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
866  ((LEVEL) == OB_RDP_LEVEL_1) ||\
867  ((LEVEL) == OB_RDP_LEVEL_2))
868 
869 #define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
870 
871 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
872 
873 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
874 
875 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
876 
877 #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
878 
879 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
880 
881 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
882  ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
883 
884 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
885  ((LATENCY) == FLASH_LATENCY_1) || \
886  ((LATENCY) == FLASH_LATENCY_2) || \
887  ((LATENCY) == FLASH_LATENCY_3) || \
888  ((LATENCY) == FLASH_LATENCY_4) || \
889  ((LATENCY) == FLASH_LATENCY_5) || \
890  ((LATENCY) == FLASH_LATENCY_6) || \
891  ((LATENCY) == FLASH_LATENCY_7) || \
892  ((LATENCY) == FLASH_LATENCY_8) || \
893  ((LATENCY) == FLASH_LATENCY_9) || \
894  ((LATENCY) == FLASH_LATENCY_10) || \
895  ((LATENCY) == FLASH_LATENCY_11) || \
896  ((LATENCY) == FLASH_LATENCY_12) || \
897  ((LATENCY) == FLASH_LATENCY_13) || \
898  ((LATENCY) == FLASH_LATENCY_14) || \
899  ((LATENCY) == FLASH_LATENCY_15))
900 
901 #define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)
902 
903 #if (FLASH_SECTOR_TOTAL == 8U)
904 #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
905 #else
906 #define IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)
907 #endif /* FLASH_SECTOR_TOTAL == 8U */
908 
909 #define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
910  ((CONFIG) == OB_PCROP_RDP_ERASE))
911 
912 #define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
913  ((CONFIG) == OB_SECURE_RDP_ERASE))
914 
915 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
916 
917 #define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
918 
919 #if defined (FLASH_OPTSR_VDDMMC_HSLV)
920 #define IS_OB_USER_VDDMMC_HSLV(VALUE) (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
921 #endif /* FLASH_OPTSR_VDDMMC_HSLV */
922 
923 #define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
924 #if defined (DUAL_CORE)
925 #define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
926 #endif /* DUAL_CORE */
927 #define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
928 
929 #define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
930 
931 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
932 
933 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
934 
935 #define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \
936  ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))
937 
938 #define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
939 
940 #if defined (DUAL_CORE)
941 #define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
942 
943 #define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
944 #endif /* DUAL_CORE */
945 
946 #if defined (FLASH_OPTSR_NRST_STOP_D2)
947 #define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
948 
949 #define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
950 #endif /* FLASH_OPTSR_NRST_STOP_D2 */
951 
952 #if defined (FLASH_OPTSR2_TCM_AXI_SHARED)
953 #define IS_OB_USER_TCM_AXI_SHARED(VALUE) (((VALUE) == OB_TCM_AXI_SHARED_ITCM64KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM128KB) || \
954  ((VALUE) == OB_TCM_AXI_SHARED_ITCM192KB) || ((VALUE) == OB_TCM_AXI_SHARED_ITCM256KB))
955 #endif /* FLASH_OPTSR2_TCM_AXI_SHARED */
956 
957 #if defined (FLASH_OPTSR2_CPUFREQ_BOOST)
958 #define IS_OB_USER_CPUFREQ_BOOST(VALUE) (((VALUE) == OB_CPUFREQ_BOOST_DISABLE) || ((VALUE) == OB_CPUFREQ_BOOST_ENABLE))
959 #endif /* FLASH_OPTSR2_CPUFREQ_BOOST */
960 
961 #define IS_OB_USER_TYPE(TYPE) ((((TYPE) & OB_USER_ALL) != 0U) && \
962  (((TYPE) & ~OB_USER_ALL) == 0U))
963 
964 #define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
965  ((VALUE) == OB_BOOT_ADD1) || \
966  ((VALUE) == OB_BOOT_ADD_BOTH))
967 
968 #define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \
969  ((VALUE) == FLASH_CRC_SECTORS) || \
970  ((VALUE) == FLASH_CRC_BANK))
971 
972 #if defined (FLASH_OTPBL_LOCKBL)
973 #define IS_OTP_BLOCK(VALUE) ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
974 #endif /* FLASH_OTPBL_LOCKBL */
975 
983 /* Private functions ---------------------------------------------------------*/
987 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);
1004 #ifdef __cplusplus
1005 }
1006 #endif
1007 
1008 #endif /* STM32H7xx_HAL_FLASH_EX_H */
1009 
1010 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
FLASH_Erase_Sector
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
FLASH_CRCInitTypeDef
FLASH Erase structure definition.
Definition: stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:156
FLASH_OBProgramInitTypeDef
FLASH Option Bytes Program structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:69
HAL_FLASHEx_Lock_Bank1
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void)
HAL_FLASHEx_Unlock_Bank1
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void)
HAL_FLASHEx_Erase
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
HAL_FLASHEx_OBProgram
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
HAL_FLASHEx_ComputeCRC
HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result)
HAL_FLASHEx_OBGetConfig
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_FLASHEx_Erase_IT
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
FLASH_EraseInitTypeDef
FLASH Erase structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:47

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:54