picovoice_driver: stm32h7xx_hal_flash

#include "stm32h7xx_hal_def.h"

Include dependency graph for stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h:

This graph shows which files directly or indirectly include this file:

Classes
struct	FLASH_CRCInitTypeDef
	FLASH Erase structure definition. More...

struct	FLASH_EraseInitTypeDef
	FLASH Erase structure definition. More...

struct	FLASH_OBProgramInitTypeDef
	FLASH Option Bytes Program structure definition. More...

Macros
#define	__HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)
	Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) More...

#define	__HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)
	Get the FLASH Programming Delay. More...

#define	__HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))
	Set the FLASH Programming Delay. More...

#define	FLASH_BANK_1 0x01U

#define	FLASH_CRC_ADDR 0x00000000U

#define	FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK \| FLASH_CRCCR_CRC_BY_SECT)

#define	FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0

#define	FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST

#define	FLASH_CRC_BURST_SIZE_4 0x00000000U

#define	FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1

#define	FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT

#define	FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS

#define	FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS

#define	FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS

#define	FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS

#define	FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS

#define	FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS

#define	FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS

#define	FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS

#define	FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS

#define	FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS

#define	FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS

#define	FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS

#define	FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS

#define	FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS

#define	FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS

#define	FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS

#define	FLASH_PROGRAMMING_DELAY_0 0x00000000U

#define	FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0

#define	FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1

#define	FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ

#define	FLASH_TYPEERASE_MASSERASE 0x01U

#define	FLASH_TYPEERASE_SECTORS 0x00U

#define	IS_FLASH_LATENCY(LATENCY)

#define	IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL)

#define	IS_FLASH_TYPECRC(VALUE)

#define	IS_FLASH_TYPEERASE(VALUE)

#define	IS_OB_BOOT_ADD_OPTION(VALUE)

#define	IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)

#define	IS_OB_BOR_LEVEL(LEVEL)

#define	IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) \|\| ((SOURCE) == OB_IWDG1_HW))

#define	IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) \|\| ((SOURCE) == OB_IWDG_HW))

#define	IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) \|\| ((FREEZE) == OB_IWDG_STDBY_ACTIVE))

#define	IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) \|\| ((FREEZE) == OB_IWDG_STOP_ACTIVE))

#define	IS_OB_PCROP_RDP(CONFIG)

#define	IS_OB_RDP_LEVEL(LEVEL)

#define	IS_OB_SECURE_RDP(CONFIG)

#define	IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) \|\| ((VALUE) == OB_STDBY_RST_D1))

#define	IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) \|\| ((SOURCE) == OB_STDBY_RST))

#define	IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) \|\| ((VALUE) == OB_STOP_RST_D1))

#define	IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) \|\| ((SOURCE) == OB_STOP_RST))

#define	IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) \|\| ((VALUE) == OB_IOHSLV_ENABLE))

#define	IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) \|\| ((VALUE) == OB_IWDG_STDBY_ACTIVE))

#define	IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) \|\| ((VALUE) == OB_IWDG_STOP_ACTIVE))

#define	IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) \|\| ((VALUE) == OB_SECURITY_DISABLE))

#define	IS_OB_USER_ST_RAM_SIZE(VALUE)

#define	IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) \|\| ((VALUE) == OB_SWAP_BANK_ENABLE))

#define	IS_OB_USER_TYPE(TYPE)

#define	IS_OB_WRP_SECTOR(SECTOR) ((SECTOR) != 0x00000000U)

#define	IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) \|\| ((SOURCE) == OB_WWDG_HW))

#define	IS_OPTIONBYTE(VALUE)

#define	IS_WRPSTATE(VALUE)

#define	OB_BOOT_ADD0 0x01U

#define	OB_BOOT_ADD1 0x02U

#define	OB_BOOT_ADD_BOTH 0x03U

#define	OB_BOOTADDR_AXIM_FLASH 0x2000U

#define	OB_BOOTADDR_DTCM_RAM 0x8000U

#define	OB_BOOTADDR_ITCM_FLASH 0x0080U

#define	OB_BOOTADDR_ITCM_RAM 0x0000U

#define	OB_BOOTADDR_SRAM1 0x8004U

#define	OB_BOOTADDR_SRAM2 0x8013U

#define	OB_BOOTADDR_SYSTEM 0x0040U

#define	OB_BOR_LEVEL0 0x00000000U

#define	OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0

#define	OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1

#define	OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 \| FLASH_OPTSR_BOR_LEV_0)

#define	OB_IOHSLV_DISABLE 0x00000000U

#define	OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV

#define	OB_IWDG1_HW 0x00000000U

#define	OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW

#define	OB_IWDG_HW OB_IWDG1_HW

#define	OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY

#define	OB_IWDG_STDBY_FREEZE 0x00000000U

#define	OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP

#define	OB_IWDG_STOP_FREEZE 0x00000000U

#define	OB_IWDG_SW OB_IWDG1_SW

#define	OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP

#define	OB_PCROP_RDP_NOT_ERASE 0x00000000U

#define	OB_RDP_LEVEL_0 0xAA00U

#define	OB_RDP_LEVEL_1 0x5500U

#define	OB_RDP_LEVEL_2 0xCC00U

#define	OB_SECURE_RDP_ERASE FLASH_SCAR_DMES

#define	OB_SECURE_RDP_NOT_ERASE 0x00000000U

#define	OB_SECURITY_DISABLE 0x00000000U

#define	OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY

#define	OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE

#define	OB_ST_RAM_SIZE_2KB 0x00000000U

#define	OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0

#define	OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1

#define	OB_STDBY_NO_RST 0x80U

#define	OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1

#define	OB_STDBY_RST 0x00U

#define	OB_STDBY_RST_D1 0x00000000U

#define	OB_STOP_NO_RST 0x40U

#define	OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1

#define	OB_STOP_RST 0x00U

#define	OB_STOP_RST_D1 0x00000000U

#define	OB_SWAP_BANK_DISABLE 0x00000000U

#define	OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT

#define	OB_USER_ALL

#define	OB_USER_IOHSLV 0x0080U

#define	OB_USER_IWDG1_SW 0x0001U

#define	OB_USER_IWDG_STDBY 0x0010U

#define	OB_USER_IWDG_STOP 0x0008U

#define	OB_USER_NRST_STDBY_D1 0x0004U

#define	OB_USER_NRST_STOP_D1 0x0002U

#define	OB_USER_SECURITY 0x0040U

#define	OB_USER_ST_RAM_SIZE 0x0020U

#define	OB_WRP_SECTOR_0 0x00000001U

#define	OB_WRP_SECTOR_1 0x00000002U

#define	OB_WRP_SECTOR_2 0x00000004U

#define	OB_WRP_SECTOR_3 0x00000008U

#define	OB_WRP_SECTOR_4 0x00000010U

#define	OB_WRP_SECTOR_5 0x00000020U

#define	OB_WRP_SECTOR_6 0x00000040U

#define	OB_WRP_SECTOR_7 0x00000080U

#define	OB_WRP_SECTOR_ALL 0x000000FFU

#define	OB_WRPSTATE_DISABLE 0x00000000U

#define	OB_WRPSTATE_ENABLE 0x00000001U

#define	OB_WWDG_HW 0x00U

#define	OB_WWDG_SW 0x10U

#define	OPTIONBYTE_ALL

#define	OPTIONBYTE_BOOTADD 0x40U

#define	OPTIONBYTE_BOR 0x10U

#define	OPTIONBYTE_PCROP 0x08U

#define	OPTIONBYTE_RDP 0x02U

#define	OPTIONBYTE_SECURE_AREA 0x20U

#define	OPTIONBYTE_USER 0x04U

#define	OPTIONBYTE_WRP 0x01U

Functions
void	FLASH_Erase_Sector (uint32_t Sector, uint32_t Banks, uint32_t VoltageRange)

HAL_StatusTypeDef	HAL_FLASHEx_ComputeCRC (FLASH_CRCInitTypeDef pCRCInit, uint32_t CRC_Result)

HAL_StatusTypeDef	HAL_FLASHEx_Erase (FLASH_EraseInitTypeDef pEraseInit, uint32_t SectorError)

HAL_StatusTypeDef	HAL_FLASHEx_Erase_IT (FLASH_EraseInitTypeDef *pEraseInit)

HAL_StatusTypeDef	HAL_FLASHEx_Lock_Bank1 (void)

void	HAL_FLASHEx_OBGetConfig (FLASH_OBProgramInitTypeDef *pOBInit)

HAL_StatusTypeDef	HAL_FLASHEx_OBProgram (FLASH_OBProgramInitTypeDef *pOBInit)

HAL_StatusTypeDef	HAL_FLASHEx_Unlock_Bank1 (void)

Classes

Macros

Functions