stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_DMA2D_H
22 #define STM32H7xx_HAL_DMA2D_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
35 #if defined (DMA2D)
36 
42 /* Exported types ------------------------------------------------------------*/
46 #define MAX_DMA2D_LAYER 2U
51 typedef struct
52 {
53  uint32_t *pCLUT;
55  uint32_t CLUTColorMode;
58  uint32_t Size;
60 } DMA2D_CLUTCfgTypeDef;
61 
65 typedef struct
66 {
67  uint32_t Mode;
70  uint32_t ColorMode;
73  uint32_t OutputOffset;
75  uint32_t AlphaInverted;
78  uint32_t RedBlueSwap;
83  uint32_t BytesSwap;
86  uint32_t LineOffsetMode;
89 } DMA2D_InitTypeDef;
90 
91 
95 typedef struct
96 {
97  uint32_t InputOffset;
100  uint32_t InputColorMode;
103  uint32_t AlphaMode;
106  uint32_t InputAlpha;
114  uint32_t AlphaInverted;
117  uint32_t RedBlueSwap;
120  uint32_t ChromaSubSampling;
123 } DMA2D_LayerCfgTypeDef;
124 
128 typedef enum
129 {
130  HAL_DMA2D_STATE_RESET = 0x00U,
131  HAL_DMA2D_STATE_READY = 0x01U,
132  HAL_DMA2D_STATE_BUSY = 0x02U,
133  HAL_DMA2D_STATE_TIMEOUT = 0x03U,
134  HAL_DMA2D_STATE_ERROR = 0x04U,
135  HAL_DMA2D_STATE_SUSPEND = 0x05U
136 }HAL_DMA2D_StateTypeDef;
137 
141 typedef struct __DMA2D_HandleTypeDef
142 {
143  DMA2D_TypeDef *Instance;
145  DMA2D_InitTypeDef Init;
147  void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);
149  void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d);
151 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
152  void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d);
154  void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d);
156  void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d);
158  void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d);
160 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
161 
162  DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER];
164  HAL_LockTypeDef Lock;
166  __IO HAL_DMA2D_StateTypeDef State;
168  __IO uint32_t ErrorCode;
169 } DMA2D_HandleTypeDef;
170 
171 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
172 
175 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d);
176 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
177 
181 /* Exported constants --------------------------------------------------------*/
189 #define HAL_DMA2D_ERROR_NONE 0x00000000U
190 #define HAL_DMA2D_ERROR_TE 0x00000001U
191 #define HAL_DMA2D_ERROR_CE 0x00000002U
192 #define HAL_DMA2D_ERROR_CAE 0x00000004U
193 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U
194 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
195 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U
196 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
197 
205 #define DMA2D_M2M 0x00000000U
206 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0
207 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1
208 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0)
209 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2
210 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0)
218 #define DMA2D_OUTPUT_ARGB8888 0x00000000U
219 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0
220 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1
221 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
222 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2
230 #define DMA2D_INPUT_ARGB8888 0x00000000U
231 #define DMA2D_INPUT_RGB888 0x00000001U
232 #define DMA2D_INPUT_RGB565 0x00000002U
233 #define DMA2D_INPUT_ARGB1555 0x00000003U
234 #define DMA2D_INPUT_ARGB4444 0x00000004U
235 #define DMA2D_INPUT_L8 0x00000005U
236 #define DMA2D_INPUT_AL44 0x00000006U
237 #define DMA2D_INPUT_AL88 0x00000007U
238 #define DMA2D_INPUT_L4 0x00000008U
239 #define DMA2D_INPUT_A8 0x00000009U
240 #define DMA2D_INPUT_A4 0x0000000AU
241 #define DMA2D_INPUT_YCBCR 0x0000000BU
249 #define DMA2D_NO_MODIF_ALPHA 0x00000000U
250 #define DMA2D_REPLACE_ALPHA 0x00000001U
251 #define DMA2D_COMBINE_ALPHA 0x00000002U
260 #define DMA2D_REGULAR_ALPHA 0x00000000U
261 #define DMA2D_INVERTED_ALPHA 0x00000001U
269 #define DMA2D_RB_REGULAR 0x00000000U
270 #define DMA2D_RB_SWAP 0x00000001U
280 #define DMA2D_LOM_PIXELS 0x00000000U
281 #define DMA2D_LOM_BYTES DMA2D_CR_LOM
289 #define DMA2D_BYTES_REGULAR 0x00000000U
290 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB
298 #define DMA2D_NO_CSS 0x00000000U
299 #define DMA2D_CSS_422 0x00000001U
300 #define DMA2D_CSS_420 0x00000002U
308 #define DMA2D_CCM_ARGB8888 0x00000000U
309 #define DMA2D_CCM_RGB888 0x00000001U
317 #define DMA2D_IT_CE DMA2D_CR_CEIE
318 #define DMA2D_IT_CTC DMA2D_CR_CTCIE
319 #define DMA2D_IT_CAE DMA2D_CR_CAEIE
320 #define DMA2D_IT_TW DMA2D_CR_TWIE
321 #define DMA2D_IT_TC DMA2D_CR_TCIE
322 #define DMA2D_IT_TE DMA2D_CR_TEIE
330 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF
331 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
332 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
333 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF
334 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF
335 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF
343 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort
348 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
349 
352 typedef enum
353 {
354  HAL_DMA2D_MSPINIT_CB_ID = 0x00U,
355  HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U,
356  HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U,
357  HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U,
358  HAL_DMA2D_LINEEVENT_CB_ID = 0x04U,
359  HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U,
360 }HAL_DMA2D_CallbackIDTypeDef;
361 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
362 
363 
367 /* Exported macros ------------------------------------------------------------*/
376 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
377 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
378  (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
379  (__HANDLE__)->MspInitCallback = NULL; \
380  (__HANDLE__)->MspDeInitCallback = NULL; \
381  }while(0)
382 #else
383 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
384 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
385 
386 
392 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
393 
394 
395 /* Interrupt & Flag management */
409 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
410 
424 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
425 
439 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
440 
454 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
455 
469 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
470 
475 /* Exported functions --------------------------------------------------------*/
484 /* Initialization and de-initialization functions *******************************/
485 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
486 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
487 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
488 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
489 /* Callbacks Register/UnRegister functions ***********************************/
490 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
491 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
492 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
493 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
494 
504 /* IO operation functions *******************************************************/
505 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
506 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
507 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
508 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
509 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
510 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
511 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
512 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
513 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
514 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
515 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
516 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
517 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
518 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
519 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
520 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
521 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
522 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
523 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
524 
533 /* Peripheral Control functions *************************************************/
534 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
535 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
536 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
537 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
538 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
539 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
540 
549 /* Peripheral State functions ***************************************************/
550 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
551 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
552 
561 /* Private constants ---------------------------------------------------------*/
562 
570 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW
578 #define DMA2D_COLOR_VALUE 0x000000FFU
586 #define DMA2D_MAX_LAYER 2U
594 #define DMA2D_BACKGROUND_LAYER 0x00000000U
595 #define DMA2D_FOREGROUND_LAYER 0x00000001U
603 #define DMA2D_OFFSET DMA2D_FGOR_LO
611 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)
612 #define DMA2D_LINE DMA2D_NLR_NL
620 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U)
630 /* Private macros ------------------------------------------------------------*/
631 
634 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
635 
636 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
637  ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \
638  ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
639 
640 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
641  ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
642  ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
643 
644 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
645 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
646 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
647 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
648 
649 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
650  ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
651  ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
652  ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
653  ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
654  ((INPUT_CM) == DMA2D_INPUT_A4) || ((INPUT_CM) == DMA2D_INPUT_YCBCR))
655 
656 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
657  ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
658  ((AlphaMode) == DMA2D_COMBINE_ALPHA))
659 
660 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
661  ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
662 
663 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
664  ((RB_Swap) == DMA2D_RB_SWAP))
665 
666 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \
667  ((LOM) == DMA2D_LOM_BYTES))
668 
669 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
670  ((BYTES_SWAP) == DMA2D_BYTES_SWAP))
671 
672 #define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \
673  ((CSS) == DMA2D_CSS_422) || \
674  ((CSS) == DMA2D_CSS_420))
675 
676 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
677 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
678 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
679 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
680  ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
681  ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
682 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
683  ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
684  ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
685 
693 #endif /* defined (DMA2D) */
694 
699 #ifdef __cplusplus
700 }
701 #endif
702 
703 #endif /* STM32H7xx_HAL_DMA2D_H */
704 
705 
706 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
Init
napi_value Init(napi_env env, napi_value exports)
Definition: porcupine/demo/c/pvrecorder/node/pv_recorder_napi.c:197
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f469xx.h:377
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:54