stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_DMA2D_H
22 #define STM32H7xx_HAL_DMA2D_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
35 #if defined (DMA2D)
36 
42 /* Exported types ------------------------------------------------------------*/
46 #define MAX_DMA2D_LAYER 2U
51 typedef struct
52 {
53  uint32_t *pCLUT;
55  uint32_t CLUTColorMode;
58  uint32_t Size;
60 } DMA2D_CLUTCfgTypeDef;
61 
65 typedef struct
66 {
67  uint32_t Mode;
70  uint32_t ColorMode;
73  uint32_t OutputOffset;
76  uint32_t AlphaInverted;
79  uint32_t RedBlueSwap;
84  uint32_t BytesSwap;
87  uint32_t LineOffsetMode;
90 } DMA2D_InitTypeDef;
91 
92 
96 typedef struct
97 {
98  uint32_t InputOffset;
102  uint32_t InputColorMode;
105  uint32_t AlphaMode;
108  uint32_t InputAlpha;
119  uint32_t AlphaInverted;
122  uint32_t RedBlueSwap;
125  uint32_t ChromaSubSampling;
128 } DMA2D_LayerCfgTypeDef;
129 
133 typedef enum
134 {
135  HAL_DMA2D_STATE_RESET = 0x00U,
136  HAL_DMA2D_STATE_READY = 0x01U,
137  HAL_DMA2D_STATE_BUSY = 0x02U,
138  HAL_DMA2D_STATE_TIMEOUT = 0x03U,
139  HAL_DMA2D_STATE_ERROR = 0x04U,
140  HAL_DMA2D_STATE_SUSPEND = 0x05U
141 } HAL_DMA2D_StateTypeDef;
142 
146 typedef struct __DMA2D_HandleTypeDef
147 {
148  DMA2D_TypeDef *Instance;
150  DMA2D_InitTypeDef Init;
152  void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
154  void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
156 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
157  void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
159  void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
161  void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
163  void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
165 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
166 
167  DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER];
169  HAL_LockTypeDef Lock;
171  __IO HAL_DMA2D_StateTypeDef State;
173  __IO uint32_t ErrorCode;
174 } DMA2D_HandleTypeDef;
175 
176 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
177 
180 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d);
181 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
182 
186 /* Exported constants --------------------------------------------------------*/
194 #define HAL_DMA2D_ERROR_NONE 0x00000000U
195 #define HAL_DMA2D_ERROR_TE 0x00000001U
196 #define HAL_DMA2D_ERROR_CE 0x00000002U
197 #define HAL_DMA2D_ERROR_CAE 0x00000004U
198 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U
199 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
200 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U
201 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
202 
210 #define DMA2D_M2M 0x00000000U
211 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0
212 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1
213 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0)
214 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2
215 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0)
223 #define DMA2D_OUTPUT_ARGB8888 0x00000000U
224 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0
225 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1
226 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
227 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2
235 #define DMA2D_INPUT_ARGB8888 0x00000000U
236 #define DMA2D_INPUT_RGB888 0x00000001U
237 #define DMA2D_INPUT_RGB565 0x00000002U
238 #define DMA2D_INPUT_ARGB1555 0x00000003U
239 #define DMA2D_INPUT_ARGB4444 0x00000004U
240 #define DMA2D_INPUT_L8 0x00000005U
241 #define DMA2D_INPUT_AL44 0x00000006U
242 #define DMA2D_INPUT_AL88 0x00000007U
243 #define DMA2D_INPUT_L4 0x00000008U
244 #define DMA2D_INPUT_A8 0x00000009U
245 #define DMA2D_INPUT_A4 0x0000000AU
246 #define DMA2D_INPUT_YCBCR 0x0000000BU
254 #define DMA2D_NO_MODIF_ALPHA 0x00000000U
255 #define DMA2D_REPLACE_ALPHA 0x00000001U
256 #define DMA2D_COMBINE_ALPHA 0x00000002U
265 #define DMA2D_REGULAR_ALPHA 0x00000000U
266 #define DMA2D_INVERTED_ALPHA 0x00000001U
274 #define DMA2D_RB_REGULAR 0x00000000U
275 #define DMA2D_RB_SWAP 0x00000001U
285 #define DMA2D_LOM_PIXELS 0x00000000U
286 #define DMA2D_LOM_BYTES DMA2D_CR_LOM
294 #define DMA2D_BYTES_REGULAR 0x00000000U
295 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB
303 #define DMA2D_NO_CSS 0x00000000U
304 #define DMA2D_CSS_422 0x00000001U
305 #define DMA2D_CSS_420 0x00000002U
313 #define DMA2D_CCM_ARGB8888 0x00000000U
314 #define DMA2D_CCM_RGB888 0x00000001U
322 #define DMA2D_IT_CE DMA2D_CR_CEIE
323 #define DMA2D_IT_CTC DMA2D_CR_CTCIE
324 #define DMA2D_IT_CAE DMA2D_CR_CAEIE
325 #define DMA2D_IT_TW DMA2D_CR_TWIE
326 #define DMA2D_IT_TC DMA2D_CR_TCIE
327 #define DMA2D_IT_TE DMA2D_CR_TEIE
335 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF
336 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
337 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
338 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF
339 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF
340 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF
348 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort
354 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
355 
358 typedef enum
359 {
360  HAL_DMA2D_MSPINIT_CB_ID = 0x00U,
361  HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U,
362  HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U,
363  HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U,
364  HAL_DMA2D_LINEEVENT_CB_ID = 0x04U,
365  HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U,
366 } HAL_DMA2D_CallbackIDTypeDef;
367 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
368 
369 
373 /* Exported macros ------------------------------------------------------------*/
382 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
383 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
384  (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
385  (__HANDLE__)->MspInitCallback = NULL; \
386  (__HANDLE__)->MspDeInitCallback = NULL; \
387  }while(0)
388 #else
389 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
390 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
391 
392 
398 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
399 
400 
401 /* Interrupt & Flag management */
415 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
416 
430 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
431 
445 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
446 
460 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
461 
475 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
476 
481 /* Exported functions --------------------------------------------------------*/
490 /* Initialization and de-initialization functions *******************************/
491 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
492 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
493 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
494 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
495 /* Callbacks Register/UnRegister functions ***********************************/
496 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
497 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
498  pDMA2D_CallbackTypeDef pCallback);
499 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
500 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
501 
511 /* IO operation functions *******************************************************/
512 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
513  uint32_t Height);
514 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
515  uint32_t DstAddress, uint32_t Width, uint32_t Height);
516 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
517  uint32_t Height);
518 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
519  uint32_t DstAddress, uint32_t Width, uint32_t Height);
520 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
521 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
522 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
523 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
524 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
525  uint32_t LayerIdx);
526 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg,
527  uint32_t LayerIdx);
528 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
529 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
530 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
531 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
532 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
533 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
534 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
535 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
536 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
537 
546 /* Peripheral Control functions *************************************************/
547 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
548 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
549 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
550 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
551 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
552 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
553 
562 /* Peripheral State functions ***************************************************/
563 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
564 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
565 
574 /* Private constants ---------------------------------------------------------*/
575 
583 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW
591 #define DMA2D_COLOR_VALUE 0x000000FFU
599 #define DMA2D_MAX_LAYER 2U
607 #define DMA2D_BACKGROUND_LAYER 0x00000000U
608 #define DMA2D_FOREGROUND_LAYER 0x00000001U
616 #define DMA2D_OFFSET DMA2D_FGOR_LO
624 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)
625 #define DMA2D_LINE DMA2D_NLR_NL
633 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U)
643 /* Private macros ------------------------------------------------------------*/
644 
647 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
648  || ((LAYER) == DMA2D_FOREGROUND_LAYER))
649 
650 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
651  ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \
652  ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
653 
654 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
655  ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
656  ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
657  ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
658  ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
659 
660 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
661 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
662 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
663 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
664 
665 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
666  ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
667  ((INPUT_CM) == DMA2D_INPUT_RGB565) || \
668  ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
669  ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
670  ((INPUT_CM) == DMA2D_INPUT_L8) || \
671  ((INPUT_CM) == DMA2D_INPUT_AL44) || \
672  ((INPUT_CM) == DMA2D_INPUT_AL88) || \
673  ((INPUT_CM) == DMA2D_INPUT_L4) || \
674  ((INPUT_CM) == DMA2D_INPUT_A8) || \
675  ((INPUT_CM) == DMA2D_INPUT_A4) || \
676  ((INPUT_CM) == DMA2D_INPUT_YCBCR))
677 
678 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
679  ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
680  ((AlphaMode) == DMA2D_COMBINE_ALPHA))
681 
682 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
683  ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
684 
685 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
686  ((RB_Swap) == DMA2D_RB_SWAP))
687 
688 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \
689  ((LOM) == DMA2D_LOM_BYTES))
690 
691 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
692  ((BYTES_SWAP) == DMA2D_BYTES_SWAP))
693 
694 #define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \
695  ((CSS) == DMA2D_CSS_422) || \
696  ((CSS) == DMA2D_CSS_420))
697 
698 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
699 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
700 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
701 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
702  ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
703  ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
704 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
705  ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
706  ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
707 
715 #endif /* defined (DMA2D) */
716 
721 #ifdef __cplusplus
722 }
723 #endif
724 
725 #endif /* STM32H7xx_HAL_DMA2D_H */
726 
727 
728 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
Init
napi_value Init(napi_env env, napi_value exports)
Definition: porcupine/demo/c/pvrecorder/node/pv_recorder_napi.c:197
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f469xx.h:377
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:54