Classes | Macros | Functions
stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h File Reference

Go to the source code of this file.

Classes

struct  ARM_MPU_Region_t
 

Macros

#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)
 
#define ARM_MPU_ACCESS_DEVICE(IsShareable)   ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
 
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable)   ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
 
#define ARM_MPU_ACCESS_ORDERED   ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
 
#define ARM_MPU_AP_FULL   3U
 
#define ARM_MPU_AP_NONE   0U
 
#define ARM_MPU_AP_PRIV   1U
 
#define ARM_MPU_AP_PRO   5U
 
#define ARM_MPU_AP_RO   6U
 
#define ARM_MPU_AP_URO   2U
 
#define ARM_MPU_ARMV7_H
 
#define ARM_MPU_CACHEP_NOCACHE   0U
 
#define ARM_MPU_CACHEP_WB_NWA   3U
 
#define ARM_MPU_CACHEP_WB_WRA   1U
 
#define ARM_MPU_CACHEP_WT_NWA   2U
 
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)   ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
 
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)
 
#define ARM_MPU_RBAR(Region, BaseAddress)
 
#define ARM_MPU_REGION_SIZE_128B   ((uint8_t)0x06U)
 
#define ARM_MPU_REGION_SIZE_128KB   ((uint8_t)0x10U)
 
#define ARM_MPU_REGION_SIZE_128MB   ((uint8_t)0x1AU)
 
#define ARM_MPU_REGION_SIZE_16KB   ((uint8_t)0x0DU)
 
#define ARM_MPU_REGION_SIZE_16MB   ((uint8_t)0x17U)
 
#define ARM_MPU_REGION_SIZE_1GB   ((uint8_t)0x1DU)
 
#define ARM_MPU_REGION_SIZE_1KB   ((uint8_t)0x09U)
 
#define ARM_MPU_REGION_SIZE_1MB   ((uint8_t)0x13U)
 
#define ARM_MPU_REGION_SIZE_256B   ((uint8_t)0x07U)
 
#define ARM_MPU_REGION_SIZE_256KB   ((uint8_t)0x11U)
 
#define ARM_MPU_REGION_SIZE_256MB   ((uint8_t)0x1BU)
 
#define ARM_MPU_REGION_SIZE_2GB   ((uint8_t)0x1EU)
 
#define ARM_MPU_REGION_SIZE_2KB   ((uint8_t)0x0AU)
 
#define ARM_MPU_REGION_SIZE_2MB   ((uint8_t)0x14U)
 
#define ARM_MPU_REGION_SIZE_32B   ((uint8_t)0x04U)
 
#define ARM_MPU_REGION_SIZE_32KB   ((uint8_t)0x0EU)
 
#define ARM_MPU_REGION_SIZE_32MB   ((uint8_t)0x18U)
 
#define ARM_MPU_REGION_SIZE_4GB   ((uint8_t)0x1FU)
 
#define ARM_MPU_REGION_SIZE_4KB   ((uint8_t)0x0BU)
 
#define ARM_MPU_REGION_SIZE_4MB   ((uint8_t)0x15U)
 
#define ARM_MPU_REGION_SIZE_512B   ((uint8_t)0x08U)
 
#define ARM_MPU_REGION_SIZE_512KB   ((uint8_t)0x12U)
 
#define ARM_MPU_REGION_SIZE_512MB   ((uint8_t)0x1CU)
 
#define ARM_MPU_REGION_SIZE_64B   ((uint8_t)0x05U)
 
#define ARM_MPU_REGION_SIZE_64KB   ((uint8_t)0x0FU)
 
#define ARM_MPU_REGION_SIZE_64MB   ((uint8_t)0x19U)
 
#define ARM_MPU_REGION_SIZE_8KB   ((uint8_t)0x0CU)
 
#define ARM_MPU_REGION_SIZE_8MB   ((uint8_t)0x16U)
 

Functions

__STATIC_INLINE void ARM_MPU_ClrRegion (uint32_t rnr)
 
__STATIC_INLINE void ARM_MPU_Disable (void)
 
__STATIC_INLINE void ARM_MPU_Enable (uint32_t MPU_Control)
 
__STATIC_INLINE void ARM_MPU_Load (ARM_MPU_Region_t const *table, uint32_t cnt)
 
__STATIC_INLINE void ARM_MPU_SetRegion (uint32_t rbar, uint32_t rasr)
 
__STATIC_INLINE void ARM_MPU_SetRegionEx (uint32_t rnr, uint32_t rbar, uint32_t rasr)
 
__STATIC_INLINE void orderedCpy (volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
 

Macro Definition Documentation

◆ ARM_MPU_ACCESS_

#define ARM_MPU_ACCESS_ (   TypeExtField,
  IsShareable,
  IsCacheable,
  IsBufferable 
)
Value:
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))

MPU Memory Access Attributes

Parameters
TypeExtFieldType extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
IsShareableRegion is shareable between multiple bus masters.
IsCacheableRegion is cacheable, i.e. its value may be kept in cache.
IsBufferableRegion is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.

Definition at line 88 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_ACCESS_DEVICE

#define ARM_MPU_ACCESS_DEVICE (   IsShareable)    ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))

MPU Memory Access Attribute for device memory.

  • TEX: 000b (if non-shareable) or 010b (if shareable)
  • Shareable or non-shareable
  • Non-cacheable
  • Bufferable (if shareable) or non-bufferable (if non-shareable)
Parameters
IsShareableConfigures the device memory as shareable or non-shareable.

Definition at line 141 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_ACCESS_NORMAL

#define ARM_MPU_ACCESS_NORMAL (   OuterCp,
  InnerCp,
  IsShareable 
)    ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))

MPU Memory Access Attribute for normal memory.

  • TEX: 1BBb (reflecting outer cacheability rules)
  • Shareable or non-shareable
  • Cacheable or non-cacheable (reflecting inner cacheability rules)
  • Bufferable or non-bufferable (reflecting inner cacheability rules)
Parameters
OuterCpConfigures the outer cache policy.
InnerCpConfigures the inner cache policy.
IsShareableConfigures the memory as shareable or non-shareable.

Definition at line 154 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_ACCESS_ORDERED

#define ARM_MPU_ACCESS_ORDERED   ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)

MPU Memory Access Attribute for strongly ordered memory.

  • TEX: 000b
  • Shareable
  • Non-cacheable
  • Non-bufferable

Definition at line 130 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_AP_FULL

#define ARM_MPU_AP_FULL   3U

◆ ARM_MPU_AP_NONE

#define ARM_MPU_AP_NONE   0U

◆ ARM_MPU_AP_PRIV

#define ARM_MPU_AP_PRIV   1U

◆ ARM_MPU_AP_PRO

#define ARM_MPU_AP_PRO   5U

◆ ARM_MPU_AP_RO

#define ARM_MPU_AP_RO   6U

◆ ARM_MPU_AP_URO

#define ARM_MPU_AP_URO   2U

◆ ARM_MPU_ARMV7_H

#define ARM_MPU_ARMV7_H

◆ ARM_MPU_CACHEP_NOCACHE

#define ARM_MPU_CACHEP_NOCACHE   0U

MPU Memory Access Attribute non-cacheable policy.

Definition at line 159 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_CACHEP_WB_NWA

#define ARM_MPU_CACHEP_WB_NWA   3U

MPU Memory Access Attribute write-back, no write allocate policy.

Definition at line 174 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_CACHEP_WB_WRA

#define ARM_MPU_CACHEP_WB_WRA   1U

MPU Memory Access Attribute write-back, write and read allocate policy.

Definition at line 164 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_CACHEP_WT_NWA

#define ARM_MPU_CACHEP_WT_NWA   2U

MPU Memory Access Attribute write-through, no write allocate policy.

Definition at line 169 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_RASR

#define ARM_MPU_RASR (   DisableExec,
  AccessPermission,
  TypeExtField,
  IsShareable,
  IsCacheable,
  IsBufferable,
  SubRegionDisable,
  Size 
)    ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)

MPU Region Attribute and Size Register Value

Parameters
DisableExecInstruction access disable bit, 1= disable instruction fetches.
AccessPermissionData access permissions, allows you to configure read/write access for User and Privileged mode.
TypeExtFieldType extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
IsShareableRegion is shareable between multiple bus masters.
IsCacheableRegion is cacheable, i.e. its value may be kept in cache.
IsBufferableRegion is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
SubRegionDisableSub-region disable field.
SizeRegion size of the region to be configured, for example 4K, 8K.

Definition at line 120 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_RASR_EX

#define ARM_MPU_RASR_EX (   DisableExec,
  AccessPermission,
  AccessAttributes,
  SubRegionDisable,
  Size 
)
Value:
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))

MPU Region Attribute and Size Register Value

Parameters
DisableExecInstruction access disable bit, 1= disable instruction fetches.
AccessPermissionData access permissions, allows you to configure read/write access for User and Privileged mode.
AccessAttributesMemory access attribution, see ARM_MPU_ACCESS_.
SubRegionDisableSub-region disable field.
SizeRegion size of the region to be configured, for example 4K, 8K.

Definition at line 103 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_RBAR

#define ARM_MPU_RBAR (   Region,
  BaseAddress 
)
Value:
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))

MPU Region Base Address Register Value

Parameters
RegionThe region to be configured, number 0 to 15.
BaseAddressThe base address for the region.

Definition at line 75 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_REGION_SIZE_128B

#define ARM_MPU_REGION_SIZE_128B   ((uint8_t)0x06U)

◆ ARM_MPU_REGION_SIZE_128KB

#define ARM_MPU_REGION_SIZE_128KB   ((uint8_t)0x10U)

◆ ARM_MPU_REGION_SIZE_128MB

#define ARM_MPU_REGION_SIZE_128MB   ((uint8_t)0x1AU)

◆ ARM_MPU_REGION_SIZE_16KB

#define ARM_MPU_REGION_SIZE_16KB   ((uint8_t)0x0DU)

◆ ARM_MPU_REGION_SIZE_16MB

#define ARM_MPU_REGION_SIZE_16MB   ((uint8_t)0x17U)

◆ ARM_MPU_REGION_SIZE_1GB

#define ARM_MPU_REGION_SIZE_1GB   ((uint8_t)0x1DU)

◆ ARM_MPU_REGION_SIZE_1KB

#define ARM_MPU_REGION_SIZE_1KB   ((uint8_t)0x09U)

◆ ARM_MPU_REGION_SIZE_1MB

#define ARM_MPU_REGION_SIZE_1MB   ((uint8_t)0x13U)

◆ ARM_MPU_REGION_SIZE_256B

#define ARM_MPU_REGION_SIZE_256B   ((uint8_t)0x07U)

◆ ARM_MPU_REGION_SIZE_256KB

#define ARM_MPU_REGION_SIZE_256KB   ((uint8_t)0x11U)

◆ ARM_MPU_REGION_SIZE_256MB

#define ARM_MPU_REGION_SIZE_256MB   ((uint8_t)0x1BU)

◆ ARM_MPU_REGION_SIZE_2GB

#define ARM_MPU_REGION_SIZE_2GB   ((uint8_t)0x1EU)

◆ ARM_MPU_REGION_SIZE_2KB

#define ARM_MPU_REGION_SIZE_2KB   ((uint8_t)0x0AU)

◆ ARM_MPU_REGION_SIZE_2MB

#define ARM_MPU_REGION_SIZE_2MB   ((uint8_t)0x14U)

◆ ARM_MPU_REGION_SIZE_32B

#define ARM_MPU_REGION_SIZE_32B   ((uint8_t)0x04U)

◆ ARM_MPU_REGION_SIZE_32KB

#define ARM_MPU_REGION_SIZE_32KB   ((uint8_t)0x0EU)

◆ ARM_MPU_REGION_SIZE_32MB

#define ARM_MPU_REGION_SIZE_32MB   ((uint8_t)0x18U)

◆ ARM_MPU_REGION_SIZE_4GB

#define ARM_MPU_REGION_SIZE_4GB   ((uint8_t)0x1FU)

◆ ARM_MPU_REGION_SIZE_4KB

#define ARM_MPU_REGION_SIZE_4KB   ((uint8_t)0x0BU)

◆ ARM_MPU_REGION_SIZE_4MB

#define ARM_MPU_REGION_SIZE_4MB   ((uint8_t)0x15U)

◆ ARM_MPU_REGION_SIZE_512B

#define ARM_MPU_REGION_SIZE_512B   ((uint8_t)0x08U)

◆ ARM_MPU_REGION_SIZE_512KB

#define ARM_MPU_REGION_SIZE_512KB   ((uint8_t)0x12U)

◆ ARM_MPU_REGION_SIZE_512MB

#define ARM_MPU_REGION_SIZE_512MB   ((uint8_t)0x1CU)

◆ ARM_MPU_REGION_SIZE_64B

#define ARM_MPU_REGION_SIZE_64B   ((uint8_t)0x05U)

◆ ARM_MPU_REGION_SIZE_64KB

#define ARM_MPU_REGION_SIZE_64KB   ((uint8_t)0x0FU)

◆ ARM_MPU_REGION_SIZE_64MB

#define ARM_MPU_REGION_SIZE_64MB   ((uint8_t)0x19U)

◆ ARM_MPU_REGION_SIZE_8KB

#define ARM_MPU_REGION_SIZE_8KB   ((uint8_t)0x0CU)

◆ ARM_MPU_REGION_SIZE_8MB

#define ARM_MPU_REGION_SIZE_8MB   ((uint8_t)0x16U)

Function Documentation

◆ ARM_MPU_ClrRegion()

__STATIC_INLINE void ARM_MPU_ClrRegion ( uint32_t  rnr)

Clear and disable the given MPU region.

Parameters
rnrRegion number to be cleared.

Definition at line 213 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_Disable()

__STATIC_INLINE void ARM_MPU_Disable ( void  )

Disable the MPU.

Definition at line 200 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_Enable()

__STATIC_INLINE void ARM_MPU_Enable ( uint32_t  MPU_Control)

Enable the MPU.

Parameters
MPU_ControlDefault access permissions for unconfigured regions.

Definition at line 188 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_Load()

__STATIC_INLINE void ARM_MPU_Load ( ARM_MPU_Region_t const *  table,
uint32_t  cnt 
)

Load the given number of MPU regions from a table.

Parameters
tablePointer to the MPU configuration table.
cntAmount of regions to be configured.

Definition at line 259 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_SetRegion()

__STATIC_INLINE void ARM_MPU_SetRegion ( uint32_t  rbar,
uint32_t  rasr 
)

Configure an MPU region.

Parameters
rbarValue for RBAR register.
rsarValue for RSAR register.

Definition at line 223 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ ARM_MPU_SetRegionEx()

__STATIC_INLINE void ARM_MPU_SetRegionEx ( uint32_t  rnr,
uint32_t  rbar,
uint32_t  rasr 
)

Configure the given MPU region.

Parameters
rnrRegion number to be configured.
rbarValue for RBAR register.
rsarValue for RSAR register.

Definition at line 234 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.

◆ orderedCpy()

__STATIC_INLINE void orderedCpy ( volatile uint32_t *  dst,
const uint32_t *__RESTRICT  src,
uint32_t  len 
)

Memcopy with strictly ordered memory access, e.g. for register targets.

Parameters
dstDestination data is copied to.
srcSource data is copied from.
lenAmount of data words to be copied.

Definition at line 246 of file stm32f407/stm32f407g-disc1/Drivers/CMSIS/Include/mpu_armv7.h.



picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:00