27 #ifndef __CMSIS_ICCARM_H__
28 #define __CMSIS_ICCARM_H__
31 #error This file should only be compiled by ICCARM
34 #pragma system_include
36 #define __IAR_FT _Pragma("inline=forced") __intrinsic
38 #if (__VER__ >= 8000000)
46 #define __ALIGNED(x) __attribute__((aligned(x)))
47 #elif (__VER__ >= 7080000)
49 #define __ALIGNED(x) __attribute__((aligned(x)))
51 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
59 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
62 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
63 #define __ARM_ARCH_8M_MAIN__ 1
64 #elif defined(__ARM8M_BASELINE__)
65 #define __ARM_ARCH_8M_BASE__ 1
66 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
68 #define __ARM_ARCH_6M__ 1
71 #define __ARM_ARCH_7EM__ 1
73 #define __ARM_ARCH_7M__ 1
80 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
81 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
82 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
83 #define __ARM_ARCH_6M__ 1
84 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
85 #define __ARM_ARCH_7M__ 1
86 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
87 #define __ARM_ARCH_7EM__ 1
88 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
89 #define __ARM_ARCH_8M_BASE__ 1
90 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
91 #define __ARM_ARCH_8M_MAIN__ 1
92 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
93 #define __ARM_ARCH_8M_MAIN__ 1
95 #error "Unknown target."
101 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
102 #define __IAR_M0_FAMILY 1
103 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
104 #define __IAR_M0_FAMILY 1
106 #define __IAR_M0_FAMILY 0
114 #ifndef __COMPILER_BARRIER
115 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
119 #define __INLINE inline
124 #define __NO_RETURN __attribute__((__noreturn__))
126 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
132 #define __PACKED __attribute__((packed, aligned(1)))
135 #define __PACKED __packed
139 #ifndef __PACKED_STRUCT
141 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
144 #define __PACKED_STRUCT __packed struct
148 #ifndef __PACKED_UNION
150 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
153 #define __PACKED_UNION __packed union
159 #define __RESTRICT __restrict
162 #define __RESTRICT restrict
166 #ifndef __STATIC_INLINE
167 #define __STATIC_INLINE static inline
170 #ifndef __FORCEINLINE
171 #define __FORCEINLINE _Pragma("inline=forced")
174 #ifndef __STATIC_FORCEINLINE
175 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
178 #ifndef __UNALIGNED_UINT16_READ
179 #pragma language=save
180 #pragma language=extended
183 return *(__packed uint16_t*)(ptr);
185 #pragma language=restore
186 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
190 #ifndef __UNALIGNED_UINT16_WRITE
191 #pragma language=save
192 #pragma language=extended
195 *(__packed uint16_t*)(ptr) = val;;
197 #pragma language=restore
198 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
201 #ifndef __UNALIGNED_UINT32_READ
202 #pragma language=save
203 #pragma language=extended
206 return *(__packed uint32_t*)(ptr);
208 #pragma language=restore
209 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
212 #ifndef __UNALIGNED_UINT32_WRITE
213 #pragma language=save
214 #pragma language=extended
217 *(__packed uint32_t*)(ptr) = val;;
219 #pragma language=restore
220 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
223 #ifndef __UNALIGNED_UINT32
224 #pragma language=save
225 #pragma language=extended
227 #pragma language=restore
228 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
233 #define __USED __attribute__((used))
235 #define __USED _Pragma("__root")
241 #define __WEAK __attribute__((weak))
243 #define __WEAK _Pragma("__weak")
247 #ifndef __PROGRAM_START
248 #define __PROGRAM_START __iar_program_start
252 #define __INITIAL_SP CSTACK$$Limit
255 #ifndef __STACK_LIMIT
256 #define __STACK_LIMIT CSTACK$$Base
259 #ifndef __VECTOR_TABLE
260 #define __VECTOR_TABLE __vector_table
263 #ifndef __VECTOR_TABLE_ATTRIBUTE
264 #define __VECTOR_TABLE_ATTRIBUTE @".intvec"
267 #ifndef __ICCARM_INTRINSICS_VERSION__
268 #define __ICCARM_INTRINSICS_VERSION__ 0
271 #if __ICCARM_INTRINSICS_VERSION__ == 2
289 #include "iccarm_builtin.h"
291 #define __disable_fault_irq __iar_builtin_disable_fiq
292 #define __disable_irq __iar_builtin_disable_interrupt
293 #define __enable_fault_irq __iar_builtin_enable_fiq
294 #define __enable_irq __iar_builtin_enable_interrupt
295 #define __arm_rsr __iar_builtin_rsr
296 #define __arm_wsr __iar_builtin_wsr
299 #define __get_APSR() (__arm_rsr("APSR"))
300 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
301 #define __get_CONTROL() (__arm_rsr("CONTROL"))
302 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
304 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
305 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
306 #define __get_FPSCR() (__arm_rsr("FPSCR"))
307 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
309 #define __get_FPSCR() ( 0 )
310 #define __set_FPSCR(VALUE) ((void)VALUE)
313 #define __get_IPSR() (__arm_rsr("IPSR"))
314 #define __get_MSP() (__arm_rsr("MSP"))
315 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
316 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
318 #define __get_MSPLIM() (0U)
320 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
322 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
323 #define __get_PSP() (__arm_rsr("PSP"))
325 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
326 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
328 #define __get_PSPLIM() (0U)
330 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
333 #define __get_xPSR() (__arm_rsr("xPSR"))
335 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
336 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
337 #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
338 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
339 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
341 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
342 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
344 #define __set_MSPLIM(VALUE) ((void)(VALUE))
346 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
348 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
349 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
350 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
351 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
353 #define __set_PSPLIM(VALUE) ((void)(VALUE))
355 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
358 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
359 #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
360 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
361 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
362 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
363 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
364 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
365 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
366 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
367 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
368 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
369 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
370 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
371 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
373 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
374 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
376 #define __TZ_get_PSPLIM_NS() (0U)
377 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
379 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
380 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
383 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
384 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
386 #define __NOP __iar_builtin_no_operation
388 #define __CLZ __iar_builtin_CLZ
389 #define __CLREX __iar_builtin_CLREX
391 #define __DMB __iar_builtin_DMB
392 #define __DSB __iar_builtin_DSB
393 #define __ISB __iar_builtin_ISB
395 #define __LDREXB __iar_builtin_LDREXB
396 #define __LDREXH __iar_builtin_LDREXH
397 #define __LDREXW __iar_builtin_LDREX
399 #define __RBIT __iar_builtin_RBIT
400 #define __REV __iar_builtin_REV
401 #define __REV16 __iar_builtin_REV16
405 return (int16_t) __iar_builtin_REVSH(val);
408 #define __ROR __iar_builtin_ROR
409 #define __RRX __iar_builtin_RRX
411 #define __SEV __iar_builtin_SEV
414 #define __SSAT __iar_builtin_SSAT
417 #define __STREXB __iar_builtin_STREXB
418 #define __STREXH __iar_builtin_STREXH
419 #define __STREXW __iar_builtin_STREX
422 #define __USAT __iar_builtin_USAT
425 #define __WFE __iar_builtin_WFE
426 #define __WFI __iar_builtin_WFI
429 #define __SADD8 __iar_builtin_SADD8
430 #define __QADD8 __iar_builtin_QADD8
431 #define __SHADD8 __iar_builtin_SHADD8
432 #define __UADD8 __iar_builtin_UADD8
433 #define __UQADD8 __iar_builtin_UQADD8
434 #define __UHADD8 __iar_builtin_UHADD8
435 #define __SSUB8 __iar_builtin_SSUB8
436 #define __QSUB8 __iar_builtin_QSUB8
437 #define __SHSUB8 __iar_builtin_SHSUB8
438 #define __USUB8 __iar_builtin_USUB8
439 #define __UQSUB8 __iar_builtin_UQSUB8
440 #define __UHSUB8 __iar_builtin_UHSUB8
441 #define __SADD16 __iar_builtin_SADD16
442 #define __QADD16 __iar_builtin_QADD16
443 #define __SHADD16 __iar_builtin_SHADD16
444 #define __UADD16 __iar_builtin_UADD16
445 #define __UQADD16 __iar_builtin_UQADD16
446 #define __UHADD16 __iar_builtin_UHADD16
447 #define __SSUB16 __iar_builtin_SSUB16
448 #define __QSUB16 __iar_builtin_QSUB16
449 #define __SHSUB16 __iar_builtin_SHSUB16
450 #define __USUB16 __iar_builtin_USUB16
451 #define __UQSUB16 __iar_builtin_UQSUB16
452 #define __UHSUB16 __iar_builtin_UHSUB16
453 #define __SASX __iar_builtin_SASX
454 #define __QASX __iar_builtin_QASX
455 #define __SHASX __iar_builtin_SHASX
456 #define __UASX __iar_builtin_UASX
457 #define __UQASX __iar_builtin_UQASX
458 #define __UHASX __iar_builtin_UHASX
459 #define __SSAX __iar_builtin_SSAX
460 #define __QSAX __iar_builtin_QSAX
461 #define __SHSAX __iar_builtin_SHSAX
462 #define __USAX __iar_builtin_USAX
463 #define __UQSAX __iar_builtin_UQSAX
464 #define __UHSAX __iar_builtin_UHSAX
465 #define __USAD8 __iar_builtin_USAD8
466 #define __USADA8 __iar_builtin_USADA8
467 #define __SSAT16 __iar_builtin_SSAT16
468 #define __USAT16 __iar_builtin_USAT16
469 #define __UXTB16 __iar_builtin_UXTB16
470 #define __UXTAB16 __iar_builtin_UXTAB16
471 #define __SXTB16 __iar_builtin_SXTB16
472 #define __SXTAB16 __iar_builtin_SXTAB16
473 #define __SMUAD __iar_builtin_SMUAD
474 #define __SMUADX __iar_builtin_SMUADX
475 #define __SMMLA __iar_builtin_SMMLA
476 #define __SMLAD __iar_builtin_SMLAD
477 #define __SMLADX __iar_builtin_SMLADX
478 #define __SMLALD __iar_builtin_SMLALD
479 #define __SMLALDX __iar_builtin_SMLALDX
480 #define __SMUSD __iar_builtin_SMUSD
481 #define __SMUSDX __iar_builtin_SMUSDX
482 #define __SMLSD __iar_builtin_SMLSD
483 #define __SMLSDX __iar_builtin_SMLSDX
484 #define __SMLSLD __iar_builtin_SMLSLD
485 #define __SMLSLDX __iar_builtin_SMLSLDX
486 #define __SEL __iar_builtin_SEL
487 #define __QADD __iar_builtin_QADD
488 #define __QSUB __iar_builtin_QSUB
489 #define __PKHBT __iar_builtin_PKHBT
490 #define __PKHTB __iar_builtin_PKHTB
497 #define __CLZ __cmsis_iar_clz_not_active
498 #define __SSAT __cmsis_iar_ssat_not_active
499 #define __USAT __cmsis_iar_usat_not_active
500 #define __RBIT __cmsis_iar_rbit_not_active
501 #define __get_APSR __cmsis_iar_get_APSR_not_active
505 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
506 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
507 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
508 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
511 #ifdef __INTRINSICS_INCLUDED
512 #error intrinsics.h is already included previously!
515 #include <intrinsics.h>
527 if (data == 0U) {
return 32U; }
530 uint32_t mask = 0x80000000U;
532 while ((data & mask) == 0U)
544 for (v >>= 1U; v; v >>= 1U)
556 __asm(
"MRS %0,APSR" :
"=r" (res));
562 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
563 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
566 #define __get_FPSCR() (0)
567 #define __set_FPSCR(VALUE) ((void)VALUE)
570 #pragma diag_suppress=Pe940
571 #pragma diag_suppress=Pe177
573 #define __enable_irq __enable_interrupt
574 #define __disable_irq __disable_interrupt
575 #define __NOP __no_operation
577 #define __get_xPSR __get_PSR
579 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
583 return __LDREX((
unsigned long *)ptr);
588 return __STREX(value, (
unsigned long *)ptr);
594 #if (__CORTEX_M >= 0x03)
596 __IAR_FT uint32_t __RRX(uint32_t value)
599 __ASM(
"RRX %0, %1" :
"=r"(result) :
"r" (value) :
"cc");
603 __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
605 __asm
volatile(
"MSR BASEPRI_MAX,%0"::
"r" (value));
609 #define __enable_fault_irq __enable_fiq
610 #define __disable_fault_irq __disable_fiq
617 return (op1 >> op2) | (op1 << ((
sizeof(op1)*8)-op2));
620 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
621 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
623 __IAR_FT uint32_t __get_MSPLIM(
void)
626 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
627 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
631 __asm
volatile(
"MRS %0,MSPLIM" :
"=r" (res));
636 __IAR_FT void __set_MSPLIM(uint32_t value)
638 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
639 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
643 __asm
volatile(
"MSR MSPLIM,%0" ::
"r" (value));
647 __IAR_FT uint32_t __get_PSPLIM(
void)
650 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
651 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
655 __asm
volatile(
"MRS %0,PSPLIM" :
"=r" (res));
660 __IAR_FT void __set_PSPLIM(uint32_t value)
662 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
663 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
667 __asm
volatile(
"MSR PSPLIM,%0" ::
"r" (value));
671 __IAR_FT uint32_t __TZ_get_CONTROL_NS(
void)
674 __asm
volatile(
"MRS %0,CONTROL_NS" :
"=r" (res));
678 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
680 __asm
volatile(
"MSR CONTROL_NS,%0" ::
"r" (value));
683 __IAR_FT uint32_t __TZ_get_PSP_NS(
void)
686 __asm
volatile(
"MRS %0,PSP_NS" :
"=r" (res));
690 __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
692 __asm
volatile(
"MSR PSP_NS,%0" ::
"r" (value));
695 __IAR_FT uint32_t __TZ_get_MSP_NS(
void)
698 __asm
volatile(
"MRS %0,MSP_NS" :
"=r" (res));
702 __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
704 __asm
volatile(
"MSR MSP_NS,%0" ::
"r" (value));
707 __IAR_FT uint32_t __TZ_get_SP_NS(
void)
710 __asm
volatile(
"MRS %0,SP_NS" :
"=r" (res));
713 __IAR_FT void __TZ_set_SP_NS(uint32_t value)
715 __asm
volatile(
"MSR SP_NS,%0" ::
"r" (value));
718 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(
void)
721 __asm
volatile(
"MRS %0,PRIMASK_NS" :
"=r" (res));
725 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
727 __asm
volatile(
"MSR PRIMASK_NS,%0" ::
"r" (value));
730 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(
void)
733 __asm
volatile(
"MRS %0,BASEPRI_NS" :
"=r" (res));
737 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
739 __asm
volatile(
"MSR BASEPRI_NS,%0" ::
"r" (value));
742 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(
void)
745 __asm
volatile(
"MRS %0,FAULTMASK_NS" :
"=r" (res));
749 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
751 __asm
volatile(
"MSR FAULTMASK_NS,%0" ::
"r" (value));
754 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(
void)
757 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
758 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
762 __asm
volatile(
"MRS %0,PSPLIM_NS" :
"=r" (res));
767 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
769 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
770 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
774 __asm
volatile(
"MSR PSPLIM_NS,%0" ::
"r" (value));
778 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(
void)
781 __asm
volatile(
"MRS %0,MSPLIM_NS" :
"=r" (res));
785 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
787 __asm
volatile(
"MSR MSPLIM_NS,%0" ::
"r" (value));
794 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
799 if ((
sat >= 1U) && (
sat <= 32U))
801 const int32_t max = (int32_t)((1U << (
sat - 1U)) - 1U);
802 const int32_t
min = -1 - max ;
819 const uint32_t max = ((1U <<
sat) - 1U);
820 if (val > (int32_t)max)
829 return (uint32_t)val;
833 #if (__CORTEX_M >= 0x03)
835 __IAR_FT uint8_t __LDRBT(
volatile uint8_t *addr)
838 __ASM(
"LDRBT %0, [%1]" :
"=r" (res) :
"r" (addr) :
"memory");
839 return ((uint8_t)res);
842 __IAR_FT uint16_t __LDRHT(
volatile uint16_t *addr)
845 __ASM(
"LDRHT %0, [%1]" :
"=r" (res) :
"r" (addr) :
"memory");
846 return ((uint16_t)res);
849 __IAR_FT uint32_t __LDRT(
volatile uint32_t *addr)
852 __ASM(
"LDRT %0, [%1]" :
"=r" (res) :
"r" (addr) :
"memory");
856 __IAR_FT void __STRBT(uint8_t value,
volatile uint8_t *addr)
858 __ASM(
"STRBT %1, [%0]" : :
"r" (addr),
"r" ((uint32_t)value) :
"memory");
861 __IAR_FT void __STRHT(uint16_t value,
volatile uint16_t *addr)
863 __ASM(
"STRHT %1, [%0]" : :
"r" (addr),
"r" ((uint32_t)value) :
"memory");
866 __IAR_FT void __STRT(uint32_t value,
volatile uint32_t *addr)
868 __ASM(
"STRT %1, [%0]" : :
"r" (addr),
"r" (value) :
"memory");
873 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
874 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
877 __IAR_FT uint8_t __LDAB(
volatile uint8_t *ptr)
880 __ASM volatile (
"LDAB %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
881 return ((uint8_t)res);
884 __IAR_FT uint16_t __LDAH(
volatile uint16_t *ptr)
887 __ASM volatile (
"LDAH %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
888 return ((uint16_t)res);
891 __IAR_FT uint32_t __LDA(
volatile uint32_t *ptr)
894 __ASM volatile (
"LDA %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
898 __IAR_FT void __STLB(uint8_t value,
volatile uint8_t *ptr)
900 __ASM volatile (
"STLB %1, [%0]" ::
"r" (ptr),
"r" (value) :
"memory");
903 __IAR_FT void __STLH(uint16_t value,
volatile uint16_t *ptr)
905 __ASM volatile (
"STLH %1, [%0]" ::
"r" (ptr),
"r" (value) :
"memory");
908 __IAR_FT void __STL(uint32_t value,
volatile uint32_t *ptr)
910 __ASM volatile (
"STL %1, [%0]" ::
"r" (ptr),
"r" (value) :
"memory");
913 __IAR_FT uint8_t __LDAEXB(
volatile uint8_t *ptr)
916 __ASM volatile (
"LDAEXB %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
917 return ((uint8_t)res);
920 __IAR_FT uint16_t __LDAEXH(
volatile uint16_t *ptr)
923 __ASM volatile (
"LDAEXH %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
924 return ((uint16_t)res);
927 __IAR_FT uint32_t __LDAEX(
volatile uint32_t *ptr)
930 __ASM volatile (
"LDAEX %0, [%1]" :
"=r" (res) :
"r" (ptr) :
"memory");
934 __IAR_FT uint32_t __STLEXB(uint8_t value,
volatile uint8_t *ptr)
937 __ASM volatile (
"STLEXB %0, %2, [%1]" :
"=r" (res) :
"r" (ptr),
"r" (value) :
"memory");
941 __IAR_FT uint32_t __STLEXH(uint16_t value,
volatile uint16_t *ptr)
944 __ASM volatile (
"STLEXH %0, %2, [%1]" :
"=r" (res) :
"r" (ptr),
"r" (value) :
"memory");
948 __IAR_FT uint32_t __STLEX(uint32_t value,
volatile uint32_t *ptr)
951 __ASM volatile (
"STLEX %0, %2, [%1]" :
"=r" (res) :
"r" (ptr),
"r" (value) :
"memory");
958 #undef __IAR_M0_FAMILY
961 #pragma diag_default=Pe940
962 #pragma diag_default=Pe177