Macros | |
| #define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL |
| #define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL |
| #define | TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL |
| #define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL |
| #define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL |
| #define | TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL |
| #define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL |
| #define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL |
| #define | TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL |
| #define | TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL |
| #define | TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL |
| #define | TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL |
Detailed Description
Macro Definition Documentation
◆ TIM_BREAK_SYSTEM_ECC [1/3]
| #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL |
Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17
Definition at line 1081 of file stm32f7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_ECC [2/3]
| #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL |
Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17
Definition at line 1119 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_ECC [3/3]
| #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL |
Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17
Definition at line 1119 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_LOCKUP [1/3]
| #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL |
Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17
Definition at line 1084 of file stm32f7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_LOCKUP [2/3]
| #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL |
Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17
Definition at line 1122 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_LOCKUP [3/3]
| #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL |
Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17
Definition at line 1122 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_PVD [1/3]
| #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL |
Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface
Definition at line 1082 of file stm32f7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_PVD [2/3]
| #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL |
Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface
Definition at line 1120 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_PVD [3/3]
| #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL |
Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface
Definition at line 1120 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR [1/3]
| #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL |
Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17
Definition at line 1083 of file stm32f7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR [2/3]
| #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL |
Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17
Definition at line 1121 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.
◆ TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR [3/3]
| #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL |
Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17
Definition at line 1121 of file stm32h747/stm32h747i-disco/CM7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h.