Modules | Macros
Collaboration diagram for FMC_LL Private Macros:

Modules

 FMC TCLR Setup Time
 
 FMC TAR Setup Time
 
 FMC Setup Time
 
 FMC Wait Setup Time
 
 FMC Hold Setup Time
 
 FMC HiZ Setup Time
 
 FMC Data Latency
 
 FMC Address Setup Time
 
 FMC Address Hold Time
 
 FMC Data Setup Time
 
 FMC Bus Turn around Duration
 
 FMC CLK Division
 
 FMC SDRAM LoadToActive Delay
 
 FMC SDRAM ExitSelfRefresh Delay
 
 FMC SDRAM SelfRefresh Time
 
 FMC SDRAM RowCycle Delay
 
 FMC SDRAM Write Recovery Time
 
 FMC SDRAM RP Delay
 
 FMC SDRAM RCD Delay
 
 FMC SDRAM AutoRefresh Number
 
 FMC SDRAM ModeRegister Definition
 
 FMC SDRAM Refresh rate
 
 FMC NORSRAM Device Instance
 
 FMC NORSRAM EXTENDED Device Instance
 
 FMC NAND Device Instance
 
 FMC SDRAM Device Instance
 
 FMC NOR/SRAM Macros
 macros to handle NOR device enable/disable and read/write operations
 
 FMC NAND Macros
 macros to handle NAND device enable/disable
 
 FMC Interrupt
 macros to handle FMC interrupts
 

Macros

#define IS_FMC_ACCESS_MODE(__MODE__)
 
#define IS_FMC_ASYNWAIT(__STATE__)
 
#define IS_FMC_BURSTMODE(__STATE__)
 
#define IS_FMC_CAS_LATENCY(LATENCY)
 
#define IS_FMC_COLUMNBITS_NUMBER(COLUMN)
 
#define IS_FMC_COMMAND_MODE(__COMMAND__)
 
#define IS_FMC_COMMAND_TARGET(__TARGET__)
 
#define IS_FMC_CONTINOUS_CLOCK(CCLOCK)
 
#define IS_FMC_ECC_STATE(STATE)
 
#define IS_FMC_ECCPAGE_SIZE(SIZE)
 
#define IS_FMC_EXTENDED_MODE(__MODE__)
 
#define IS_FMC_INTERNALBANK_NUMBER(NUMBER)
 
#define IS_FMC_MEMORY(__MEMORY__)
 
#define IS_FMC_MUX(__MUX__)
 
#define IS_FMC_NAND_BANK(BANK)   ((BANK) == FMC_NAND_BANK3)
 
#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH)
 
#define IS_FMC_NORSRAM_BANK(BANK)
 
#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__)
 
#define IS_FMC_PAGESIZE(__SIZE__)
 
#define IS_FMC_READ_BURST(__RBURST__)
 
#define IS_FMC_READPIPE_DELAY(__DELAY__)
 
#define IS_FMC_ROWBITS_NUMBER(ROW)
 
#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__)
 
#define IS_FMC_SDMEMORY_WIDTH(WIDTH)
 
#define IS_FMC_SDRAM_BANK(BANK)
 
#define IS_FMC_WAIT_FEATURE(FEATURE)
 
#define IS_FMC_WAIT_POLARITY(__POLARITY__)
 
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__)
 
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__)
 
#define IS_FMC_WRITE_BURST(__BURST__)
 
#define IS_FMC_WRITE_FIFO(__FIFO__)
 
#define IS_FMC_WRITE_OPERATION(__OPERATION__)
 
#define IS_FMC_WRITE_PROTECTION(__WRITE__)
 

Detailed Description

Macro Definition Documentation

◆ IS_FMC_ACCESS_MODE

#define IS_FMC_ACCESS_MODE (   __MODE__)
Value:
(((__MODE__) == FMC_ACCESS_MODE_A) || \
((__MODE__) == FMC_ACCESS_MODE_B) || \
((__MODE__) == FMC_ACCESS_MODE_C) || \
((__MODE__) == FMC_ACCESS_MODE_D))

Definition at line 58 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_ASYNWAIT

#define IS_FMC_ASYNWAIT (   __STATE__)
Value:
(((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))

Definition at line 177 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_BURSTMODE

#define IS_FMC_BURSTMODE (   __STATE__)
Value:
(((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))

Definition at line 159 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_CAS_LATENCY

#define IS_FMC_CAS_LATENCY (   LATENCY)
Value:
(((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))

Definition at line 363 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_COLUMNBITS_NUMBER

#define IS_FMC_COLUMNBITS_NUMBER (   COLUMN)
Value:
(((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \

Definition at line 350 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_COMMAND_MODE

#define IS_FMC_COMMAND_MODE (   __COMMAND__)
Value:
(((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))

Definition at line 99 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_COMMAND_TARGET

#define IS_FMC_COMMAND_TARGET (   __TARGET__)
Value:
(((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))

Definition at line 107 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_CONTINOUS_CLOCK

#define IS_FMC_CONTINOUS_CLOCK (   CCLOCK)
Value:

Definition at line 191 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_ECC_STATE

#define IS_FMC_ECC_STATE (   STATE)
Value:
(((STATE) == FMC_NAND_ECC_DISABLE) || \
((STATE) == FMC_NAND_ECC_ENABLE))

Definition at line 71 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_ECCPAGE_SIZE

#define IS_FMC_ECCPAGE_SIZE (   SIZE)
Value:

Definition at line 74 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_EXTENDED_MODE

#define IS_FMC_EXTENDED_MODE (   __MODE__)
Value:
(((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FMC_EXTENDED_MODE_ENABLE))

Definition at line 174 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_INTERNALBANK_NUMBER

#define IS_FMC_INTERNALBANK_NUMBER (   NUMBER)
Value:
(((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \

Definition at line 359 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_MEMORY

#define IS_FMC_MEMORY (   __MEMORY__)
Value:
(((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
((__MEMORY__) == FMC_MEMORY_TYPE_NOR))

Definition at line 50 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_MUX

#define IS_FMC_MUX (   __MUX__)
Value:
(((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \

Definition at line 47 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_NAND_BANK

#define IS_FMC_NAND_BANK (   BANK)    ((BANK) == FMC_NAND_BANK3)

Definition at line 63 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_NAND_MEMORY_WIDTH

#define IS_FMC_NAND_MEMORY_WIDTH (   WIDTH)
Value:
(((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \

Definition at line 68 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_NORSRAM_BANK

#define IS_FMC_NORSRAM_BANK (   BANK)
Value:
(((BANK) == FMC_NORSRAM_BANK1) || \
((BANK) == FMC_NORSRAM_BANK2) || \
((BANK) == FMC_NORSRAM_BANK3) || \
((BANK) == FMC_NORSRAM_BANK4))

Definition at line 42 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_NORSRAM_MEMORY_WIDTH

#define IS_FMC_NORSRAM_MEMORY_WIDTH (   __WIDTH__)
Value:
(((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))

Definition at line 54 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_PAGESIZE

#define IS_FMC_PAGESIZE (   __SIZE__)
Value:
(((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
((__SIZE__) == FMC_PAGE_SIZE_128) || \
((__SIZE__) == FMC_PAGE_SIZE_256) || \
((__SIZE__) == FMC_PAGE_SIZE_512) || \
((__SIZE__) == FMC_PAGE_SIZE_1024))

Definition at line 367 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_READ_BURST

#define IS_FMC_READ_BURST (   __RBURST__)
Value:
(((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))

Definition at line 92 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_READPIPE_DELAY

#define IS_FMC_READPIPE_DELAY (   __DELAY__)
Value:
(((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))

Definition at line 95 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_ROWBITS_NUMBER

#define IS_FMC_ROWBITS_NUMBER (   ROW)
Value:

Definition at line 355 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_SDCLOCK_PERIOD

#define IS_FMC_SDCLOCK_PERIOD (   __PERIOD__)
Value:
(((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))

Definition at line 88 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_SDMEMORY_WIDTH

#define IS_FMC_SDMEMORY_WIDTH (   WIDTH)
Value:
(((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \

Definition at line 81 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_SDRAM_BANK

#define IS_FMC_SDRAM_BANK (   BANK)
Value:
(((BANK) == FMC_SDRAM_BANK1) || \
((BANK) == FMC_SDRAM_BANK2))

Definition at line 347 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_WAIT_FEATURE

#define IS_FMC_WAIT_FEATURE (   FEATURE)
Value:
(((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \

Definition at line 65 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_WAIT_POLARITY

#define IS_FMC_WAIT_POLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))

Definition at line 162 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_WAIT_SIGNAL_ACTIVE

#define IS_FMC_WAIT_SIGNAL_ACTIVE (   __ACTIVE__)
Value:
(((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))

Definition at line 165 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_WAITE_SIGNAL

#define IS_FMC_WAITE_SIGNAL (   __SIGNAL__)
Value:
(((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))

Definition at line 171 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_WRITE_BURST

#define IS_FMC_WRITE_BURST (   __BURST__)
Value:
(((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FMC_WRITE_BURST_ENABLE))

Definition at line 188 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_WRITE_FIFO

#define IS_FMC_WRITE_FIFO (   __FIFO__)
Value:
(((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
((__FIFO__) == FMC_WRITE_FIFO_ENABLE))

Definition at line 373 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_WRITE_OPERATION

#define IS_FMC_WRITE_OPERATION (   __OPERATION__)
Value:
(((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))

Definition at line 168 of file stm32f7xx_ll_fmc.h.

◆ IS_FMC_WRITE_PROTECTION

#define IS_FMC_WRITE_PROTECTION (   __WRITE__)
Value:

Definition at line 85 of file stm32f7xx_ll_fmc.h.

FMC_PAGE_SIZE_128
#define FMC_PAGE_SIZE_128
Definition: stm32f7xx_ll_fmc.h:777
FMC_NAND_ECC_PAGE_SIZE_2048BYTE
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE
Definition: stm32f7xx_ll_fmc.h:879
FMC_DATA_ADDRESS_MUX_ENABLE
#define FMC_DATA_ADDRESS_MUX_ENABLE
Definition: stm32f7xx_ll_fmc.h:676
FMC_SDRAM_CLOCK_DISABLE
#define FMC_SDRAM_CLOCK_DISABLE
Definition: stm32f7xx_ll_fmc.h:964
FMC_EXTENDED_MODE_DISABLE
#define FMC_EXTENDED_MODE_DISABLE
Definition: stm32f7xx_ll_fmc.h:758
FMC_SDRAM_INTERN_BANKS_NUM_2
#define FMC_SDRAM_INTERN_BANKS_NUM_2
Definition: stm32f7xx_ll_fmc.h:936
FMC_PAGE_SIZE_NONE
#define FMC_PAGE_SIZE_NONE
Definition: stm32f7xx_ll_fmc.h:776
FMC_SDRAM_MEM_BUS_WIDTH_8
#define FMC_SDRAM_MEM_BUS_WIDTH_8
Definition: stm32f7xx_ll_fmc.h:926
FMC_SDRAM_COLUMN_BITS_NUM_8
#define FMC_SDRAM_COLUMN_BITS_NUM_8
Definition: stm32f7xx_ll_fmc.h:905
FMC_NORSRAM_MEM_BUS_WIDTH_16
#define FMC_NORSRAM_MEM_BUS_WIDTH_16
Definition: stm32f7xx_ll_fmc.h:695
FMC_CONTINUOUS_CLOCK_SYNC_ONLY
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY
Definition: stm32f7xx_ll_fmc.h:797
FMC_SDRAM_COLUMN_BITS_NUM_11
#define FMC_SDRAM_COLUMN_BITS_NUM_11
Definition: stm32f7xx_ll_fmc.h:908
FMC_PAGE_SIZE_1024
#define FMC_PAGE_SIZE_1024
Definition: stm32f7xx_ll_fmc.h:780
FMC_SDRAM_INTERN_BANKS_NUM_4
#define FMC_SDRAM_INTERN_BANKS_NUM_4
Definition: stm32f7xx_ll_fmc.h:937
FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_WAIT_FEATURE_ENABLE
Definition: stm32f7xx_ll_fmc.h:842
FMC_SDRAM_CMD_AUTOREFRESH_MODE
#define FMC_SDRAM_CMD_AUTOREFRESH_MODE
Definition: stm32f7xx_ll_fmc.h:996
FMC_NAND_ECC_PAGE_SIZE_256BYTE
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE
Definition: stm32f7xx_ll_fmc.h:876
FMC_WAIT_SIGNAL_POLARITY_HIGH
#define FMC_WAIT_SIGNAL_POLARITY_HIGH
Definition: stm32f7xx_ll_fmc.h:723
FMC_SDRAM_ROW_BITS_NUM_12
#define FMC_SDRAM_ROW_BITS_NUM_12
Definition: stm32f7xx_ll_fmc.h:917
FMC_SDRAM_CMD_TARGET_BANK2
#define FMC_SDRAM_CMD_TARGET_BANK2
Definition: stm32f7xx_ll_fmc.h:1007
FMC_WRITE_BURST_ENABLE
#define FMC_WRITE_BURST_ENABLE
Definition: stm32f7xx_ll_fmc.h:789
FMC_NAND_MEM_BUS_WIDTH_8
#define FMC_NAND_MEM_BUS_WIDTH_8
Definition: stm32f7xx_ll_fmc.h:858
FMC_EXTENDED_MODE_ENABLE
#define FMC_EXTENDED_MODE_ENABLE
Definition: stm32f7xx_ll_fmc.h:759
FMC_WRITE_OPERATION_DISABLE
#define FMC_WRITE_OPERATION_DISABLE
Definition: stm32f7xx_ll_fmc.h:740
FMC_SDRAM_RBURST_DISABLE
#define FMC_SDRAM_RBURST_DISABLE
Definition: stm32f7xx_ll_fmc.h:974
FMC_WAIT_TIMING_BEFORE_WS
#define FMC_WAIT_TIMING_BEFORE_WS
Definition: stm32f7xx_ll_fmc.h:731
FMC_NORSRAM_BANK1
#define FMC_NORSRAM_BANK1
Definition: stm32f7xx_ll_fmc.h:664
FMC_NORSRAM_BANK2
#define FMC_NORSRAM_BANK2
Definition: stm32f7xx_ll_fmc.h:665
FMC_WAIT_TIMING_DURING_WS
#define FMC_WAIT_TIMING_DURING_WS
Definition: stm32f7xx_ll_fmc.h:732
FMC_SDRAM_CLOCK_PERIOD_2
#define FMC_SDRAM_CLOCK_PERIOD_2
Definition: stm32f7xx_ll_fmc.h:965
FMC_NAND_ECC_PAGE_SIZE_1024BYTE
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE
Definition: stm32f7xx_ll_fmc.h:878
FMC_SDRAM_CMD_PALL
#define FMC_SDRAM_CMD_PALL
Definition: stm32f7xx_ll_fmc.h:995
FMC_WRITE_BURST_DISABLE
#define FMC_WRITE_BURST_DISABLE
Definition: stm32f7xx_ll_fmc.h:788
FMC_SDRAM_CMD_CLK_ENABLE
#define FMC_SDRAM_CMD_CLK_ENABLE
Definition: stm32f7xx_ll_fmc.h:994
FMC_SDRAM_CMD_POWERDOWN_MODE
#define FMC_SDRAM_CMD_POWERDOWN_MODE
Definition: stm32f7xx_ll_fmc.h:999
FMC_NAND_ECC_PAGE_SIZE_512BYTE
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE
Definition: stm32f7xx_ll_fmc.h:877
FMC_SDRAM_CAS_LATENCY_2
#define FMC_SDRAM_CAS_LATENCY_2
Definition: stm32f7xx_ll_fmc.h:946
FMC_SDRAM_CAS_LATENCY_1
#define FMC_SDRAM_CAS_LATENCY_1
Definition: stm32f7xx_ll_fmc.h:945
FMC_SDRAM_WRITE_PROTECTION_ENABLE
#define FMC_SDRAM_WRITE_PROTECTION_ENABLE
Definition: stm32f7xx_ll_fmc.h:956
FMC_NORSRAM_MEM_BUS_WIDTH_32
#define FMC_NORSRAM_MEM_BUS_WIDTH_32
Definition: stm32f7xx_ll_fmc.h:696
FMC_WRITE_FIFO_DISABLE
#define FMC_WRITE_FIFO_DISABLE
Definition: stm32f7xx_ll_fmc.h:806
FMC_SDRAM_CMD_SELFREFRESH_MODE
#define FMC_SDRAM_CMD_SELFREFRESH_MODE
Definition: stm32f7xx_ll_fmc.h:998
FMC_SDRAM_RPIPE_DELAY_2
#define FMC_SDRAM_RPIPE_DELAY_2
Definition: stm32f7xx_ll_fmc.h:985
FMC_MEMORY_TYPE_NOR
#define FMC_MEMORY_TYPE_NOR
Definition: stm32f7xx_ll_fmc.h:686
FMC_WAIT_SIGNAL_POLARITY_LOW
#define FMC_WAIT_SIGNAL_POLARITY_LOW
Definition: stm32f7xx_ll_fmc.h:722
FMC_WAIT_SIGNAL_ENABLE
#define FMC_WAIT_SIGNAL_ENABLE
Definition: stm32f7xx_ll_fmc.h:750
FMC_SDRAM_CMD_LOAD_MODE
#define FMC_SDRAM_CMD_LOAD_MODE
Definition: stm32f7xx_ll_fmc.h:997
FMC_SDRAM_CAS_LATENCY_3
#define FMC_SDRAM_CAS_LATENCY_3
Definition: stm32f7xx_ll_fmc.h:947
FMC_DATA_ADDRESS_MUX_DISABLE
#define FMC_DATA_ADDRESS_MUX_DISABLE
Definition: stm32f7xx_ll_fmc.h:675
FMC_SDRAM_CMD_TARGET_BANK1
#define FMC_SDRAM_CMD_TARGET_BANK1
Definition: stm32f7xx_ll_fmc.h:1008
FMC_SDRAM_COLUMN_BITS_NUM_9
#define FMC_SDRAM_COLUMN_BITS_NUM_9
Definition: stm32f7xx_ll_fmc.h:906
FMC_NAND_MEM_BUS_WIDTH_16
#define FMC_NAND_MEM_BUS_WIDTH_16
Definition: stm32f7xx_ll_fmc.h:859
FMC_PAGE_SIZE_512
#define FMC_PAGE_SIZE_512
Definition: stm32f7xx_ll_fmc.h:779
FMC_MEMORY_TYPE_SRAM
#define FMC_MEMORY_TYPE_SRAM
Definition: stm32f7xx_ll_fmc.h:684
FMC_PAGE_SIZE_256
#define FMC_PAGE_SIZE_256
Definition: stm32f7xx_ll_fmc.h:778
FMC_SDRAM_ROW_BITS_NUM_11
#define FMC_SDRAM_ROW_BITS_NUM_11
Definition: stm32f7xx_ll_fmc.h:916
FMC_SDRAM_CMD_NORMAL_MODE
#define FMC_SDRAM_CMD_NORMAL_MODE
Definition: stm32f7xx_ll_fmc.h:993
FMC_NORSRAM_MEM_BUS_WIDTH_8
#define FMC_NORSRAM_MEM_BUS_WIDTH_8
Definition: stm32f7xx_ll_fmc.h:694
FMC_ACCESS_MODE_C
#define FMC_ACCESS_MODE_C
Definition: stm32f7xx_ll_fmc.h:817
FMC_SDRAM_COLUMN_BITS_NUM_10
#define FMC_SDRAM_COLUMN_BITS_NUM_10
Definition: stm32f7xx_ll_fmc.h:907
FMC_SDRAM_WRITE_PROTECTION_DISABLE
#define FMC_SDRAM_WRITE_PROTECTION_DISABLE
Definition: stm32f7xx_ll_fmc.h:955
FMC_ACCESS_MODE_A
#define FMC_ACCESS_MODE_A
Definition: stm32f7xx_ll_fmc.h:815
FMC_NAND_ECC_DISABLE
#define FMC_NAND_ECC_DISABLE
Definition: stm32f7xx_ll_fmc.h:867
FMC_SDRAM_BANK1
#define FMC_SDRAM_BANK1
Definition: stm32f7xx_ll_fmc.h:896
FMC_SDRAM_CLOCK_PERIOD_3
#define FMC_SDRAM_CLOCK_PERIOD_3
Definition: stm32f7xx_ll_fmc.h:966
FMC_NORSRAM_BANK4
#define FMC_NORSRAM_BANK4
Definition: stm32f7xx_ll_fmc.h:667
FMC_MEMORY_TYPE_PSRAM
#define FMC_MEMORY_TYPE_PSRAM
Definition: stm32f7xx_ll_fmc.h:685
FMC_SDRAM_BANK2
#define FMC_SDRAM_BANK2
Definition: stm32f7xx_ll_fmc.h:897
FMC_SDRAM_RPIPE_DELAY_1
#define FMC_SDRAM_RPIPE_DELAY_1
Definition: stm32f7xx_ll_fmc.h:984
FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_WAIT_FEATURE_DISABLE
Definition: stm32f7xx_ll_fmc.h:841
FMC_WRITE_FIFO_ENABLE
#define FMC_WRITE_FIFO_ENABLE
Definition: stm32f7xx_ll_fmc.h:807
FMC_WAIT_SIGNAL_DISABLE
#define FMC_WAIT_SIGNAL_DISABLE
Definition: stm32f7xx_ll_fmc.h:749
FMC_SDRAM_RBURST_ENABLE
#define FMC_SDRAM_RBURST_ENABLE
Definition: stm32f7xx_ll_fmc.h:975
FMC_ACCESS_MODE_B
#define FMC_ACCESS_MODE_B
Definition: stm32f7xx_ll_fmc.h:816
FMC_SDRAM_MEM_BUS_WIDTH_16
#define FMC_SDRAM_MEM_BUS_WIDTH_16
Definition: stm32f7xx_ll_fmc.h:927
FMC_NORSRAM_BANK3
#define FMC_NORSRAM_BANK3
Definition: stm32f7xx_ll_fmc.h:666
FMC_ASYNCHRONOUS_WAIT_ENABLE
#define FMC_ASYNCHRONOUS_WAIT_ENABLE
Definition: stm32f7xx_ll_fmc.h:768
FMC_SDRAM_ROW_BITS_NUM_13
#define FMC_SDRAM_ROW_BITS_NUM_13
Definition: stm32f7xx_ll_fmc.h:918
FMC_SDRAM_CMD_TARGET_BANK1_2
#define FMC_SDRAM_CMD_TARGET_BANK1_2
Definition: stm32f7xx_ll_fmc.h:1009
FMC_CONTINUOUS_CLOCK_SYNC_ASYNC
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC
Definition: stm32f7xx_ll_fmc.h:798
FMC_ASYNCHRONOUS_WAIT_DISABLE
#define FMC_ASYNCHRONOUS_WAIT_DISABLE
Definition: stm32f7xx_ll_fmc.h:767
FMC_NAND_ECC_PAGE_SIZE_4096BYTE
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE
Definition: stm32f7xx_ll_fmc.h:880
FMC_NAND_ECC_ENABLE
#define FMC_NAND_ECC_ENABLE
Definition: stm32f7xx_ll_fmc.h:868
FMC_ACCESS_MODE_D
#define FMC_ACCESS_MODE_D
Definition: stm32f7xx_ll_fmc.h:818
FMC_WRITE_OPERATION_ENABLE
#define FMC_WRITE_OPERATION_ENABLE
Definition: stm32f7xx_ll_fmc.h:741
FMC_NAND_ECC_PAGE_SIZE_8192BYTE
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE
Definition: stm32f7xx_ll_fmc.h:881
FMC_SDRAM_MEM_BUS_WIDTH_32
#define FMC_SDRAM_MEM_BUS_WIDTH_32
Definition: stm32f7xx_ll_fmc.h:928
FMC_BURST_ACCESS_MODE_DISABLE
#define FMC_BURST_ACCESS_MODE_DISABLE
Definition: stm32f7xx_ll_fmc.h:713
FMC_BURST_ACCESS_MODE_ENABLE
#define FMC_BURST_ACCESS_MODE_ENABLE
Definition: stm32f7xx_ll_fmc.h:714
FMC_SDRAM_RPIPE_DELAY_0
#define FMC_SDRAM_RPIPE_DELAY_0
Definition: stm32f7xx_ll_fmc.h:983


picovoice_driver
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autogenerated on Fri Apr 1 2022 02:15:08