◆ IS_FMC_ACCESS_MODE
#define IS_FMC_ACCESS_MODE |
( |
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__MODE__ | ) |
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◆ IS_FMC_ASYNWAIT
#define IS_FMC_ASYNWAIT |
( |
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__STATE__ | ) |
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◆ IS_FMC_BURSTMODE
#define IS_FMC_BURSTMODE |
( |
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__STATE__ | ) |
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◆ IS_FMC_CAS_LATENCY
#define IS_FMC_CAS_LATENCY |
( |
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LATENCY | ) |
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◆ IS_FMC_COLUMNBITS_NUMBER
#define IS_FMC_COLUMNBITS_NUMBER |
( |
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COLUMN | ) |
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◆ IS_FMC_COMMAND_MODE
#define IS_FMC_COMMAND_MODE |
( |
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__COMMAND__ | ) |
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◆ IS_FMC_COMMAND_TARGET
#define IS_FMC_COMMAND_TARGET |
( |
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__TARGET__ | ) |
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◆ IS_FMC_CONTINOUS_CLOCK
#define IS_FMC_CONTINOUS_CLOCK |
( |
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CCLOCK | ) |
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◆ IS_FMC_ECC_STATE
#define IS_FMC_ECC_STATE |
( |
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STATE | ) |
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◆ IS_FMC_ECCPAGE_SIZE
#define IS_FMC_ECCPAGE_SIZE |
( |
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SIZE | ) |
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◆ IS_FMC_EXTENDED_MODE
#define IS_FMC_EXTENDED_MODE |
( |
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__MODE__ | ) |
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◆ IS_FMC_INTERNALBANK_NUMBER
#define IS_FMC_INTERNALBANK_NUMBER |
( |
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NUMBER | ) |
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◆ IS_FMC_MEMORY
#define IS_FMC_MEMORY |
( |
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__MEMORY__ | ) |
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◆ IS_FMC_MUX
#define IS_FMC_MUX |
( |
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__MUX__ | ) |
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◆ IS_FMC_NAND_BANK
◆ IS_FMC_NAND_MEMORY_WIDTH
#define IS_FMC_NAND_MEMORY_WIDTH |
( |
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WIDTH | ) |
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◆ IS_FMC_NORSRAM_BANK
#define IS_FMC_NORSRAM_BANK |
( |
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BANK | ) |
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◆ IS_FMC_NORSRAM_MEMORY_WIDTH
#define IS_FMC_NORSRAM_MEMORY_WIDTH |
( |
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__WIDTH__ | ) |
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◆ IS_FMC_PAGESIZE
#define IS_FMC_PAGESIZE |
( |
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__SIZE__ | ) |
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◆ IS_FMC_READ_BURST
#define IS_FMC_READ_BURST |
( |
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__RBURST__ | ) |
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◆ IS_FMC_READPIPE_DELAY
#define IS_FMC_READPIPE_DELAY |
( |
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__DELAY__ | ) |
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◆ IS_FMC_ROWBITS_NUMBER
#define IS_FMC_ROWBITS_NUMBER |
( |
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ROW | ) |
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◆ IS_FMC_SDCLOCK_PERIOD
#define IS_FMC_SDCLOCK_PERIOD |
( |
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__PERIOD__ | ) |
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◆ IS_FMC_SDMEMORY_WIDTH
#define IS_FMC_SDMEMORY_WIDTH |
( |
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WIDTH | ) |
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◆ IS_FMC_SDRAM_BANK
#define IS_FMC_SDRAM_BANK |
( |
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BANK | ) |
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◆ IS_FMC_WAIT_FEATURE
#define IS_FMC_WAIT_FEATURE |
( |
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FEATURE | ) |
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◆ IS_FMC_WAIT_POLARITY
#define IS_FMC_WAIT_POLARITY |
( |
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__POLARITY__ | ) |
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◆ IS_FMC_WAIT_SIGNAL_ACTIVE
#define IS_FMC_WAIT_SIGNAL_ACTIVE |
( |
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__ACTIVE__ | ) |
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◆ IS_FMC_WAITE_SIGNAL
#define IS_FMC_WAITE_SIGNAL |
( |
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__SIGNAL__ | ) |
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◆ IS_FMC_WRITE_BURST
#define IS_FMC_WRITE_BURST |
( |
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__BURST__ | ) |
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◆ IS_FMC_WRITE_FIFO
#define IS_FMC_WRITE_FIFO |
( |
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__FIFO__ | ) |
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◆ IS_FMC_WRITE_OPERATION
#define IS_FMC_WRITE_OPERATION |
( |
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__OPERATION__ | ) |
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◆ IS_FMC_WRITE_PROTECTION
#define IS_FMC_WRITE_PROTECTION |
( |
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__WRITE__ | ) |
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#define FMC_PAGE_SIZE_128
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE
#define FMC_DATA_ADDRESS_MUX_ENABLE
#define FMC_SDRAM_CLOCK_DISABLE
#define FMC_EXTENDED_MODE_DISABLE
#define FMC_SDRAM_INTERN_BANKS_NUM_2
#define FMC_PAGE_SIZE_NONE
#define FMC_SDRAM_MEM_BUS_WIDTH_8
#define FMC_SDRAM_COLUMN_BITS_NUM_8
#define FMC_NORSRAM_MEM_BUS_WIDTH_16
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY
#define FMC_SDRAM_COLUMN_BITS_NUM_11
#define FMC_PAGE_SIZE_1024
#define FMC_SDRAM_INTERN_BANKS_NUM_4
#define FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_SDRAM_CMD_AUTOREFRESH_MODE
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE
#define FMC_WAIT_SIGNAL_POLARITY_HIGH
#define FMC_SDRAM_ROW_BITS_NUM_12
#define FMC_SDRAM_CMD_TARGET_BANK2
#define FMC_WRITE_BURST_ENABLE
#define FMC_NAND_MEM_BUS_WIDTH_8
#define FMC_EXTENDED_MODE_ENABLE
#define FMC_WRITE_OPERATION_DISABLE
#define FMC_SDRAM_RBURST_DISABLE
#define FMC_WAIT_TIMING_BEFORE_WS
#define FMC_NORSRAM_BANK1
#define FMC_NORSRAM_BANK2
#define FMC_WAIT_TIMING_DURING_WS
#define FMC_SDRAM_CLOCK_PERIOD_2
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE
#define FMC_SDRAM_CMD_PALL
#define FMC_WRITE_BURST_DISABLE
#define FMC_SDRAM_CMD_CLK_ENABLE
#define FMC_SDRAM_CMD_POWERDOWN_MODE
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE
#define FMC_SDRAM_CAS_LATENCY_2
#define FMC_SDRAM_CAS_LATENCY_1
#define FMC_SDRAM_WRITE_PROTECTION_ENABLE
#define FMC_NORSRAM_MEM_BUS_WIDTH_32
#define FMC_WRITE_FIFO_DISABLE
#define FMC_SDRAM_CMD_SELFREFRESH_MODE
#define FMC_SDRAM_RPIPE_DELAY_2
#define FMC_MEMORY_TYPE_NOR
#define FMC_WAIT_SIGNAL_POLARITY_LOW
#define FMC_WAIT_SIGNAL_ENABLE
#define FMC_SDRAM_CMD_LOAD_MODE
#define FMC_SDRAM_CAS_LATENCY_3
#define FMC_DATA_ADDRESS_MUX_DISABLE
#define FMC_SDRAM_CMD_TARGET_BANK1
#define FMC_SDRAM_COLUMN_BITS_NUM_9
#define FMC_NAND_MEM_BUS_WIDTH_16
#define FMC_PAGE_SIZE_512
#define FMC_MEMORY_TYPE_SRAM
#define FMC_PAGE_SIZE_256
#define FMC_SDRAM_ROW_BITS_NUM_11
#define FMC_SDRAM_CMD_NORMAL_MODE
#define FMC_NORSRAM_MEM_BUS_WIDTH_8
#define FMC_ACCESS_MODE_C
#define FMC_SDRAM_COLUMN_BITS_NUM_10
#define FMC_SDRAM_WRITE_PROTECTION_DISABLE
#define FMC_ACCESS_MODE_A
#define FMC_NAND_ECC_DISABLE
#define FMC_SDRAM_CLOCK_PERIOD_3
#define FMC_NORSRAM_BANK4
#define FMC_MEMORY_TYPE_PSRAM
#define FMC_SDRAM_RPIPE_DELAY_1
#define FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_WRITE_FIFO_ENABLE
#define FMC_WAIT_SIGNAL_DISABLE
#define FMC_SDRAM_RBURST_ENABLE
#define FMC_ACCESS_MODE_B
#define FMC_SDRAM_MEM_BUS_WIDTH_16
#define FMC_NORSRAM_BANK3
#define FMC_ASYNCHRONOUS_WAIT_ENABLE
#define FMC_SDRAM_ROW_BITS_NUM_13
#define FMC_SDRAM_CMD_TARGET_BANK1_2
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC
#define FMC_ASYNCHRONOUS_WAIT_DISABLE
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE
#define FMC_NAND_ECC_ENABLE
#define FMC_ACCESS_MODE_D
#define FMC_WRITE_OPERATION_ENABLE
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE
#define FMC_SDRAM_MEM_BUS_WIDTH_32
#define FMC_BURST_ACCESS_MODE_DISABLE
#define FMC_BURST_ACCESS_MODE_ENABLE
#define FMC_SDRAM_RPIPE_DELAY_0