Macros
CS43L22_Exported_Constants
Collaboration diagram for CS43L22_Exported_Constants:

Macros

#define AUDIO_FREQUENCY_11K   ((uint32_t)11025)
 
#define AUDIO_FREQUENCY_11K   ((uint32_t)11025)
 
#define AUDIO_FREQUENCY_11K   ((uint32_t)11025)
 
#define AUDIO_FREQUENCY_16K   ((uint32_t)16000)
 
#define AUDIO_FREQUENCY_16K   ((uint32_t)16000)
 
#define AUDIO_FREQUENCY_16K   ((uint32_t)16000)
 
#define AUDIO_FREQUENCY_192K   ((uint32_t)192000)
 
#define AUDIO_FREQUENCY_192K   ((uint32_t)192000)
 
#define AUDIO_FREQUENCY_192K   ((uint32_t)192000)
 
#define AUDIO_FREQUENCY_22K   ((uint32_t)22050)
 
#define AUDIO_FREQUENCY_22K   ((uint32_t)22050)
 
#define AUDIO_FREQUENCY_22K   ((uint32_t)22050)
 
#define AUDIO_FREQUENCY_32K   ((uint32_t)32000)
 
#define AUDIO_FREQUENCY_32K   ((uint32_t)32000)
 
#define AUDIO_FREQUENCY_32K   ((uint32_t)32000)
 
#define AUDIO_FREQUENCY_44K   ((uint32_t)44100)
 
#define AUDIO_FREQUENCY_44K   ((uint32_t)44100)
 
#define AUDIO_FREQUENCY_44K   ((uint32_t)44100)
 
#define AUDIO_FREQUENCY_48K   ((uint32_t)48000)
 
#define AUDIO_FREQUENCY_48K   ((uint32_t)48000)
 
#define AUDIO_FREQUENCY_48K   ((uint32_t)48000)
 
#define AUDIO_FREQUENCY_8K   ((uint32_t)8000)
 
#define AUDIO_FREQUENCY_8K   ((uint32_t)8000)
 
#define AUDIO_FREQUENCY_8K   ((uint32_t)8000)
 
#define AUDIO_FREQUENCY_96K   ((uint32_t)96000)
 
#define AUDIO_FREQUENCY_96K   ((uint32_t)96000)
 
#define AUDIO_FREQUENCY_96K   ((uint32_t)96000)
 
#define AUDIO_MUTE_OFF   0
 
#define AUDIO_MUTE_OFF   0
 
#define AUDIO_MUTE_OFF   0
 
#define AUDIO_MUTE_ON   1
 
#define AUDIO_MUTE_ON   1
 
#define AUDIO_MUTE_ON   1
 
#define AUDIO_PAUSE   0
 
#define AUDIO_PAUSE   0
 
#define AUDIO_PAUSE   0
 
#define AUDIO_RESUME   1
 
#define AUDIO_RESUME   1
 
#define AUDIO_RESUME   1
 
#define CODEC_PDWN_HW   1
 
#define CODEC_PDWN_HW   1
 
#define CODEC_PDWN_HW   1
 
#define CODEC_PDWN_SW   2
 
#define CODEC_PDWN_SW   2
 
#define CODEC_PDWN_SW   2
 
#define CS43L22_CHIPID_ADDR   0x01
 Chip ID Register: Chip I.D. and Revision Register Read only register Default value: 0x01 [7:3] CHIPID[4:0]: I.D. code for the CS43L22. Default value: 11100b [2:0] REVID[2:0]: CS43L22 revision level. Default value: 000 - Rev A0 001 - Rev A1 010 - Rev B0 011 - Rev B1. More...
 
#define CS43L22_CHIPID_ADDR   0x01
 Chip ID Register: Chip I.D. and Revision Register Read only register Default value: 0x01 [7:3] CHIPID[4:0]: I.D. code for the CS43L22. Default value: 11100b [2:0] REVID[2:0]: CS43L22 revision level. Default value: 000 - Rev A0 001 - Rev A1 010 - Rev B0 011 - Rev B1. More...
 
#define CS43L22_CHIPID_ADDR   0x01
 Chip ID Register: Chip I.D. and Revision Register Read only register Default value: 0x01 [7:3] CHIPID[4:0]: I.D. code for the CS43L22. Default value: 11100b [2:0] REVID[2:0]: CS43L22 revision level. Default value: 000 - Rev A0 001 - Rev A1 010 - Rev B0 011 - Rev B1. More...
 
#define CS43L22_ID   0xE0
 CS43L22 ID
More...
 
#define CS43L22_ID   0xE0
 CS43L22 ID
More...
 
#define CS43L22_ID   0xE0
 CS43L22 ID
More...
 
#define CS43L22_ID_MASK   0xF8
 
#define CS43L22_ID_MASK   0xF8
 
#define CS43L22_ID_MASK   0xF8
 
#define CS43L22_REG_ANALOG_ZC_SR_SETT   0x0A
 
#define CS43L22_REG_ANALOG_ZC_SR_SETT   0x0A
 
#define CS43L22_REG_ANALOG_ZC_SR_SETT   0x0A
 
#define CS43L22_REG_BATT_COMPENSATION   0x2F
 
#define CS43L22_REG_BATT_COMPENSATION   0x2F
 
#define CS43L22_REG_BATT_COMPENSATION   0x2F
 
#define CS43L22_REG_BEEP_FREQ_ON_TIME   0x1C
 
#define CS43L22_REG_BEEP_FREQ_ON_TIME   0x1C
 
#define CS43L22_REG_BEEP_FREQ_ON_TIME   0x1C
 
#define CS43L22_REG_BEEP_TONE_CFG   0x1E
 
#define CS43L22_REG_BEEP_TONE_CFG   0x1E
 
#define CS43L22_REG_BEEP_TONE_CFG   0x1E
 
#define CS43L22_REG_BEEP_VOL_OFF_TIME   0x1D
 
#define CS43L22_REG_BEEP_VOL_OFF_TIME   0x1D
 
#define CS43L22_REG_BEEP_VOL_OFF_TIME   0x1D
 
#define CS43L22_REG_CH_MIXER_SWAP   0x26
 
#define CS43L22_REG_CH_MIXER_SWAP   0x26
 
#define CS43L22_REG_CH_MIXER_SWAP   0x26
 
#define CS43L22_REG_CHARGE_PUMP_FREQ   0x34
 
#define CS43L22_REG_CHARGE_PUMP_FREQ   0x34
 
#define CS43L22_REG_CHARGE_PUMP_FREQ   0x34
 
#define CS43L22_REG_CLOCKING_CTL   0x05
 
#define CS43L22_REG_CLOCKING_CTL   0x05
 
#define CS43L22_REG_CLOCKING_CTL   0x05
 
#define CS43L22_REG_HEADPHONE_A_VOL   0x22
 
#define CS43L22_REG_HEADPHONE_A_VOL   0x22
 
#define CS43L22_REG_HEADPHONE_A_VOL   0x22
 
#define CS43L22_REG_HEADPHONE_B_VOL   0x23
 
#define CS43L22_REG_HEADPHONE_B_VOL   0x23
 
#define CS43L22_REG_HEADPHONE_B_VOL   0x23
 
#define CS43L22_REG_ID   0x01
 
#define CS43L22_REG_ID   0x01
 
#define CS43L22_REG_ID   0x01
 
#define CS43L22_REG_INTERFACE_CTL1   0x06
 
#define CS43L22_REG_INTERFACE_CTL1   0x06
 
#define CS43L22_REG_INTERFACE_CTL1   0x06
 
#define CS43L22_REG_INTERFACE_CTL2   0x07
 
#define CS43L22_REG_INTERFACE_CTL2   0x07
 
#define CS43L22_REG_INTERFACE_CTL2   0x07
 
#define CS43L22_REG_LIMIT_ATTACK_RATE   0x29
 
#define CS43L22_REG_LIMIT_ATTACK_RATE   0x29
 
#define CS43L22_REG_LIMIT_ATTACK_RATE   0x29
 
#define CS43L22_REG_LIMIT_CTL1   0x27
 
#define CS43L22_REG_LIMIT_CTL1   0x27
 
#define CS43L22_REG_LIMIT_CTL1   0x27
 
#define CS43L22_REG_LIMIT_CTL2   0x28
 
#define CS43L22_REG_LIMIT_CTL2   0x28
 
#define CS43L22_REG_LIMIT_CTL2   0x28
 
#define CS43L22_REG_MASTER_A_VOL   0x20
 
#define CS43L22_REG_MASTER_A_VOL   0x20
 
#define CS43L22_REG_MASTER_A_VOL   0x20
 
#define CS43L22_REG_MASTER_B_VOL   0x21
 
#define CS43L22_REG_MASTER_B_VOL   0x21
 
#define CS43L22_REG_MASTER_B_VOL   0x21
 
#define CS43L22_REG_MISC_CTL   0x0E
 
#define CS43L22_REG_MISC_CTL   0x0E
 
#define CS43L22_REG_MISC_CTL   0x0E
 
#define CS43L22_REG_OVF_CLK_STATUS   0x2E
 
#define CS43L22_REG_OVF_CLK_STATUS   0x2E
 
#define CS43L22_REG_OVF_CLK_STATUS   0x2E
 
#define CS43L22_REG_PASSTHR_A_SELECT   0x08
 
#define CS43L22_REG_PASSTHR_A_SELECT   0x08
 
#define CS43L22_REG_PASSTHR_A_SELECT   0x08
 
#define CS43L22_REG_PASSTHR_A_VOL   0x14
 
#define CS43L22_REG_PASSTHR_A_VOL   0x14
 
#define CS43L22_REG_PASSTHR_A_VOL   0x14
 
#define CS43L22_REG_PASSTHR_B_SELECT   0x09
 
#define CS43L22_REG_PASSTHR_B_SELECT   0x09
 
#define CS43L22_REG_PASSTHR_B_SELECT   0x09
 
#define CS43L22_REG_PASSTHR_B_VOL   0x15
 
#define CS43L22_REG_PASSTHR_B_VOL   0x15
 
#define CS43L22_REG_PASSTHR_B_VOL   0x15
 
#define CS43L22_REG_PASSTHR_GANG_CTL   0x0C
 
#define CS43L22_REG_PASSTHR_GANG_CTL   0x0C
 
#define CS43L22_REG_PASSTHR_GANG_CTL   0x0C
 
#define CS43L22_REG_PCMA_VOL   0x1A
 
#define CS43L22_REG_PCMA_VOL   0x1A
 
#define CS43L22_REG_PCMA_VOL   0x1A
 
#define CS43L22_REG_PCMB_VOL   0x1B
 
#define CS43L22_REG_PCMB_VOL   0x1B
 
#define CS43L22_REG_PCMB_VOL   0x1B
 
#define CS43L22_REG_PLAYBACK_CTL1   0x0D
 
#define CS43L22_REG_PLAYBACK_CTL1   0x0D
 
#define CS43L22_REG_PLAYBACK_CTL1   0x0D
 
#define CS43L22_REG_PLAYBACK_CTL2   0x0F
 
#define CS43L22_REG_PLAYBACK_CTL2   0x0F
 
#define CS43L22_REG_PLAYBACK_CTL2   0x0F
 
#define CS43L22_REG_POWER_CTL1   0x02
 
#define CS43L22_REG_POWER_CTL1   0x02
 
#define CS43L22_REG_POWER_CTL1   0x02
 
#define CS43L22_REG_POWER_CTL2   0x04
 
#define CS43L22_REG_POWER_CTL2   0x04
 
#define CS43L22_REG_POWER_CTL2   0x04
 
#define CS43L22_REG_SPEAKER_A_VOL   0x24
 
#define CS43L22_REG_SPEAKER_A_VOL   0x24
 
#define CS43L22_REG_SPEAKER_A_VOL   0x24
 
#define CS43L22_REG_SPEAKER_B_VOL   0x25
 
#define CS43L22_REG_SPEAKER_B_VOL   0x25
 
#define CS43L22_REG_SPEAKER_B_VOL   0x25
 
#define CS43L22_REG_SPEAKER_STATUS   0x31
 
#define CS43L22_REG_SPEAKER_STATUS   0x31
 
#define CS43L22_REG_SPEAKER_STATUS   0x31
 
#define CS43L22_REG_TEMPMONITOR_CTL   0x32
 
#define CS43L22_REG_TEMPMONITOR_CTL   0x32
 
#define CS43L22_REG_TEMPMONITOR_CTL   0x32
 
#define CS43L22_REG_THERMAL_FOLDBACK   0x33
 
#define CS43L22_REG_THERMAL_FOLDBACK   0x33
 
#define CS43L22_REG_THERMAL_FOLDBACK   0x33
 
#define CS43L22_REG_TONE_CTL   0x1F
 
#define CS43L22_REG_TONE_CTL   0x1F
 
#define CS43L22_REG_TONE_CTL   0x1F
 
#define CS43L22_REG_VP_BATTERY_LEVEL   0x30
 
#define CS43L22_REG_VP_BATTERY_LEVEL   0x30
 
#define CS43L22_REG_VP_BATTERY_LEVEL   0x30
 
#define DEFAULT_VOLMAX   0xFF
 
#define DEFAULT_VOLMAX   0xFF
 
#define DEFAULT_VOLMAX   0xFF
 
#define DEFAULT_VOLMIN   0x00
 
#define DEFAULT_VOLMIN   0x00
 
#define DEFAULT_VOLMIN   0x00
 
#define DEFAULT_VOLSTEP   0x04
 
#define DEFAULT_VOLSTEP   0x04
 
#define DEFAULT_VOLSTEP   0x04
 
#define OUTPUT_DEVICE_AUTO   4
 
#define OUTPUT_DEVICE_AUTO   4
 
#define OUTPUT_DEVICE_AUTO   4
 
#define OUTPUT_DEVICE_BOTH   3
 
#define OUTPUT_DEVICE_BOTH   3
 
#define OUTPUT_DEVICE_BOTH   3
 
#define OUTPUT_DEVICE_HEADPHONE   2
 
#define OUTPUT_DEVICE_HEADPHONE   2
 
#define OUTPUT_DEVICE_HEADPHONE   2
 
#define OUTPUT_DEVICE_SPEAKER   1
 
#define OUTPUT_DEVICE_SPEAKER   1
 
#define OUTPUT_DEVICE_SPEAKER   1
 

Detailed Description

Macro Definition Documentation

◆ AUDIO_FREQUENCY_11K [1/3]

#define AUDIO_FREQUENCY_11K   ((uint32_t)11025)

◆ AUDIO_FREQUENCY_11K [2/3]

#define AUDIO_FREQUENCY_11K   ((uint32_t)11025)

◆ AUDIO_FREQUENCY_11K [3/3]

#define AUDIO_FREQUENCY_11K   ((uint32_t)11025)

◆ AUDIO_FREQUENCY_16K [1/3]

#define AUDIO_FREQUENCY_16K   ((uint32_t)16000)

◆ AUDIO_FREQUENCY_16K [2/3]

#define AUDIO_FREQUENCY_16K   ((uint32_t)16000)

◆ AUDIO_FREQUENCY_16K [3/3]

#define AUDIO_FREQUENCY_16K   ((uint32_t)16000)

◆ AUDIO_FREQUENCY_192K [1/3]

#define AUDIO_FREQUENCY_192K   ((uint32_t)192000)

◆ AUDIO_FREQUENCY_192K [2/3]

#define AUDIO_FREQUENCY_192K   ((uint32_t)192000)

◆ AUDIO_FREQUENCY_192K [3/3]

#define AUDIO_FREQUENCY_192K   ((uint32_t)192000)

◆ AUDIO_FREQUENCY_22K [1/3]

#define AUDIO_FREQUENCY_22K   ((uint32_t)22050)

◆ AUDIO_FREQUENCY_22K [2/3]

#define AUDIO_FREQUENCY_22K   ((uint32_t)22050)

◆ AUDIO_FREQUENCY_22K [3/3]

#define AUDIO_FREQUENCY_22K   ((uint32_t)22050)

◆ AUDIO_FREQUENCY_32K [1/3]

#define AUDIO_FREQUENCY_32K   ((uint32_t)32000)

◆ AUDIO_FREQUENCY_32K [2/3]

#define AUDIO_FREQUENCY_32K   ((uint32_t)32000)

◆ AUDIO_FREQUENCY_32K [3/3]

#define AUDIO_FREQUENCY_32K   ((uint32_t)32000)

◆ AUDIO_FREQUENCY_44K [1/3]

#define AUDIO_FREQUENCY_44K   ((uint32_t)44100)

◆ AUDIO_FREQUENCY_44K [2/3]

#define AUDIO_FREQUENCY_44K   ((uint32_t)44100)

◆ AUDIO_FREQUENCY_44K [3/3]

#define AUDIO_FREQUENCY_44K   ((uint32_t)44100)

◆ AUDIO_FREQUENCY_48K [1/3]

#define AUDIO_FREQUENCY_48K   ((uint32_t)48000)

◆ AUDIO_FREQUENCY_48K [2/3]

#define AUDIO_FREQUENCY_48K   ((uint32_t)48000)

◆ AUDIO_FREQUENCY_48K [3/3]

#define AUDIO_FREQUENCY_48K   ((uint32_t)48000)

◆ AUDIO_FREQUENCY_8K [1/3]

#define AUDIO_FREQUENCY_8K   ((uint32_t)8000)

◆ AUDIO_FREQUENCY_8K [2/3]

#define AUDIO_FREQUENCY_8K   ((uint32_t)8000)

◆ AUDIO_FREQUENCY_8K [3/3]

#define AUDIO_FREQUENCY_8K   ((uint32_t)8000)

◆ AUDIO_FREQUENCY_96K [1/3]

#define AUDIO_FREQUENCY_96K   ((uint32_t)96000)

◆ AUDIO_FREQUENCY_96K [2/3]

#define AUDIO_FREQUENCY_96K   ((uint32_t)96000)

◆ AUDIO_FREQUENCY_96K [3/3]

#define AUDIO_FREQUENCY_96K   ((uint32_t)96000)

◆ AUDIO_MUTE_OFF [1/3]

#define AUDIO_MUTE_OFF   0

◆ AUDIO_MUTE_OFF [2/3]

#define AUDIO_MUTE_OFF   0

◆ AUDIO_MUTE_OFF [3/3]

#define AUDIO_MUTE_OFF   0

◆ AUDIO_MUTE_ON [1/3]

#define AUDIO_MUTE_ON   1

◆ AUDIO_MUTE_ON [2/3]

#define AUDIO_MUTE_ON   1

◆ AUDIO_MUTE_ON [3/3]

#define AUDIO_MUTE_ON   1

◆ AUDIO_PAUSE [1/3]

#define AUDIO_PAUSE   0

◆ AUDIO_PAUSE [2/3]

#define AUDIO_PAUSE   0

◆ AUDIO_PAUSE [3/3]

#define AUDIO_PAUSE   0

◆ AUDIO_RESUME [1/3]

#define AUDIO_RESUME   1

◆ AUDIO_RESUME [2/3]

#define AUDIO_RESUME   1

◆ AUDIO_RESUME [3/3]

#define AUDIO_RESUME   1

◆ CODEC_PDWN_HW [1/3]

#define CODEC_PDWN_HW   1

◆ CODEC_PDWN_HW [2/3]

#define CODEC_PDWN_HW   1

◆ CODEC_PDWN_HW [3/3]

#define CODEC_PDWN_HW   1

◆ CODEC_PDWN_SW [1/3]

#define CODEC_PDWN_SW   2

◆ CODEC_PDWN_SW [2/3]

#define CODEC_PDWN_SW   2

◆ CODEC_PDWN_SW [3/3]

#define CODEC_PDWN_SW   2

◆ CS43L22_CHIPID_ADDR [1/3]

#define CS43L22_CHIPID_ADDR   0x01

Chip ID Register: Chip I.D. and Revision Register Read only register Default value: 0x01 [7:3] CHIPID[4:0]: I.D. code for the CS43L22. Default value: 11100b [2:0] REVID[2:0]: CS43L22 revision level. Default value: 000 - Rev A0 001 - Rev A1 010 - Rev B0 011 - Rev B1.

Definition at line 164 of file stm32f469/stm32f469i-disco/Drivers/BSP/Components/cs43l22/cs43l22.h.

◆ CS43L22_CHIPID_ADDR [2/3]

#define CS43L22_CHIPID_ADDR   0x01

Chip ID Register: Chip I.D. and Revision Register Read only register Default value: 0x01 [7:3] CHIPID[4:0]: I.D. code for the CS43L22. Default value: 11100b [2:0] REVID[2:0]: CS43L22 revision level. Default value: 000 - Rev A0 001 - Rev A1 010 - Rev B0 011 - Rev B1.

Definition at line 164 of file stm32f407/stm32f407g-disc1/Drivers/BSP/Components/cs43l22/cs43l22.h.

◆ CS43L22_CHIPID_ADDR [3/3]

#define CS43L22_CHIPID_ADDR   0x01

Chip ID Register: Chip I.D. and Revision Register Read only register Default value: 0x01 [7:3] CHIPID[4:0]: I.D. code for the CS43L22. Default value: 11100b [2:0] REVID[2:0]: CS43L22 revision level. Default value: 000 - Rev A0 001 - Rev A1 010 - Rev B0 011 - Rev B1.

Definition at line 164 of file stm32f411/stm32f411e-disco/Drivers/BSP/Components/cs43l22/cs43l22.h.

◆ CS43L22_ID [1/3]

#define CS43L22_ID   0xE0

◆ CS43L22_ID [2/3]

#define CS43L22_ID   0xE0

◆ CS43L22_ID [3/3]

#define CS43L22_ID   0xE0

◆ CS43L22_ID_MASK [1/3]

#define CS43L22_ID_MASK   0xF8

◆ CS43L22_ID_MASK [2/3]

#define CS43L22_ID_MASK   0xF8

◆ CS43L22_ID_MASK [3/3]

#define CS43L22_ID_MASK   0xF8

◆ CS43L22_REG_ANALOG_ZC_SR_SETT [1/3]

#define CS43L22_REG_ANALOG_ZC_SR_SETT   0x0A

◆ CS43L22_REG_ANALOG_ZC_SR_SETT [2/3]

#define CS43L22_REG_ANALOG_ZC_SR_SETT   0x0A

◆ CS43L22_REG_ANALOG_ZC_SR_SETT [3/3]

#define CS43L22_REG_ANALOG_ZC_SR_SETT   0x0A

◆ CS43L22_REG_BATT_COMPENSATION [1/3]

#define CS43L22_REG_BATT_COMPENSATION   0x2F

◆ CS43L22_REG_BATT_COMPENSATION [2/3]

#define CS43L22_REG_BATT_COMPENSATION   0x2F

◆ CS43L22_REG_BATT_COMPENSATION [3/3]

#define CS43L22_REG_BATT_COMPENSATION   0x2F

◆ CS43L22_REG_BEEP_FREQ_ON_TIME [1/3]

#define CS43L22_REG_BEEP_FREQ_ON_TIME   0x1C

◆ CS43L22_REG_BEEP_FREQ_ON_TIME [2/3]

#define CS43L22_REG_BEEP_FREQ_ON_TIME   0x1C

◆ CS43L22_REG_BEEP_FREQ_ON_TIME [3/3]

#define CS43L22_REG_BEEP_FREQ_ON_TIME   0x1C

◆ CS43L22_REG_BEEP_TONE_CFG [1/3]

#define CS43L22_REG_BEEP_TONE_CFG   0x1E

◆ CS43L22_REG_BEEP_TONE_CFG [2/3]

#define CS43L22_REG_BEEP_TONE_CFG   0x1E

◆ CS43L22_REG_BEEP_TONE_CFG [3/3]

#define CS43L22_REG_BEEP_TONE_CFG   0x1E

◆ CS43L22_REG_BEEP_VOL_OFF_TIME [1/3]

#define CS43L22_REG_BEEP_VOL_OFF_TIME   0x1D

◆ CS43L22_REG_BEEP_VOL_OFF_TIME [2/3]

#define CS43L22_REG_BEEP_VOL_OFF_TIME   0x1D

◆ CS43L22_REG_BEEP_VOL_OFF_TIME [3/3]

#define CS43L22_REG_BEEP_VOL_OFF_TIME   0x1D

◆ CS43L22_REG_CH_MIXER_SWAP [1/3]

#define CS43L22_REG_CH_MIXER_SWAP   0x26

◆ CS43L22_REG_CH_MIXER_SWAP [2/3]

#define CS43L22_REG_CH_MIXER_SWAP   0x26

◆ CS43L22_REG_CH_MIXER_SWAP [3/3]

#define CS43L22_REG_CH_MIXER_SWAP   0x26

◆ CS43L22_REG_CHARGE_PUMP_FREQ [1/3]

#define CS43L22_REG_CHARGE_PUMP_FREQ   0x34

◆ CS43L22_REG_CHARGE_PUMP_FREQ [2/3]

#define CS43L22_REG_CHARGE_PUMP_FREQ   0x34

◆ CS43L22_REG_CHARGE_PUMP_FREQ [3/3]

#define CS43L22_REG_CHARGE_PUMP_FREQ   0x34

◆ CS43L22_REG_CLOCKING_CTL [1/3]

#define CS43L22_REG_CLOCKING_CTL   0x05

◆ CS43L22_REG_CLOCKING_CTL [2/3]

#define CS43L22_REG_CLOCKING_CTL   0x05

◆ CS43L22_REG_CLOCKING_CTL [3/3]

#define CS43L22_REG_CLOCKING_CTL   0x05

◆ CS43L22_REG_HEADPHONE_A_VOL [1/3]

#define CS43L22_REG_HEADPHONE_A_VOL   0x22

◆ CS43L22_REG_HEADPHONE_A_VOL [2/3]

#define CS43L22_REG_HEADPHONE_A_VOL   0x22

◆ CS43L22_REG_HEADPHONE_A_VOL [3/3]

#define CS43L22_REG_HEADPHONE_A_VOL   0x22

◆ CS43L22_REG_HEADPHONE_B_VOL [1/3]

#define CS43L22_REG_HEADPHONE_B_VOL   0x23

◆ CS43L22_REG_HEADPHONE_B_VOL [2/3]

#define CS43L22_REG_HEADPHONE_B_VOL   0x23

◆ CS43L22_REG_HEADPHONE_B_VOL [3/3]

#define CS43L22_REG_HEADPHONE_B_VOL   0x23

◆ CS43L22_REG_ID [1/3]

#define CS43L22_REG_ID   0x01

CS43l22 Registers

Definition at line 104 of file stm32f469/stm32f469i-disco/Drivers/BSP/Components/cs43l22/cs43l22.h.

◆ CS43L22_REG_ID [2/3]

#define CS43L22_REG_ID   0x01

CS43l22 Registers

Definition at line 104 of file stm32f411/stm32f411e-disco/Drivers/BSP/Components/cs43l22/cs43l22.h.

◆ CS43L22_REG_ID [3/3]

#define CS43L22_REG_ID   0x01

CS43l22 Registers

Definition at line 104 of file stm32f407/stm32f407g-disc1/Drivers/BSP/Components/cs43l22/cs43l22.h.

◆ CS43L22_REG_INTERFACE_CTL1 [1/3]

#define CS43L22_REG_INTERFACE_CTL1   0x06

◆ CS43L22_REG_INTERFACE_CTL1 [2/3]

#define CS43L22_REG_INTERFACE_CTL1   0x06

◆ CS43L22_REG_INTERFACE_CTL1 [3/3]

#define CS43L22_REG_INTERFACE_CTL1   0x06

◆ CS43L22_REG_INTERFACE_CTL2 [1/3]

#define CS43L22_REG_INTERFACE_CTL2   0x07

◆ CS43L22_REG_INTERFACE_CTL2 [2/3]

#define CS43L22_REG_INTERFACE_CTL2   0x07

◆ CS43L22_REG_INTERFACE_CTL2 [3/3]

#define CS43L22_REG_INTERFACE_CTL2   0x07

◆ CS43L22_REG_LIMIT_ATTACK_RATE [1/3]

#define CS43L22_REG_LIMIT_ATTACK_RATE   0x29

◆ CS43L22_REG_LIMIT_ATTACK_RATE [2/3]

#define CS43L22_REG_LIMIT_ATTACK_RATE   0x29

◆ CS43L22_REG_LIMIT_ATTACK_RATE [3/3]

#define CS43L22_REG_LIMIT_ATTACK_RATE   0x29

◆ CS43L22_REG_LIMIT_CTL1 [1/3]

#define CS43L22_REG_LIMIT_CTL1   0x27

◆ CS43L22_REG_LIMIT_CTL1 [2/3]

#define CS43L22_REG_LIMIT_CTL1   0x27

◆ CS43L22_REG_LIMIT_CTL1 [3/3]

#define CS43L22_REG_LIMIT_CTL1   0x27

◆ CS43L22_REG_LIMIT_CTL2 [1/3]

#define CS43L22_REG_LIMIT_CTL2   0x28

◆ CS43L22_REG_LIMIT_CTL2 [2/3]

#define CS43L22_REG_LIMIT_CTL2   0x28

◆ CS43L22_REG_LIMIT_CTL2 [3/3]

#define CS43L22_REG_LIMIT_CTL2   0x28

◆ CS43L22_REG_MASTER_A_VOL [1/3]

#define CS43L22_REG_MASTER_A_VOL   0x20

◆ CS43L22_REG_MASTER_A_VOL [2/3]

#define CS43L22_REG_MASTER_A_VOL   0x20

◆ CS43L22_REG_MASTER_A_VOL [3/3]

#define CS43L22_REG_MASTER_A_VOL   0x20

◆ CS43L22_REG_MASTER_B_VOL [1/3]

#define CS43L22_REG_MASTER_B_VOL   0x21

◆ CS43L22_REG_MASTER_B_VOL [2/3]

#define CS43L22_REG_MASTER_B_VOL   0x21

◆ CS43L22_REG_MASTER_B_VOL [3/3]

#define CS43L22_REG_MASTER_B_VOL   0x21

◆ CS43L22_REG_MISC_CTL [1/3]

#define CS43L22_REG_MISC_CTL   0x0E

◆ CS43L22_REG_MISC_CTL [2/3]

#define CS43L22_REG_MISC_CTL   0x0E

◆ CS43L22_REG_MISC_CTL [3/3]

#define CS43L22_REG_MISC_CTL   0x0E

◆ CS43L22_REG_OVF_CLK_STATUS [1/3]

#define CS43L22_REG_OVF_CLK_STATUS   0x2E

◆ CS43L22_REG_OVF_CLK_STATUS [2/3]

#define CS43L22_REG_OVF_CLK_STATUS   0x2E

◆ CS43L22_REG_OVF_CLK_STATUS [3/3]

#define CS43L22_REG_OVF_CLK_STATUS   0x2E

◆ CS43L22_REG_PASSTHR_A_SELECT [1/3]

#define CS43L22_REG_PASSTHR_A_SELECT   0x08

◆ CS43L22_REG_PASSTHR_A_SELECT [2/3]

#define CS43L22_REG_PASSTHR_A_SELECT   0x08

◆ CS43L22_REG_PASSTHR_A_SELECT [3/3]

#define CS43L22_REG_PASSTHR_A_SELECT   0x08

◆ CS43L22_REG_PASSTHR_A_VOL [1/3]

#define CS43L22_REG_PASSTHR_A_VOL   0x14

◆ CS43L22_REG_PASSTHR_A_VOL [2/3]

#define CS43L22_REG_PASSTHR_A_VOL   0x14

◆ CS43L22_REG_PASSTHR_A_VOL [3/3]

#define CS43L22_REG_PASSTHR_A_VOL   0x14

◆ CS43L22_REG_PASSTHR_B_SELECT [1/3]

#define CS43L22_REG_PASSTHR_B_SELECT   0x09

◆ CS43L22_REG_PASSTHR_B_SELECT [2/3]

#define CS43L22_REG_PASSTHR_B_SELECT   0x09

◆ CS43L22_REG_PASSTHR_B_SELECT [3/3]

#define CS43L22_REG_PASSTHR_B_SELECT   0x09

◆ CS43L22_REG_PASSTHR_B_VOL [1/3]

#define CS43L22_REG_PASSTHR_B_VOL   0x15

◆ CS43L22_REG_PASSTHR_B_VOL [2/3]

#define CS43L22_REG_PASSTHR_B_VOL   0x15

◆ CS43L22_REG_PASSTHR_B_VOL [3/3]

#define CS43L22_REG_PASSTHR_B_VOL   0x15

◆ CS43L22_REG_PASSTHR_GANG_CTL [1/3]

#define CS43L22_REG_PASSTHR_GANG_CTL   0x0C

◆ CS43L22_REG_PASSTHR_GANG_CTL [2/3]

#define CS43L22_REG_PASSTHR_GANG_CTL   0x0C

◆ CS43L22_REG_PASSTHR_GANG_CTL [3/3]

#define CS43L22_REG_PASSTHR_GANG_CTL   0x0C

◆ CS43L22_REG_PCMA_VOL [1/3]

#define CS43L22_REG_PCMA_VOL   0x1A

◆ CS43L22_REG_PCMA_VOL [2/3]

#define CS43L22_REG_PCMA_VOL   0x1A

◆ CS43L22_REG_PCMA_VOL [3/3]

#define CS43L22_REG_PCMA_VOL   0x1A

◆ CS43L22_REG_PCMB_VOL [1/3]

#define CS43L22_REG_PCMB_VOL   0x1B

◆ CS43L22_REG_PCMB_VOL [2/3]

#define CS43L22_REG_PCMB_VOL   0x1B

◆ CS43L22_REG_PCMB_VOL [3/3]

#define CS43L22_REG_PCMB_VOL   0x1B

◆ CS43L22_REG_PLAYBACK_CTL1 [1/3]

#define CS43L22_REG_PLAYBACK_CTL1   0x0D

◆ CS43L22_REG_PLAYBACK_CTL1 [2/3]

#define CS43L22_REG_PLAYBACK_CTL1   0x0D

◆ CS43L22_REG_PLAYBACK_CTL1 [3/3]

#define CS43L22_REG_PLAYBACK_CTL1   0x0D

◆ CS43L22_REG_PLAYBACK_CTL2 [1/3]

#define CS43L22_REG_PLAYBACK_CTL2   0x0F

◆ CS43L22_REG_PLAYBACK_CTL2 [2/3]

#define CS43L22_REG_PLAYBACK_CTL2   0x0F

◆ CS43L22_REG_PLAYBACK_CTL2 [3/3]

#define CS43L22_REG_PLAYBACK_CTL2   0x0F

◆ CS43L22_REG_POWER_CTL1 [1/3]

#define CS43L22_REG_POWER_CTL1   0x02

◆ CS43L22_REG_POWER_CTL1 [2/3]

#define CS43L22_REG_POWER_CTL1   0x02

◆ CS43L22_REG_POWER_CTL1 [3/3]

#define CS43L22_REG_POWER_CTL1   0x02

◆ CS43L22_REG_POWER_CTL2 [1/3]

#define CS43L22_REG_POWER_CTL2   0x04

◆ CS43L22_REG_POWER_CTL2 [2/3]

#define CS43L22_REG_POWER_CTL2   0x04

◆ CS43L22_REG_POWER_CTL2 [3/3]

#define CS43L22_REG_POWER_CTL2   0x04

◆ CS43L22_REG_SPEAKER_A_VOL [1/3]

#define CS43L22_REG_SPEAKER_A_VOL   0x24

◆ CS43L22_REG_SPEAKER_A_VOL [2/3]

#define CS43L22_REG_SPEAKER_A_VOL   0x24

◆ CS43L22_REG_SPEAKER_A_VOL [3/3]

#define CS43L22_REG_SPEAKER_A_VOL   0x24

◆ CS43L22_REG_SPEAKER_B_VOL [1/3]

#define CS43L22_REG_SPEAKER_B_VOL   0x25

◆ CS43L22_REG_SPEAKER_B_VOL [2/3]

#define CS43L22_REG_SPEAKER_B_VOL   0x25

◆ CS43L22_REG_SPEAKER_B_VOL [3/3]

#define CS43L22_REG_SPEAKER_B_VOL   0x25

◆ CS43L22_REG_SPEAKER_STATUS [1/3]

#define CS43L22_REG_SPEAKER_STATUS   0x31

◆ CS43L22_REG_SPEAKER_STATUS [2/3]

#define CS43L22_REG_SPEAKER_STATUS   0x31

◆ CS43L22_REG_SPEAKER_STATUS [3/3]

#define CS43L22_REG_SPEAKER_STATUS   0x31

◆ CS43L22_REG_TEMPMONITOR_CTL [1/3]

#define CS43L22_REG_TEMPMONITOR_CTL   0x32

◆ CS43L22_REG_TEMPMONITOR_CTL [2/3]

#define CS43L22_REG_TEMPMONITOR_CTL   0x32

◆ CS43L22_REG_TEMPMONITOR_CTL [3/3]

#define CS43L22_REG_TEMPMONITOR_CTL   0x32

◆ CS43L22_REG_THERMAL_FOLDBACK [1/3]

#define CS43L22_REG_THERMAL_FOLDBACK   0x33

◆ CS43L22_REG_THERMAL_FOLDBACK [2/3]

#define CS43L22_REG_THERMAL_FOLDBACK   0x33

◆ CS43L22_REG_THERMAL_FOLDBACK [3/3]

#define CS43L22_REG_THERMAL_FOLDBACK   0x33

◆ CS43L22_REG_TONE_CTL [1/3]

#define CS43L22_REG_TONE_CTL   0x1F

◆ CS43L22_REG_TONE_CTL [2/3]

#define CS43L22_REG_TONE_CTL   0x1F

◆ CS43L22_REG_TONE_CTL [3/3]

#define CS43L22_REG_TONE_CTL   0x1F

◆ CS43L22_REG_VP_BATTERY_LEVEL [1/3]

#define CS43L22_REG_VP_BATTERY_LEVEL   0x30

◆ CS43L22_REG_VP_BATTERY_LEVEL [2/3]

#define CS43L22_REG_VP_BATTERY_LEVEL   0x30

◆ CS43L22_REG_VP_BATTERY_LEVEL [3/3]

#define CS43L22_REG_VP_BATTERY_LEVEL   0x30

◆ DEFAULT_VOLMAX [1/3]

#define DEFAULT_VOLMAX   0xFF

◆ DEFAULT_VOLMAX [2/3]

#define DEFAULT_VOLMAX   0xFF

◆ DEFAULT_VOLMAX [3/3]

#define DEFAULT_VOLMAX   0xFF

◆ DEFAULT_VOLMIN [1/3]

#define DEFAULT_VOLMIN   0x00

◆ DEFAULT_VOLMIN [2/3]

#define DEFAULT_VOLMIN   0x00

◆ DEFAULT_VOLMIN [3/3]

#define DEFAULT_VOLMIN   0x00

◆ DEFAULT_VOLSTEP [1/3]

#define DEFAULT_VOLSTEP   0x04

◆ DEFAULT_VOLSTEP [2/3]

#define DEFAULT_VOLSTEP   0x04

◆ DEFAULT_VOLSTEP [3/3]

#define DEFAULT_VOLSTEP   0x04

◆ OUTPUT_DEVICE_AUTO [1/3]

#define OUTPUT_DEVICE_AUTO   4

◆ OUTPUT_DEVICE_AUTO [2/3]

#define OUTPUT_DEVICE_AUTO   4

◆ OUTPUT_DEVICE_AUTO [3/3]

#define OUTPUT_DEVICE_AUTO   4

◆ OUTPUT_DEVICE_BOTH [1/3]

#define OUTPUT_DEVICE_BOTH   3

◆ OUTPUT_DEVICE_BOTH [2/3]

#define OUTPUT_DEVICE_BOTH   3

◆ OUTPUT_DEVICE_BOTH [3/3]

#define OUTPUT_DEVICE_BOTH   3

◆ OUTPUT_DEVICE_HEADPHONE [1/3]

#define OUTPUT_DEVICE_HEADPHONE   2

◆ OUTPUT_DEVICE_HEADPHONE [2/3]

#define OUTPUT_DEVICE_HEADPHONE   2

◆ OUTPUT_DEVICE_HEADPHONE [3/3]

#define OUTPUT_DEVICE_HEADPHONE   2

◆ OUTPUT_DEVICE_SPEAKER [1/3]

#define OUTPUT_DEVICE_SPEAKER   1

◆ OUTPUT_DEVICE_SPEAKER [2/3]

#define OUTPUT_DEVICE_SPEAKER   1

◆ OUTPUT_DEVICE_SPEAKER [3/3]

#define OUTPUT_DEVICE_SPEAKER   1


picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:05