Macros
#define	SYSCTL_IRC_FREQ (12000000)

Typedefs
typedef enum CHIP_SYSCTL_CLKOUTSRC	CHIP_SYSCTL_CLKOUTSRC_T

typedef enum CHIP_SYSCTL_CLOCK	CHIP_SYSCTL_CLOCK_T

typedef enum CHIP_SYSCTL_MAINCLKSRC	CHIP_SYSCTL_MAINCLKSRC_T

typedef enum CHIP_SYSCTL_PLLCLKSRC	CHIP_SYSCTL_PLLCLKSRC_T

typedef enum CHIP_WDTLFO_OSC	CHIP_WDTLFO_OSC_T

Enumerations
enum	CHIP_SYSCTL_CLKOUTSRC { SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_MAINOSC, SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_LFOSC = SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_MAINSYSCLK }

enum	CHIP_SYSCTL_CLOCK { SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM, SYSCTL_CLOCK_FLASHREG, SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0, SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0, SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0, SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_RESERVED14, SYSCTL_CLOCK_WDT, SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_PINT, SYSCTL_CLOCK_RESERVED20, SYSCTL_CLOCK_RESERVED21, SYSCTL_CLOCK_RESERVED22, SYSCTL_CLOCK_P0INT, SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT, SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_RESERVED25, SYSCTL_CLOCK_RESERVED26, SYSCTL_CLOCK_RESERVED27 }

enum	CHIP_SYSCTL_MAINCLKSRC { SYSCTL_MAINCLKSRC_IRC = 0, SYSCTL_MAINCLKSRC_PLLIN, SYSCTL_MAINCLKSRC_LFOSC, SYSCTL_MAINCLKSRC_WDTOSC = SYSCTL_MAINCLKSRC_LFOSC, SYSCTL_MAINCLKSRC_PLLOUT }

enum	CHIP_SYSCTL_PLLCLKSRC { SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_MAINOSC, SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RESERVED2 }

enum	CHIP_WDTLFO_OSC { WDTLFO_OSC_ILLEGAL, WDTLFO_OSC_0_60, WDTLFO_OSC_1_05, WDTLFO_OSC_1_40, WDTLFO_OSC_1_75, WDTLFO_OSC_2_10, WDTLFO_OSC_2_40, WDTLFO_OSC_2_70, WDTLFO_OSC_3_00, WDTLFO_OSC_3_25, WDTLFO_OSC_3_50, WDTLFO_OSC_3_75, WDTLFO_OSC_4_00, WDTLFO_OSC_4_20, WDTLFO_OSC_4_40, WDTLFO_OSC_4_60 }

Functions
STATIC INLINE void	Chip_Clock_DisablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
	Disable a system or peripheral clock. More...

STATIC INLINE void	Chip_Clock_EnablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
	Enable a system or peripheral clock. More...

STATIC INLINE uint32_t	Chip_Clock_GetIntOscRate (void)
	Returns the internal oscillator (IRC) clock rate. More...

uint32_t	Chip_Clock_GetMainClockRate (void)
	Return main clock rate. More...

STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T	Chip_Clock_GetMainClockSource (void)
	Returns the main clock source. More...

STATIC INLINE uint32_t	Chip_Clock_GetMainOscRate (void)
	Returns the main oscillator clock rate. More...

STATIC INLINE uint32_t	Chip_Clock_GetSSP0ClockDiv (void)
	Return SSP0 divider. More...

uint32_t	Chip_Clock_GetSystemClockRate (void)
	Return system clock rate. More...

uint32_t	Chip_Clock_GetSystemPLLInClockRate (void)
	Return System PLL input clock rate. More...

uint32_t	Chip_Clock_GetSystemPLLOutClockRate (void)
	Return System PLL output clock rate. More...

STATIC INLINE uint32_t	Chip_Clock_GetUARTClockDiv (void)
	Return UART divider. More...

uint32_t	Chip_Clock_GetWDTOSCRate (void)
	Return estimated watchdog oscillator rate. More...

STATIC INLINE bool	Chip_Clock_IsSystemPLLLocked (void)
	Read System PLL lock status. More...

void	Chip_Clock_SetCLKOUTSource (CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
	Set CLKOUT clock source and divider. More...

void	Chip_Clock_SetMainClockSource (CHIP_SYSCTL_MAINCLKSRC_T src)
	Set main system clock source. More...

void	Chip_Clock_SetPLLBypass (bool bypass, bool highfr)
	Bypass System Oscillator and set oscillator frequency range. More...

STATIC INLINE void	Chip_Clock_SetSSP0ClockDiv (uint32_t div)
	Set SSP0 divider. More...

STATIC INLINE void	Chip_Clock_SetSysClockDiv (uint32_t div)
	Set system clock divider. More...

void	Chip_Clock_SetSystemPLLSource (CHIP_SYSCTL_PLLCLKSRC_T src)
	Set System PLL clock source. More...

STATIC INLINE void	Chip_Clock_SetUARTClockDiv (uint32_t div)
	Set UART divider clock. More...

STATIC INLINE void	Chip_Clock_SetupSystemPLL (uint8_t msel, uint8_t psel)
	Set System PLL divider values. More...

STATIC INLINE void	Chip_Clock_SetWDTOSC (CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
	Setup Watchdog oscillator rate and divider. More...

Detailed Description

Macro Definition Documentation

◆ SYSCTL_IRC_FREQ

#define SYSCTL_IRC_FREQ (12000000)

Internal oscillator frequency

Definition at line 45 of file clock_11xx.h.

Typedef Documentation

◆ CHIP_SYSCTL_CLKOUTSRC_T

typedef enum CHIP_SYSCTL_CLKOUTSRC CHIP_SYSCTL_CLKOUTSRC_T

Clock sources for CLKOUT

◆ CHIP_SYSCTL_CLOCK_T

typedef enum CHIP_SYSCTL_CLOCK CHIP_SYSCTL_CLOCK_T

System and peripheral clocks

◆ CHIP_SYSCTL_MAINCLKSRC_T

typedef enum CHIP_SYSCTL_MAINCLKSRC CHIP_SYSCTL_MAINCLKSRC_T

Clock sources for main system clock

◆ CHIP_SYSCTL_PLLCLKSRC_T

typedef enum CHIP_SYSCTL_PLLCLKSRC CHIP_SYSCTL_PLLCLKSRC_T

Clock sources for system and USB PLLs

◆ CHIP_WDTLFO_OSC_T

typedef enum CHIP_WDTLFO_OSC CHIP_WDTLFO_OSC_T

Watchdog and low frequency oscillator frequencies plus or minus 40%

Enumeration Type Documentation

◆ CHIP_SYSCTL_CLKOUTSRC

enum CHIP_SYSCTL_CLKOUTSRC

Clock sources for CLKOUT

Enumerator
SYSCTL_CLKOUTSRC_IRC	Internal oscillator for CLKOUT
SYSCTL_CLKOUTSRC_MAINOSC	Main oscillator for CLKOUT
SYSCTL_CLKOUTSRC_WDTOSC	Watchdog oscillator for CLKOUT
SYSCTL_CLKOUTSRC_LFOSC	LF oscillator rate (LPC11A/Exx only) for CLKOUT
SYSCTL_CLKOUTSRC_MAINSYSCLK	Main system clock for CLKOUT

Definition at line 430 of file clock_11xx.h.

◆ CHIP_SYSCTL_CLOCK

enum CHIP_SYSCTL_CLOCK

System and peripheral clocks

Enumerator
SYSCTL_CLOCK_SYS	0: System clock
SYSCTL_CLOCK_ROM	1: ROM clock
SYSCTL_CLOCK_RAM	2: RAM clock
SYSCTL_CLOCK_FLASHREG	3: FLASH register interface clock
SYSCTL_CLOCK_FLASHARRAY	4: FLASH array access clock
SYSCTL_CLOCK_I2C	5: I2C clock, not on LPC110x
SYSCTL_CLOCK_GPIO	6: GPIO clock
SYSCTL_CLOCK_CT16B0	7: 16-bit Counter/timer 0 clock
SYSCTL_CLOCK_CT16B1	8: 16-bit Counter/timer 1 clock
SYSCTL_CLOCK_CT32B0	9: 32-bit Counter/timer 0 clock
SYSCTL_CLOCK_CT32B1	10: 32-bit Counter/timer 1 clock
SYSCTL_CLOCK_SSP0	11: SSP0 clock
SYSCTL_CLOCK_UART0	12: UART0 clock
SYSCTL_CLOCK_ADC	13: ADC clock
SYSCTL_CLOCK_RESERVED14	14: Reserved
SYSCTL_CLOCK_WDT	15: Watchdog timer clock
SYSCTL_CLOCK_IOCON	16: IOCON block clock
SYSCTL_CLOCK_RESERVED17	17: Reserved
SYSCTL_CLOCK_SSP1	18: SSP1 clock, LPC11A/C/E/Uxx//1125 only
SYSCTL_CLOCK_PINT	19: GPIO Pin int register interface clock, LPC11A/E/Uxx only
SYSCTL_CLOCK_RESERVED20	20: Reserved
SYSCTL_CLOCK_RESERVED21	21: Reserved
SYSCTL_CLOCK_RESERVED22	22: Reserved
SYSCTL_CLOCK_P0INT	23: GPIO GROUP1 interrupt register clock, LPC11Axx only
SYSCTL_CLOCK_GROUP0INT	23: GPIO GROUP0 interrupt register interface clock, LPC11E/Uxx only
SYSCTL_CLOCK_P1INT	24: GPIO GROUP1 interrupt register clock, LPC11Axx only
SYSCTL_CLOCK_GROUP1INT	24: GPIO GROUP1 interrupt register interface clock, LPC11E/Uxx only
SYSCTL_CLOCK_RESERVED25	25: Reserved
SYSCTL_CLOCK_RESERVED26	26: Reserved
SYSCTL_CLOCK_RESERVED27	27: Reserved

Definition at line 228 of file clock_11xx.h.

◆ CHIP_SYSCTL_MAINCLKSRC

enum CHIP_SYSCTL_MAINCLKSRC

Clock sources for main system clock

Enumerator
SYSCTL_MAINCLKSRC_IRC	Internal oscillator
SYSCTL_MAINCLKSRC_PLLIN	System PLL input
SYSCTL_MAINCLKSRC_LFOSC	LF oscillator rate (11Axx only)
SYSCTL_MAINCLKSRC_WDTOSC	Watchdog oscillator rate
SYSCTL_MAINCLKSRC_PLLOUT	System PLL output

Definition at line 187 of file clock_11xx.h.

◆ CHIP_SYSCTL_PLLCLKSRC

enum CHIP_SYSCTL_PLLCLKSRC

Clock sources for system and USB PLLs

Enumerator
SYSCTL_PLLCLKSRC_IRC	Internal oscillator in
SYSCTL_PLLCLKSRC_MAINOSC	Crystal (main) oscillator in
SYSCTL_PLLCLKSRC_RESERVED1	Reserved
SYSCTL_PLLCLKSRC_RESERVED2	Reserved

Definition at line 71 of file clock_11xx.h.

◆ CHIP_WDTLFO_OSC

enum CHIP_WDTLFO_OSC

Watchdog and low frequency oscillator frequencies plus or minus 40%

Enumerator
WDTLFO_OSC_ILLEGAL
WDTLFO_OSC_0_60	0.6 MHz watchdog/LFO rate
WDTLFO_OSC_1_05	1.05 MHz watchdog/LFO rate
WDTLFO_OSC_1_40	1.4 MHz watchdog/LFO rate
WDTLFO_OSC_1_75	1.75 MHz watchdog/LFO rate
WDTLFO_OSC_2_10	2.1 MHz watchdog/LFO rate
WDTLFO_OSC_2_40	2.4 MHz watchdog/LFO rate
WDTLFO_OSC_2_70	2.7 MHz watchdog/LFO rate
WDTLFO_OSC_3_00	3.0 MHz watchdog/LFO rate
WDTLFO_OSC_3_25	3.25 MHz watchdog/LFO rate
WDTLFO_OSC_3_50	3.5 MHz watchdog/LFO rate
WDTLFO_OSC_3_75	3.75 MHz watchdog/LFO rate
WDTLFO_OSC_4_00	4.0 MHz watchdog/LFO rate
WDTLFO_OSC_4_20	4.2 MHz watchdog/LFO rate
WDTLFO_OSC_4_40	4.4 MHz watchdog/LFO rate
WDTLFO_OSC_4_60	4.6 MHz watchdog/LFO rate

Definition at line 138 of file clock_11xx.h.

Function Documentation

◆ Chip_Clock_DisablePeriphClock()

STATIC INLINE void Chip_Clock_DisablePeriphClock ( CHIP_SYSCTL_CLOCK_T clk )

Disable a system or peripheral clock.

Parameters

clk	: Clock to disable

Returns: Nothing

Definition at line 305 of file clock_11xx.h.

◆ Chip_Clock_EnablePeriphClock()

STATIC INLINE void Chip_Clock_EnablePeriphClock ( CHIP_SYSCTL_CLOCK_T clk )

Enable a system or peripheral clock.

Parameters

clk	: Clock to enable

Returns: Nothing

Definition at line 295 of file clock_11xx.h.

◆ Chip_Clock_GetIntOscRate()

STATIC INLINE uint32_t Chip_Clock_GetIntOscRate ( void )

Returns the internal oscillator (IRC) clock rate.

Returns: internal oscillator (IRC) clock rate

Definition at line 465 of file clock_11xx.h.

◆ Chip_Clock_GetMainClockRate()

uint32_t Chip_Clock_GetMainClockRate ( void )

Return main clock rate.

Returns: main clock rate

Definition at line 248 of file clock_11xx.c.

◆ Chip_Clock_GetMainClockSource()

STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource ( void )

Returns the main clock source.

Returns: Which clock is used for the core clock source?

Definition at line 208 of file clock_11xx.h.

◆ Chip_Clock_GetMainOscRate()

STATIC INLINE uint32_t Chip_Clock_GetMainOscRate ( void )

Returns the main oscillator clock rate.

Returns: main oscillator clock rate

Definition at line 456 of file clock_11xx.h.

◆ Chip_Clock_GetSSP0ClockDiv()

STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv ( void )

Return SSP0 divider.

Returns: divider for SSP0 clock

Note: A value of 0 means the clock is disabled.

Definition at line 327 of file clock_11xx.h.

◆ Chip_Clock_GetSystemClockRate()

uint32_t Chip_Clock_GetSystemClockRate ( void )

Return system clock rate.

Returns: system clock rate

Definition at line 281 of file clock_11xx.c.

◆ Chip_Clock_GetSystemPLLInClockRate()

uint32_t Chip_Clock_GetSystemPLLInClockRate ( void )

Return System PLL input clock rate.

Returns: System PLL input clock rate

Definition at line 183 of file clock_11xx.c.

◆ Chip_Clock_GetSystemPLLOutClockRate()

uint32_t Chip_Clock_GetSystemPLLOutClockRate ( void )

Return System PLL output clock rate.

Returns: System PLL output clock rate

Definition at line 210 of file clock_11xx.c.

◆ Chip_Clock_GetUARTClockDiv()

STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv ( void )

Return UART divider.

Returns: divider for UART clock

Note: A value of 0 means the clock is disabled.

Definition at line 349 of file clock_11xx.h.

◆ Chip_Clock_GetWDTOSCRate()

uint32_t Chip_Clock_GetWDTOSCRate ( void )

Return estimated watchdog oscillator rate.

Returns: Estimated watchdog oscillator rate

Note: This rate is accurate to plus or minus 40%.

Definition at line 168 of file clock_11xx.c.

◆ Chip_Clock_IsSystemPLLLocked()

STATIC INLINE bool Chip_Clock_IsSystemPLLLocked ( void )

Read System PLL lock status.

Returns: true of the PLL is locked. false if not locked

Definition at line 63 of file clock_11xx.h.

◆ Chip_Clock_SetCLKOUTSource()

void Chip_Clock_SetCLKOUTSource	(	CHIP_SYSCTL_CLKOUTSRC_T	src,
		uint32_t	div
	)

Set CLKOUT clock source and divider.

Parameters

src	: Clock source for CLKOUT
div	: divider for CLKOUT clock

Returns: Nothing

Note: Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock rate is the clock source divided by the divider. This function will also toggle the clock source update register to update the clock source.

Definition at line 157 of file clock_11xx.c.

◆ Chip_Clock_SetMainClockSource()

void Chip_Clock_SetMainClockSource ( CHIP_SYSCTL_MAINCLKSRC_T src )

Set main system clock source.

Parameters

src	: Clock source for main system

Returns: Nothing

Note: This function will also toggle the clock source update register to update the clock source.

Definition at line 124 of file clock_11xx.c.

◆ Chip_Clock_SetPLLBypass()

void Chip_Clock_SetPLLBypass	(	bool	bypass,
		bool	highfr
	)

Bypass System Oscillator and set oscillator frequency range.

Parameters

bypass	: Flag to bypass oscillator
highfr	: Flag to set oscillator range from 15-25 MHz

Returns: Nothing

Note: Sets the PLL input to bypass the oscillator. This would be used if an external clock that is not an oscillator is attached to the XTALIN pin.

Definition at line 98 of file clock_11xx.c.

◆ Chip_Clock_SetSSP0ClockDiv()

STATIC INLINE void Chip_Clock_SetSSP0ClockDiv ( uint32_t div )

Set SSP0 divider.

Parameters

div	: divider for SSP0 clock

Returns: Nothing

Note: Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock rate is the main system clock divided by this value.

Definition at line 317 of file clock_11xx.h.

◆ Chip_Clock_SetSysClockDiv()

STATIC INLINE void Chip_Clock_SetSysClockDiv ( uint32_t div )

Set system clock divider.

Parameters

div	: divider for system clock

Returns: Nothing

Note: Use 0 to disable, or a divider value of 1 to 255. The system clock rate is the main system clock divided by this value.

Definition at line 220 of file clock_11xx.h.

◆ Chip_Clock_SetSystemPLLSource()

void Chip_Clock_SetSystemPLLSource ( CHIP_SYSCTL_PLLCLKSRC_T src )

Set System PLL clock source.

Parameters

src	: Clock source for system PLL

Returns: Nothing

Note: This function will also toggle the clock source update register to update the clock source.

Definition at line 90 of file clock_11xx.c.

◆ Chip_Clock_SetUARTClockDiv()

STATIC INLINE void Chip_Clock_SetUARTClockDiv ( uint32_t div )

Set UART divider clock.

Parameters

div	: divider for UART clock

Returns: Nothing

Note: Use 0 to disable, or a divider value of 1 to 255. The UART clock rate is the main system clock divided by this value.

Definition at line 339 of file clock_11xx.h.

◆ Chip_Clock_SetupSystemPLL()

STATIC INLINE void Chip_Clock_SetupSystemPLL	(	uint8_t	msel,
		uint8_t	psel
	)

Set System PLL divider values.

Parameters

msel	: PLL feedback divider value. M = msel + 1.
psel	: PLL post divider value. P = (1<<psel).

Returns: Nothing

Note: See the user manual for how to setup the PLL.

Definition at line 54 of file clock_11xx.h.

◆ Chip_Clock_SetWDTOSC()

STATIC INLINE void Chip_Clock_SetWDTOSC	(	CHIP_WDTLFO_OSC_T	wdtclk,
		uint8_t	div
	)

Setup Watchdog oscillator rate and divider.

Parameters

wdtclk	: Selected watchdog clock rate
div	: Watchdog divider value, even value between 2 and 64

Returns: Nothing

Note: Watchdog rate = selected rate divided by divider rate

Definition at line 164 of file clock_11xx.h.

Macros

Typedefs

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ SYSCTL_IRC_FREQ

Typedef Documentation

◆ CHIP_SYSCTL_CLKOUTSRC_T

◆ CHIP_SYSCTL_CLOCK_T

◆ CHIP_SYSCTL_MAINCLKSRC_T

◆ CHIP_SYSCTL_PLLCLKSRC_T

◆ CHIP_WDTLFO_OSC_T

Enumeration Type Documentation

◆ CHIP_SYSCTL_CLKOUTSRC

◆ CHIP_SYSCTL_CLOCK

◆ CHIP_SYSCTL_MAINCLKSRC

◆ CHIP_SYSCTL_PLLCLKSRC

◆ CHIP_WDTLFO_OSC

Function Documentation

◆ Chip_Clock_DisablePeriphClock()

◆ Chip_Clock_EnablePeriphClock()

◆ Chip_Clock_GetIntOscRate()

◆ Chip_Clock_GetMainClockRate()

◆ Chip_Clock_GetMainClockSource()

◆ Chip_Clock_GetMainOscRate()

◆ Chip_Clock_GetSSP0ClockDiv()

◆ Chip_Clock_GetSystemClockRate()

◆ Chip_Clock_GetSystemPLLInClockRate()

◆ Chip_Clock_GetSystemPLLOutClockRate()

◆ Chip_Clock_GetUARTClockDiv()

◆ Chip_Clock_GetWDTOSCRate()

◆ Chip_Clock_IsSystemPLLLocked()

◆ Chip_Clock_SetCLKOUTSource()

◆ Chip_Clock_SetMainClockSource()

◆ Chip_Clock_SetPLLBypass()

◆ Chip_Clock_SetSSP0ClockDiv()

◆ Chip_Clock_SetSysClockDiv()

◆ Chip_Clock_SetSystemPLLSource()

◆ Chip_Clock_SetUARTClockDiv()

◆ Chip_Clock_SetupSystemPLL()

◆ Chip_Clock_SetWDTOSC()