29 #ifndef __STM32F4xx_RCC_H 30 #define __STM32F4xx_RCC_H 65 #define RCC_HSE_OFF ((uint8_t)0x00) 66 #define RCC_HSE_ON ((uint8_t)0x01) 67 #define RCC_HSE_Bypass ((uint8_t)0x05) 68 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 69 ((HSE) == RCC_HSE_Bypass)) 77 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) 78 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) 79 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \ 80 ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) 88 #define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) 89 #define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) 90 #define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) 91 #define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) 92 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ 93 ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ 94 ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ 95 ((VALUE) == RCC_PLLSAIDivR_Div16)) 103 #define RCC_PLLSource_HSI ((uint32_t)0x00000000) 104 #define RCC_PLLSource_HSE ((uint32_t)0x00400000) 105 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ 106 ((SOURCE) == RCC_PLLSource_HSE)) 107 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) 108 #define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 109 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 110 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) 111 #if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 112 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 115 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 116 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 117 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63) 118 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 119 #if defined(STM32F446xx) 120 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 121 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63) 123 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) 124 #if defined(STM32F446xx) || defined(STM32F469_479xx) 125 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) 127 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) 128 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) 130 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 131 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) 140 #if defined(STM32F446xx) 141 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 142 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 143 #define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002) 144 #define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003) 145 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 146 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 147 ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \ 148 ((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) 150 #define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK 153 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 154 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 155 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 156 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 157 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 158 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 159 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 168 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 169 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 170 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 171 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 172 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 173 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 174 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 175 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 176 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 177 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 178 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 179 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 180 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 181 ((HCLK) == RCC_SYSCLK_Div512)) 189 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 190 #define RCC_HCLK_Div2 ((uint32_t)0x00001000) 191 #define RCC_HCLK_Div4 ((uint32_t)0x00001400) 192 #define RCC_HCLK_Div8 ((uint32_t)0x00001800) 193 #define RCC_HCLK_Div16 ((uint32_t)0x00001C00) 194 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 195 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 196 ((PCLK) == RCC_HCLK_Div16)) 204 #define RCC_IT_LSIRDY ((uint8_t)0x01) 205 #define RCC_IT_LSERDY ((uint8_t)0x02) 206 #define RCC_IT_HSIRDY ((uint8_t)0x04) 207 #define RCC_IT_HSERDY ((uint8_t)0x08) 208 #define RCC_IT_PLLRDY ((uint8_t)0x10) 209 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20) 210 #define RCC_IT_PLLSAIRDY ((uint8_t)0x40) 211 #define RCC_IT_CSS ((uint8_t)0x80) 213 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) 214 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 215 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 216 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ 217 ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) 218 #define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) 227 #define RCC_LSE_OFF ((uint8_t)0x00) 228 #define RCC_LSE_ON ((uint8_t)0x01) 229 #define RCC_LSE_Bypass ((uint8_t)0x04) 230 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 231 ((LSE) == RCC_LSE_Bypass)) 239 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 240 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 241 #define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) 242 #define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) 243 #define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) 244 #define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) 245 #define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) 246 #define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) 247 #define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) 248 #define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) 249 #define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) 250 #define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) 251 #define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) 252 #define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) 253 #define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) 254 #define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) 255 #define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) 256 #define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) 257 #define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) 258 #define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) 259 #define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) 260 #define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) 261 #define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) 262 #define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) 263 #define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) 264 #define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) 265 #define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) 266 #define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) 267 #define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) 268 #define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) 269 #define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) 270 #define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) 271 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 272 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 273 ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ 274 ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ 275 ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ 276 ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ 277 ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ 278 ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ 279 ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ 280 ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ 281 ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ 282 ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ 283 ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ 284 ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ 285 ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ 286 ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ 287 ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ 288 ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ 289 ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ 290 ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ 291 ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ 292 ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ 293 ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ 294 ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ 295 ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ 296 ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ 297 ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ 298 ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ 299 ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ 300 ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ 301 ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ 302 ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) 307 #if defined(STM32F410xx) 311 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) 312 #define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) 313 #define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) 314 #define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) 316 #define IS_RCC_LPTIM1_SOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ 317 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) 325 #define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000) 326 #define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) 327 #define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) 334 #if defined(STM32F446xx) 338 #define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00) 339 #define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) 340 #define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) 341 #define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1) 343 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \ 344 ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE)) 352 #define RCC_I2SBus_APB1 ((uint8_t)0x00) 353 #define RCC_I2SBus_APB2 ((uint8_t)0x01) 354 #define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2)) 362 #define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00) 363 #define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) 364 #define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) 365 #define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1) 367 #define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \ 368 ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE)) 376 #define RCC_SAIInstance_SAI1 ((uint8_t)0x00) 377 #define RCC_SAIInstance_SAI2 ((uint8_t)0x01) 378 #define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2)) 384 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 388 #define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) 389 #define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) 391 #define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) 399 #define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) 400 #define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) 401 #define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) 403 #define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ 404 ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ 405 ((SOURCE) == RCC_SAIACLKSource_Ext)) 413 #define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) 414 #define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) 415 #define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) 417 #define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ 418 ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ 419 ((SOURCE) == RCC_SAIBCLKSource_Ext)) 428 #define RCC_TIMPrescDesactivated ((uint8_t)0x00) 429 #define RCC_TIMPrescActivated ((uint8_t)0x01) 431 #define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) 436 #if defined(STM32F469_479xx) 440 #define RCC_DSICLKSource_PHY ((uint8_t)0x00) 441 #define RCC_DSICLKSource_PLLR ((uint8_t)0x01) 442 #define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \ 443 ((CLKSOURCE) == RCC_DSICLKSource_PLLR)) 449 #if defined(STM32F446xx) || defined(STM32F469_479xx) 453 #define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00) 454 #define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01) 455 #define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \ 456 ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK)) 465 #define RCC_48MHZCLKSource_PLL ((uint8_t)0x00) 466 #define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01) 467 #define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \ 468 ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI)) 474 #if defined(STM32F446xx) 478 #define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00) 479 #define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01) 480 #define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \ 481 ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP)) 489 #define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00) 490 #define RCC_CECCLKSource_LSE ((uint8_t)0x01) 491 #define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \ 492 ((CLKSOURCE) == RCC_CECCLKSource_LSE)) 500 #define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001) 501 #define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002) 502 #define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004) 503 #define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008) 504 #define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010) 505 #define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020) 506 #define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040) 508 #define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00)) 515 #if defined(STM32F410xx) || defined(STM32F4446xx) 519 #define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00) 520 #define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) 521 #define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) 523 #define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \ 524 ((SOURCE) == RCC_FMPI2C1CLKSource_HSI)) 533 #define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) 534 #define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) 535 #define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) 536 #define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) 537 #define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) 538 #define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) 539 #define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) 540 #define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) 541 #define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) 542 #define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) 543 #define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) 544 #define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) 545 #define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) 546 #define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) 547 #define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) 548 #define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) 549 #define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) 550 #define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) 551 #define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) 552 #define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) 553 #define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) 554 #define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) 555 #define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) 556 #define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) 557 #define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) 558 #define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) 559 #define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) 560 #if defined(STM32F410xx) 561 #define RCC_AHB1Periph_RNG ((uint32_t)0x80000000) 563 #define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00)) 564 #define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00)) 565 #define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00)) 574 #define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) 575 #define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) 576 #define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) 577 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 578 #define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) 580 #define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) 581 #define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) 589 #if defined(STM32F40_41xxx) 590 #define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) 591 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) 594 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) 595 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) 596 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) 599 #if defined(STM32F446xx) || defined(STM32F469_479xx) 600 #define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) 601 #define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) 602 #define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) 612 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 613 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 614 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 615 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 616 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) 617 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 618 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) 619 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) 620 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) 621 #if defined(STM32F410xx) 622 #define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200) 624 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 625 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 626 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 627 #if defined(STM32F446xx) 628 #define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000) 630 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) 631 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) 632 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) 633 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 634 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 635 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 636 #define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) 637 #if defined(STM32F410xx) || defined(STM32F446xx) 638 #define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000) 640 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 641 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) 642 #if defined(STM32F446xx) 643 #define RCC_APB1Periph_CEC ((uint32_t)0x08000000) 645 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 646 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 647 #define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) 648 #define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) 649 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00)) 657 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) 658 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) 659 #define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) 660 #define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) 661 #define RCC_APB2Periph_ADC ((uint32_t)0x00000100) 662 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) 663 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) 664 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) 665 #define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) 666 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 667 #define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) 668 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) 669 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) 670 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) 671 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) 672 #define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) 673 #define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) 674 #define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) 675 #if defined(STM32F446xx) || defined(STM32F469_479xx) 676 #define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000) 678 #define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) 679 #if defined(STM32F469_479xx) 680 #define RCC_APB2Periph_DSI ((uint32_t)0x08000000) 683 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF30880CC) == 0x00) && ((PERIPH) != 0x00)) 684 #define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF30886CC) == 0x00) && ((PERIPH) != 0x00)) 693 #define RCC_MCO1Source_HSI ((uint32_t)0x00000000) 694 #define RCC_MCO1Source_LSE ((uint32_t)0x00200000) 695 #define RCC_MCO1Source_HSE ((uint32_t)0x00400000) 696 #define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) 697 #define RCC_MCO1Div_1 ((uint32_t)0x00000000) 698 #define RCC_MCO1Div_2 ((uint32_t)0x04000000) 699 #define RCC_MCO1Div_3 ((uint32_t)0x05000000) 700 #define RCC_MCO1Div_4 ((uint32_t)0x06000000) 701 #define RCC_MCO1Div_5 ((uint32_t)0x07000000) 702 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ 703 ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) 705 #define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ 706 ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ 707 ((DIV) == RCC_MCO1Div_5)) 715 #define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) 716 #define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) 717 #define RCC_MCO2Source_HSE ((uint32_t)0x80000000) 718 #define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) 719 #define RCC_MCO2Div_1 ((uint32_t)0x00000000) 720 #define RCC_MCO2Div_2 ((uint32_t)0x20000000) 721 #define RCC_MCO2Div_3 ((uint32_t)0x28000000) 722 #define RCC_MCO2Div_4 ((uint32_t)0x30000000) 723 #define RCC_MCO2Div_5 ((uint32_t)0x38000000) 724 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ 725 ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) 727 #define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ 728 ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ 729 ((DIV) == RCC_MCO2Div_5)) 737 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 738 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 739 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 740 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) 741 #define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) 742 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 743 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 744 #define RCC_FLAG_BORRST ((uint8_t)0x79) 745 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 746 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 747 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 748 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 749 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 750 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 752 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 753 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 754 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ 755 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 756 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ 757 ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ 758 ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) 760 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 785 #if defined(STM32F410xx) || defined(STM32F446xx) || defined(STM32F469_479xx) 786 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
789 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 790 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
795 #if defined(STM32F40_41xxx) || defined(STM32F401xx) 798 #if defined(STM32F411xE) 799 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
801 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 802 void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
804 #if defined(STM32F446xx) 805 void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
809 #if defined(STM32F469_479xx) 810 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
812 #if defined(STM32F446xx) 813 void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
815 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) 816 void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
820 void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
821 void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
836 #if defined(STM32F446xx) 838 void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
841 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) 845 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) 846 void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
847 void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
878 #if defined(STM32F469_479xx) 879 void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
883 #if defined(STM32F446xx) || defined(STM32F469_479xx) 884 void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
885 void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
889 #if defined(STM32F446xx) 890 void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating,
FunctionalState NewState);
891 void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
892 void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
896 #if defined(STM32F410xx) || defined(STM32F446xx) 897 void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
901 #if defined(STM32F410xx) 902 void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource);
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Forces or releases AHB2 peripheral reset.
void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Forces or releases AHB1 peripheral reset.
uint8_t RCC_GetSYSCLKSource(void)
Returns the clock source used as system clock.
void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
Configures the SAI clock Divider coming from PLLI2S.
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
Configures the LTDC clock Divider coming from PLLSAI.
void RCC_RTCCLKCmd(FunctionalState NewState)
Enables or disables the RTC clock.
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
Configures the main PLL clock source, multiplication and division factors.
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Enables or disables the Clock Security System.
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Configures the RTC clock (RTCCLK).
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Forces or releases Low Speed APB (APB1) peripheral reset.
void RCC_LSEConfig(uint8_t RCC_LSE)
Configures the External Low Speed oscillator (LSE).
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Checks whether the specified RCC interrupt has occurred or not.
void RCC_PLLSAICmd(FunctionalState NewState)
Enables or disables the PLLSAI.
CMSIS Cortex-M4 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
void RCC_LSICmd(FunctionalState NewState)
Enables or disables the Internal Low Speed oscillator (LSI).
void RCC_ClearFlag(void)
Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
void RCC_LSEModeConfig(uint8_t RCC_Mode)
Configures the External Low Speed oscillator mode (LSE mode).
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
Selects the clock source to output on MCO1 pin(PA8).
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
Configures the Timers clocks prescalers selection.
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Configures the AHB clock (HCLK).
void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock.
ErrorStatus RCC_WaitForHSEStartUp(void)
Waits for HSE start-up.
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Adjusts the Internal High Speed oscillator (HSI) calibration value.
void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
Configures the I2S clock source (I2SCLK).
void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
Configures the PLLI2S clock multiplication and division factors.
void RCC_HSEConfig(uint8_t RCC_HSE)
Configures the External High Speed oscillator (HSE).
void RCC_PLLCmd(FunctionalState NewState)
Enables or disables the main PLL.
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Enables or disables the specified RCC interrupts.
void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Forces or releases AHB3 peripheral reset.
void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
Configures the SAI clock Divider coming from PLLSAI.
void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
Enables or disables the AHB3 peripheral clock.
void RCC_PCLK1Config(uint32_t RCC_HCLK)
Configures the Low Speed APB clock (PCLK1).
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Enables or disables the High Speed APB (APB2) peripheral clock.
void RCC_PCLK2Config(uint32_t RCC_HCLK)
Configures the High Speed APB clock (PCLK2).
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
Selects the clock source to output on MCO2 pin(PC9).
uint32_t SYSCLK_Frequency
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Configures the system clock (SYSCLK).
void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock.
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Checks whether the specified RCC flag is set or not.
void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Forces or releases High Speed APB (APB2) peripheral reset.
void RCC_ClearITPendingBit(uint8_t RCC_IT)
Clears the RCC's interrupt pending bits.
void RCC_BackupResetCmd(FunctionalState NewState)
Forces or releases the Backup domain reset.
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Enables or disables the Low Speed APB (APB1) peripheral clock.
void RCC_HSICmd(FunctionalState NewState)
Enables or disables the Internal High Speed oscillator (HSI).
void RCC_DeInit(void)
Resets the RCC clock configuration to the default reset state.
void RCC_PLLI2SCmd(FunctionalState NewState)
Enables or disables the PLLI2S.