usbhs_device.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #ifndef USBHS_DEVICE_H_INCLUDED
38 #define USBHS_DEVICE_H_INCLUDED
39 
40 #include "compiler.h"
41 #include "preprocessor.h"
42 
44 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
49 
51 #ifndef USBHS_RAM_ADDR
52 #define USBHS_RAM_ADDR 0xA0100000u
53 #endif
54 
60 
61 #ifndef USBHS_DEVEPTCFG_EPDIR_Pos
62 // Bit pos is not defined in SAM header file but we need it.
63 # define USBHS_DEVEPTCFG_EPDIR_Pos 8
64 #endif
65 
70 #define udd_get_endpoint_max_nbr() (9)
71 #define UDD_MAX_PEP_NB (udd_get_endpoint_max_nbr() + 1)
72 #define udd_get_endpoint_bank_max_nbr(ep) ((ep == 0) ? 1 : (( ep <= 2) ? 3 : 2))
74 #define udd_get_endpoint_size_max(ep) (((ep) == 0) ? 64 : 1024)
76 #define Is_udd_endpoint_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 7)) ? true : false)
78 #define Is_udd_endpoint_high_bw_supported(ep) (((ep) >= 2) ? true : false)
80 
85 #define udd_low_speed_enable() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_LS))
86 #define udd_low_speed_disable() (Clr_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_LS))
87 #define Is_udd_low_speed_enable() (Tst_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_LS))
89 
90 #ifdef USBHS_DEVCTRL_SPDCONF_HIGH_SPEED
91 # define udd_high_speed_enable() (Wr_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_SPDCONF_Msk, 0))
93 # define udd_high_speed_disable() (Wr_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_SPDCONF_Msk, 3))
95 # define Is_udd_full_speed_mode() (Rd_bitfield(USBHS->USBHS_SR, USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED)
97 #else
98 # define udd_high_speed_enable() do { } while (0)
99 # define udd_high_speed_disable() do { } while (0)
100 # define Is_udd_full_speed_mode() true
101 #endif
102 
106 #ifdef USBHS_DEVCTRL_SPDCONF_HIGH_SPEED
107 # define udd_enable_hs_test_mode() (Wr_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_SPDCONF_Msk, 2))
109 # define udd_enable_hs_test_mode_j() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_TSTJ))
110 # define udd_enable_hs_test_mode_k() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_TSTK))
111 # define udd_enable_hs_test_mode_packet() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_TSTPCKT))
112 #endif
113 
119 #define udd_detach_device() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_DETACH))
120 #define udd_attach_device() (Clr_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_DETACH))
122 #define Is_udd_detached() (Tst_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_DETACH))
124 
126 
130 
133 #define udd_initiate_remote_wake_up() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_RMWKUP))
134 #define Is_udd_pending_remote_wake_up() (Tst_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_RMWKUP))
135 
140 #define udd_enable_remote_wake_up_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_UPRSMES)
141 #define udd_disable_remote_wake_up_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_UPRSMEC)
142 #define Is_udd_remote_wake_up_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_UPRSME))
143 #define udd_ack_remote_wake_up_start() (USBHS->USBHS_DEVICR = USBHS_DEVICR_UPRSMC)
144 #define udd_raise_remote_wake_up_start() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_UPRSMS)
145 #define Is_udd_remote_wake_up_start() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_UPRSM))
146 
151 #define udd_enable_resume_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_EORSMES)
152 #define udd_disable_resume_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_EORSMEC)
153 #define Is_udd_resume_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_EORSME))
154 #define udd_ack_resume() (USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSMC)
155 #define udd_raise_resume() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_EORSMS)
156 #define Is_udd_resume() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_EORSM))
157 
162 #define udd_enable_wake_up_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES)
163 #define udd_disable_wake_up_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC)
164 #define Is_udd_wake_up_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_WAKEUPE))
165 #define udd_ack_wake_up() (USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC)
166 #define udd_raise_wake_up() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_WAKEUPS)
167 #define Is_udd_wake_up() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_WAKEUP))
168 
173 #define udd_enable_reset_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_EORSTES)
174 #define udd_disable_reset_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_EORSTEC)
175 #define Is_udd_reset_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_EORSTE))
176 #define udd_ack_reset() (USBHS->USBHS_DEVICR = USBHS_DEVICR_EORSTC)
177 #define udd_raise_reset() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_EORSTS)
178 #define Is_udd_reset() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_EORST))
179 
183 #define udd_enable_sof_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_SOFES)
184 #define udd_disable_sof_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SOFEC)
185 #define Is_udd_sof_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_SOFE))
186 #define udd_ack_sof() (USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC)
187 #define udd_raise_sof() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_SOFS)
188 #define Is_udd_sof() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_SOF))
189 #define udd_frame_number() (Rd_bitfield(USBHS->USBHS_DEVFNUM, USBHS_DEVFNUM_FNUM_Msk))
190 #define Is_udd_frame_number_crc_error() (Tst_bits(USBHS->USBHS_DEVFNUM, USBHS_DEVFNUM_FNCERR))
191 
195 #define udd_enable_msof_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_MSOFES)
196 #define udd_disable_msof_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_MSOFEC)
197 #define Is_udd_msof_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_MSOFE))
198 #define udd_ack_msof() (USBHS->USBHS_DEVICR = USBHS_DEVIMR_MSOFE)
199 #define udd_raise_msof() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_MSOFS)
200 #define Is_udd_msof() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_MSOF))
201 #define udd_micro_frame_number() \
202  (Rd_bitfield(USBHS->USBHS_DEVFNUM, (USBHS_DEVFNUM_FNUM_Msk|USBHS_DEVFNUM_MFNUM_Msk)))
203 
207 #define udd_enable_suspend_interrupt() (USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES)
208 #define udd_disable_suspend_interrupt() (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC)
209 #define Is_udd_suspend_interrupt_enabled() (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_SUSPE))
210 #define udd_ack_suspend() (USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC)
211 #define udd_raise_suspend() (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_SUSPS)
212 #define Is_udd_suspend() (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_SUSP))
213 
216 
221 #define udd_enable_address() (Set_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_ADDEN))
222 #define udd_disable_address() (Clr_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_ADDEN))
224 #define Is_udd_address_enabled() (Tst_bits(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_ADDEN))
225 #define udd_configure_address(addr) (Wr_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_UADD_Msk, addr))
227 #define udd_get_configured_address() (Rd_bitfield(USBHS->USBHS_DEVCTRL, USBHS_DEVCTRL_UADD_Msk))
229 
231 
235 
238 #define USBHS_ARRAY(reg,index) ((&(USBHS->reg))[(index)])
239 
244 #define udd_enable_endpoint(ep) (Set_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPEN0 << (ep)))
245 #define udd_disable_endpoint(ep) (Clr_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPEN0 << (ep)))
247 #define Is_udd_endpoint_enabled(ep) (Tst_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPEN0 << (ep)))
249 #define udd_reset_endpoint(ep) \
251  do { \
252  Set_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPRST0 << (ep)); \
253  Clr_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPRST0 << (ep)); \
254  } while (0)
255 #define Is_udd_resetting_endpoint(ep) (Tst_bits(USBHS->USBHS_DEVEPT, USBHS_DEVEPT_EPRST0 << (ep)))
257 
259 #define udd_configure_endpoint_type(ep, type) (Wr_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPTYPE_Msk, type))
260 #define udd_get_endpoint_type(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPTYPE_Msk))
262 #define udd_enable_endpoint_bank_autoswitch(ep) (Set_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_AUTOSW))
264 #define udd_disable_endpoint_bank_autoswitch(ep) (Clr_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_AUTOSW))
266 #define Is_udd_endpoint_bank_autoswitch_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_AUTOSW))
267 #define udd_configure_endpoint_direction(ep, dir) (Wr_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPDIR, dir))
269 #define udd_get_endpoint_direction(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPDIR))
271 #define Is_udd_endpoint_in(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPDIR))
272 #define udd_format_endpoint_size(size) (32 - clz(((uint32_t)min(max(size, 8), 1024) << 1) - 1) - 1 - 3)
276 #define udd_configure_endpoint_size(ep, size) (Wr_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPSIZE_Msk, udd_format_endpoint_size(size)))
278 #define udd_get_endpoint_size(ep) (8 << Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPSIZE_Msk))
280 #define udd_configure_endpoint_bank(ep, bank) (Wr_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPBK_Msk, bank))
282 #define udd_get_endpoint_bank(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPBK_Msk)+1)
284 #define udd_allocate_memory(ep) (Set_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_ALLOC))
286 #define udd_unallocate_memory(ep) (Clr_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_ALLOC))
288 #define Is_udd_memory_allocated(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_ALLOC))
289 
291 #define udd_configure_endpoint(ep, type, dir, size, bank) (\
292  Wr_bits(USBHS_ARRAY(USBHS_DEVEPTCFG[0], ep), USBHS_DEVEPTCFG_EPTYPE_Msk |\
293  USBHS_DEVEPTCFG_EPDIR |\
294  USBHS_DEVEPTCFG_EPSIZE_Msk |\
295  USBHS_DEVEPTCFG_EPBK_Msk , \
296  (((uint32_t)(type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk) |\
297  (((uint32_t)(dir ) << USBHS_DEVEPTCFG_EPDIR_Pos ) & USBHS_DEVEPTCFG_EPDIR) |\
298  ( (uint32_t)udd_format_endpoint_size(size) << USBHS_DEVEPTCFG_EPSIZE_Pos) |\
299  (((uint32_t)(bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk))\
300 )
301 #define Is_udd_endpoint_configured(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_CFGOK))
303 #define udd_control_direction() (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], EP_CONTROL), USBHS_DEVEPTISR_CTRLDIR))
305 
307 #define udd_reset_data_toggle(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_RSTDTS)
308 #define Is_udd_data_toggle_reset(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_RSTDT))
310 #define udd_data_toggle(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_DTSEQ_Msk))
312 
314 
318 
323 #define udd_enable_endpoint_interrupt(ep) (USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0 << (ep))
324 #define udd_disable_endpoint_interrupt(ep) (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_PEP_0 << (ep))
326 #define Is_udd_endpoint_interrupt_enabled(ep) (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_PEP_0 << (ep)))
328 #define Is_udd_endpoint_interrupt(ep) (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_PEP_0 << (ep)))
330 #define udd_get_interrupt_endpoint_number() (ctz(((USBHS->USBHS_DEVISR >> USBHS_DEVISR_PEP_Pos) & \
332  (USBHS->USBHS_DEVIMR >> USBHS_DEVIMR_PEP_Pos)) | \
333  (1 << MAX_PEP_NB)))
334 #define USBHS_DEVISR_PEP_Pos 12
335 #define USBHS_DEVIMR_PEP_Pos 12
336 
342 #define udd_enable_stall_handshake(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_STALLRQS)
343 #define udd_disable_stall_handshake(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_STALLRQC)
345 #define Is_udd_endpoint_stall_requested(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_STALLRQ))
347 #define Is_udd_stall(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_STALLEDI))
349 #define udd_ack_stall(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_STALLEDIC)
351 #define udd_raise_stall(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_STALLEDIS)
353 #define udd_enable_stall_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_STALLEDES)
355 #define udd_disable_stall_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_STALLEDEC)
357 #define Is_udd_stall_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_STALLEDE))
359 
361 #define Is_udd_nak_out(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_NAKOUTI))
362 #define udd_ack_nak_out(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_NAKOUTIC)
364 #define udd_raise_nak_out(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_NAKOUTIS)
366 #define udd_enable_nak_out_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_NAKOUTES)
368 #define udd_disable_nak_out_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_NAKOUTEC)
370 #define Is_udd_nak_out_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_NAKOUTE))
372 
374 #define Is_udd_nak_in(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_NAKINI))
375 #define udd_ack_nak_in(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_NAKINIC)
377 #define udd_raise_nak_in(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_NAKINIS)
379 #define udd_enable_nak_in_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_NAKINES)
381 #define udd_disable_nak_in_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_NAKINEC)
383 #define Is_udd_nak_in_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_NAKINE))
385 
387 #define udd_ack_overflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_OVERFIC)
388 #define udd_raise_overflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_OVERFIS)
390 #define Is_udd_overflow(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_OVERFI))
392 #define udd_enable_overflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_OVERFES)
394 #define udd_disable_overflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_OVERFEC)
396 #define Is_udd_overflow_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_OVERFE))
398 
400 #define udd_ack_underflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_UNDERFIC)
401 #define udd_raise_underflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_UNDERFIS)
403 #define Is_udd_underflow(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_UNDERFI))
405 #define udd_enable_underflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_UNDERFES)
407 #define udd_disable_underflow_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_UNDERFEC)
409 #define Is_udd_underflow_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_UNDERFE))
411 
413 #define Is_udd_crc_error(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_CRCERRI))
414 #define udd_ack_crc_error(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_CRCERRIC)
416 #define udd_raise_crc_error(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_CRCERRIS)
418 #define udd_enable_crc_error_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_CRCERRES)
420 #define udd_disable_crc_error_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_CRCERREC)
422 #define Is_udd_crc_error_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_CRCERRE))
424 
429 
431 #define Is_udd_read_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_RWALL))
432 #define Is_udd_write_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_RWALL))
434 
436 #define udd_byte_count(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_BYCT_Msk))
437 #define udd_ack_fifocon(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_FIFOCONC)
439 #define Is_udd_fifocon(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_FIFOCON))
441 
443 #define udd_nb_busy_bank(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_NBUSYBK_Msk))
444 #define udd_current_bank(ep) (Rd_bitfield(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_CURRBK_Msk))
446 #define udd_kill_last_in_bank(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_KILLBKS)
448 #define Is_udd_kill_last(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_KILLBK))
449 #define Is_udd_last_in_bank_killed(ep) (!Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_KILLBK))
451 #define udd_force_bank_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_NBUSYBKS)
453 #define udd_unforce_bank_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_NBUSYBKS)
455 #define udd_enable_bank_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_NBUSYBKES)
457 #define udd_disable_bank_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_NBUSYBKEC)
459 #define Is_udd_bank_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_NBUSYBKE))
461 
463 #define Is_udd_short_packet(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_SHORTPACKET))
464 #define udd_ack_short_packet(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_SHORTPACKETC)
466 #define udd_raise_short_packet(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_SHORTPACKETS)
468 #define udd_enable_short_packet_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_SHORTPACKETES)
470 #define udd_disable_short_packet_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_SHORTPACKETEC)
472 #define Is_udd_short_packet_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_SHORTPACKETE))
474 
476 #define Is_udd_setup_received(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_RXSTPI))
477 #define udd_ack_setup_received(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_RXSTPIC)
479 #define udd_raise_setup_received(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_RXSTPIS)
481 #define udd_enable_setup_received_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_RXSTPES)
483 #define udd_disable_setup_received_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_RXSTPEC)
485 #define Is_udd_setup_received_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_RXSTPE))
487 
489 #define Is_udd_out_received(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_RXOUTI))
490 #define udd_ack_out_received(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_RXOUTIC)
492 #define udd_raise_out_received(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_RXOUTIS)
494 #define udd_enable_out_received_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_RXOUTES)
496 #define udd_disable_out_received_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_RXOUTEC)
498 #define Is_udd_out_received_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_RXOUTE))
500 
502 #define Is_udd_in_send(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTISR[0], ep), USBHS_DEVEPTISR_TXINI))
503 #define udd_ack_in_send(ep) (USBHS_ARRAY(USBHS_DEVEPTICR[0], ep) = USBHS_DEVEPTICR_TXINIC)
505 #define udd_raise_in_send(ep) (USBHS_ARRAY(USBHS_DEVEPTIFR[0], ep) = USBHS_DEVEPTIFR_TXINIS)
507 #define udd_enable_in_send_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0], ep) = USBHS_DEVEPTIER_TXINES)
509 #define udd_disable_in_send_interrupt(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0], ep) = USBHS_DEVEPTIDR_TXINEC)
511 #define Is_udd_in_send_interrupt_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0], ep), USBHS_DEVEPTIMR_TXINE))
513 
514 
524 #define udd_get_endpoint_fifo_access(ep, scale) \
525  (((volatile TPASTE2(U, scale) (*)[0x8000 / ((scale) / 8)])USBHS_RAM_ADDR)[(ep)])
526 
530 
532 #define UDD_ENDPOINT_MAX_TRANS 0x10000
533 #define udd_enable_endpoint_int_dis_hdma_req(ep) (USBHS_ARRAY(USBHS_DEVEPTIER[0](ep) = USBHS_DEVEPTIER_EPDISHDMAS)
535 #define udd_disable_endpoint_int_dis_hdma_req(ep) (USBHS_ARRAY(USBHS_DEVEPTIDR[0](ep) = USBHS_DEVEPTIDR_EPDISHDMAC)
537 #define Is_udd_endpoint_int_dis_hdma_req_enabled(ep) (Tst_bits(USBHS_ARRAY(USBHS_DEVEPTIMR[0](ep), USBHS_DEVEPTIMR_EPDISHDMA))
539 
541 #define udd_raise_endpoint_dma_interrupt(ep) (USBHS->USBHS_DEVIFR = USBHS_DEVIFR_DMA_1 << ((ep) - 1))
542 #define udd_clear_endpoint_dma_interrupt(ep) (USBHS->USBHS_DEVICR = USBHS_DEVISR_DMA_1 << ((ep) - 1))
544 #define Is_udd_endpoint_dma_interrupt(ep) (Tst_bits(USBHS->USBHS_DEVISR, USBHS_DEVISR_DMA_1 << ((ep) - 1)))
546 #define udd_enable_endpoint_dma_interrupt(ep) (USBHS->USBHS_DEVIER = USBHS_DEVIER_DMA_1 << ((ep) - 1))
548 #define udd_disable_endpoint_dma_interrupt(ep) (USBHS->USBHS_DEVIDR = USBHS_DEVIDR_DMA_1 << ((ep) - 1))
550 #define Is_udd_endpoint_dma_interrupt_enabled(ep) (Tst_bits(USBHS->USBHS_DEVIMR, USBHS_DEVIMR_DMA_1 << ((ep) - 1)))
552 
556 typedef struct {
557  uint32_t *NXT_DSC_ADD;
558 } uotghs_dma_nextdesc_t;
560 typedef struct {
561  uint32_t CHANN_ENB:1,
562  LDNXT_DSC:1,
563  END_TR_EN:1,
564  END_B_EN:1,
565  END_TR_IT:1,
566  END_BUFFIT:1,
567  DESC_LD_IT:1,
568  BUST_LCK:1,
569  reserved:8,
570  BUFF_LENGTH:16;
571 } uotghs_dma_control_t;
573 typedef struct {
574  uint32_t CHANN_ENB:1,
575  CHANN_ACT:1,
576  reserved0:2,
577  END_TR_ST:1,
578  END_BF_ST:1,
579  DESC_LDST:1,
580  reserved1:9,
581  BUFF_COUNT:16;
582 } uotghs_dma_status_t;
584 typedef struct {
585  union {
586  uint32_t nextdesc;
587  uotghs_dma_nextdesc_t NEXTDESC;
588  };
589  uint32_t addr;
590  union {
591  uint32_t control;
592  uotghs_dma_control_t CONTROL;
593  };
594  uint32_t reserved;
595 } sam_uotghs_dmadesc_t, uotghs_dmadesc_t;
597 typedef struct {
598  union {
599  uint32_t nextdesc;
600  uotghs_dma_nextdesc_t NEXTDESC;
601  };
602  uint32_t addr;
603  union {
604  uint32_t control;
605  uotghs_dma_control_t CONTROL;
606  };
607  union {
608  unsigned long status;
609  uotghs_dma_status_t STATUS;
610  };
611 } sam_uotghs_dmach_t, uotghs_dmach_t;
613 #define UDD_ENDPOINT_DMA_STOP_NOW (0)
614 #define UDD_ENDPOINT_DMA_RUN_AND_STOP (USBHS_DEVDMACONTROL_CHANN_ENB)
615 #define UDD_ENDPOINT_DMA_LOAD_NEXT_DESC (USBHS_DEVDMACONTROL_LDNXT_DSC)
616 #define UDD_ENDPOINT_DMA_RUN_AND_LINK (USBHS_DEVDMACONTROL_CHANN_ENB|USBHS_DEVDMACONTROL_LDNXT_DSC)
617 #define USBHS_UDDMA_ARRAY(ep) (((volatile uotghs_dmach_t *)USBHS->USBHS_DEVDMA)[(ep) - 1])
619 
621 #define udd_endpoint_dma_set_control(ep,desc) (USBHS_UDDMA_ARRAY(ep).control = desc)
622 #define udd_endpoint_dma_get_control(ep) (USBHS_UDDMA_ARRAY(ep).control)
624 #define udd_endpoint_dma_set_addr(ep,add) (USBHS_UDDMA_ARRAY(ep).addr = add)
626 #define udd_endpoint_dma_get_status(ep) (USBHS_UDDMA_ARRAY(ep).status)
628 
635 
636 
638 
639 #ifdef __cplusplus
640 }
641 #endif
642 
643 
645 #endif /* USBHS_DEVICE_H_INCLUDED */
sam_uotghs_dmach_t::CONTROL
uotghs_dma_control_t CONTROL
Definition: usbhs_device.h:605
sam_uotghs_dmach_t::nextdesc
uint32_t nextdesc
Definition: usbhs_device.h:599
uotghs_dmadesc_t
struct sam_uotghs_dmadesc_t uotghs_dmadesc_t
uotghs_dma_status_t
Structure for DMA status register.
Definition: usbhs_device.h:573
sam_uotghs_dmadesc_t
Structure for DMA descriptor.
Definition: usbhs_device.h:584
uotghs_dmach_t
struct sam_uotghs_dmach_t uotghs_dmach_t
sam_uotghs_dmach_t::STATUS
uotghs_dma_status_t STATUS
Definition: usbhs_device.h:609
uotghs_dma_control_t::reserved
uint32_t reserved
Definition: usbhs_device.h:561
sam_uotghs_dmach_t::addr
uint32_t addr
Definition: usbhs_device.h:602
uotghs_dma_nextdesc_t::NXT_DSC_ADD
uint32_t * NXT_DSC_ADD
Definition: usbhs_device.h:557
compiler.h
Commonly used includes, types and macros.
sam_uotghs_dmach_t::control
uint32_t control
Definition: usbhs_device.h:604
sam_uotghs_dmadesc_t::control
uint32_t control
Definition: usbhs_device.h:591
sam_uotghs_dmadesc_t::CONTROL
uotghs_dma_control_t CONTROL
Definition: usbhs_device.h:592
sam_uotghs_dmach_t::status
unsigned long status
Definition: usbhs_device.h:608
uotghs_dma_control_t
Structure for DMA control register.
Definition: usbhs_device.h:560
uotghs_dma_status_t::reserved1
uint32_t reserved1
Definition: usbhs_device.h:574
sam_uotghs_dmach_t
Structure for DMA registers in a channel.
Definition: usbhs_device.h:597
uotghs_dma_nextdesc_t
Structure for DMA next descriptor register.
Definition: usbhs_device.h:556
preprocessor.h
Preprocessor utils.
sam_uotghs_dmach_t::NEXTDESC
uotghs_dma_nextdesc_t NEXTDESC
Definition: usbhs_device.h:600
sam_uotghs_dmadesc_t::NEXTDESC
uotghs_dma_nextdesc_t NEXTDESC
Definition: usbhs_device.h:587
sam_uotghs_dmadesc_t::nextdesc
uint32_t nextdesc
Definition: usbhs_device.h:586
sam_uotghs_dmadesc_t::addr
uint32_t addr
Definition: usbhs_device.h:589
sam_uotghs_dmadesc_t::reserved
uint32_t reserved
Definition: usbhs_device.h:594

inertial_sense_ros
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autogenerated on Sun Feb 28 2021 03:17:58