m2m_hif.c
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1 
35 #include "common/include/nm_common.h"
36 #include "driver/source/nmbus.h"
37 #include "driver/source/nmdrv.h"
38 #include "bsp/include/nm_bsp.h"
39 #include "m2m_hif.h"
40 #include "driver/include/m2m_types.h"
41 #include "driver/source/nmasic.h"
42 #include "driver/include/m2m_periph.h"
43 
44 #if (defined NM_EDGE_INTERRUPT)&&(defined NM_LEVEL_INTERRUPT)
45 #error "only one type of interrupt NM_EDGE_INTERRUPT,NM_LEVEL_INTERRUPT"
46 #endif
47 
48 #if !((defined NM_EDGE_INTERRUPT)||(defined NM_LEVEL_INTERRUPT))
49 #error "define interrupt type NM_EDGE_INTERRUPT,NM_LEVEL_INTERRUPT"
50 #endif
51 
52 #ifndef CORTUS_APP
53 #define NMI_AHB_DATA_MEM_BASE 0x30000
54 #define NMI_AHB_SHARE_MEM_BASE 0xd0000
55 
56 #define WIFI_HOST_RCV_CTRL_0 (0x1070)
57 #define WIFI_HOST_RCV_CTRL_1 (0x1084)
58 #define WIFI_HOST_RCV_CTRL_2 (0x1078)
59 #define WIFI_HOST_RCV_CTRL_3 (0x106c)
60 #define WAKE_VALUE (0x5678)
61 #define SLEEP_VALUE (0x4321)
62 #define WAKE_REG (0x1074)
63 
64 #define INTERRUPT_CORTUS_0_3000D0 (0x10a8)
65 #define INTERRUPT_CORTUS_1_3000D0 (0x10ac)
66 #define INTERRUPT_CORTUS_2_3000D0 (0x10b0)
67 #define INTERRUPT_CORTUS_3_3000D0 (0x10b4)
68 
69 
70 static volatile uint8 gu8ChipMode = 0;
71 static volatile uint8 gu8ChipSleep = 0;
72 static volatile uint8 gu8HifSizeDone = 0;
73 static volatile uint8 gu8Interrupt = 0;
74 static volatile uint8 gu8Yield = 0;
75 
76 /*
77  Special codes for managing HIF restriction to OTA rollback/switch only
78 */
79 #define HIF_OTA_RB_ONLY 0xFFFF
80 #define HIFCODE_OTA_RB ((M2M_REQ_GROUP_OTA << 8) | M2M_OTA_REQ_ROLLBACK)
81 #define HIFCODE_OTA_SW ((M2M_REQ_GROUP_OTA << 8) | M2M_OTA_REQ_SWITCH_FIRMWARE)
82 #define HIFCODE_SSL_WRITECERT ((M2M_REQ_GROUP_SSL << 8) | M2M_SSL_REQ_WRITE_OWN_CERTS)
83 #define HIFCODE_WIFI_PASSIVESCAN ((M2M_REQ_GROUP_WIFI << 8) | M2M_WIFI_REQ_PASSIVE_SCAN)
84 /*
85  List of new HIF messages (since last HIF major increase)
86  Each entry is formed of ((GroupId << 8) | OpCode)
87  Additionally, entry 0 used to indicate OTA RB/SW only.
88 */
89 #define NEW_HIF_LIST HIF_OTA_RB_ONLY, HIFCODE_SSL_WRITECERT, HIFCODE_WIFI_PASSIVESCAN
90 /*
91  Array of HIF messages which are not supported by Firmware.
92  During hif_init() this array is rebased using an offset determined by Firmware HIF level.
93 */
94 static uint16 gau16HifBlacklist[] = {NEW_HIF_LIST};
95 #define HIF_BLACKLIST_SZ (sizeof(gau16HifBlacklist)/sizeof(gau16HifBlacklist[0]))
96 static uint8 gu8HifBlOffset = 0;
97 
98 tpfHifCallBack pfWifiCb = NULL;
99 tpfHifCallBack pfIpCb = NULL;
100 tpfHifCallBack pfOtaCb = NULL;
101 tpfHifCallBack pfSigmaCb = NULL;
102 tpfHifCallBack pfHifCb = NULL;
103 tpfHifCallBack pfSSLCb = NULL;
104 
105 static void isr(void)
106 {
107  gu8Interrupt++;
108 #ifdef NM_LEVEL_INTERRUPT
109  nm_bsp_interrupt_ctrl(0);
110 #endif
111 }
112 
113 static sint8 hif_set_rx_done(void)
114 {
115  uint32 reg;
116  sint8 ret = M2M_SUCCESS;
117 #ifdef NM_EDGE_INTERRUPT
118  nm_bsp_interrupt_ctrl(1);
119 #endif
120 
121 
122  if (ISNMC3400(nmi_get_chipid())) {
123  ret = nm_write_reg(INTERRUPT_CORTUS_0_3000D0,1);
124  if(ret != M2M_SUCCESS)goto ERR1;
125  } else {
126  ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0,&reg);
127  if(ret != M2M_SUCCESS)goto ERR1;
128  //reg &= ~(1<<0);
129 
130  /* Set RX Done */
131  reg |= (1<<1);
132  ret = nm_write_reg(WIFI_HOST_RCV_CTRL_0,reg);
133  if(ret != M2M_SUCCESS)goto ERR1;
134  }
135 
136 #ifdef NM_LEVEL_INTERRUPT
137  nm_bsp_interrupt_ctrl(1);
138 #endif
139 ERR1:
140  return ret;
141 
142 }
156 static void m2m_hif_cb(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr)
157 {
158 
159 
160 }
167 sint8 hif_chip_wake(void)
168 {
169  sint8 ret = M2M_SUCCESS;
170  if(gu8ChipSleep == 0)
171  {
172  if((gu8ChipMode == M2M_PS_DEEP_AUTOMATIC)||(gu8ChipMode == M2M_PS_MANUAL))
173  {
174  ret = nm_clkless_wake();
175  if(ret != M2M_SUCCESS)goto ERR1;
176  ret = nm_write_reg(WAKE_REG, WAKE_VALUE);
177  if(ret != M2M_SUCCESS)goto ERR1;
178  }
179  else
180  {
181  }
182  }
183  gu8ChipSleep++;
184 ERR1:
185  return ret;
186 }
201 void hif_set_sleep_mode(uint8 u8Pstype)
202 {
203  gu8ChipMode = u8Pstype;
204 }
216 uint8 hif_get_sleep_mode(void)
217 {
218  return gu8ChipMode;
219 }
226 sint8 hif_chip_sleep(void)
227 {
228  sint8 ret = M2M_SUCCESS;
229 
230  if(gu8ChipSleep >= 1)
231  {
232  gu8ChipSleep--;
233  }
234 
235  if(gu8ChipSleep == 0)
236  {
237  if((gu8ChipMode == M2M_PS_DEEP_AUTOMATIC)||(gu8ChipMode == M2M_PS_MANUAL))
238  {
239  uint32 reg = 0;
240  ret = nm_write_reg(WAKE_REG, SLEEP_VALUE);
241  if(ret != M2M_SUCCESS)goto ERR1;
242  /* Clear bit 1 */
243  ret = nm_read_reg_with_ret(0x1, &reg);
244  if(ret != M2M_SUCCESS)goto ERR1;
245  if(reg&0x2)
246  {
247  reg &=~(1 << 1);
248  ret = nm_write_reg(0x1, reg);
249  }
250  }
251  else
252  {
253  }
254  }
255 ERR1:
256  return ret;
257 }
266 sint8 hif_init(void * arg)
267 {
268  pfWifiCb = NULL;
269  pfIpCb = NULL;
270 
271  gu8ChipSleep = 0;
272  gu8ChipMode = M2M_NO_PS;
273 
274  gu8Interrupt = 0;
275  nm_bsp_register_isr(isr);
276 
277  gu8HifBlOffset = 0;
278  hif_register_cb(M2M_REQ_GROUP_HIF,m2m_hif_cb);
279 
280  return M2M_SUCCESS;
281 }
289 sint8 hif_deinit(void * arg)
290 {
291  sint8 ret = M2M_SUCCESS;
292 #if 0
293  uint32 reg = 0, cnt=0;
294  while (reg != M2M_DISABLE_PS)
295  {
296  nm_bsp_sleep(1);
297  reg = nm_read_reg(STATE_REG);
298  if(++cnt > 1000)
299  {
300  M2M_DBG("failed to stop power save\n");
301  break;
302  }
303  }
304 #endif
305  ret = hif_chip_wake();
306 
307  gu8ChipMode = 0;
308  gu8ChipSleep = 0;
309  gu8HifSizeDone = 0;
310  gu8Interrupt = 0;
311 
312  pfWifiCb = NULL;
313  pfIpCb = NULL;
314  pfOtaCb = NULL;
315  pfHifCb = NULL;
316 
317  return ret;
318 }
327 sint8 hif_check_compatibility(uint16 u16HifInfo)
328 {
329  sint8 ret = M2M_ERR_FW_VER_MISMATCH;
330  if((M2M_GET_HIF_BLOCK(u16HifInfo) == M2M_HIF_BLOCK_VALUE) && (M2M_GET_HIF_MAJOR(u16HifInfo) == M2M_HIF_MAJOR_VALUE))
331  {
332  ret = M2M_SUCCESS;
333  }
334  return ret;
335 }
343 sint8 hif_enable_access(void)
344 {
345  sint8 ret = M2M_SUCCESS;
346  uint16 fw_hif_info = 0;
347 
348  ret = nm_get_hif_info(&fw_hif_info, NULL);
349  if(ret == M2M_SUCCESS)
350  {
351  ret = hif_check_compatibility(fw_hif_info);
352  if(ret == M2M_SUCCESS)
353  {
354  switch(M2M_GET_HIF_MINOR(fw_hif_info))
355  {
356  case 0:
357  gu8HifBlOffset = 1;
358  break;
359  case 1:
360  gu8HifBlOffset = 2;
361  break;
362  case 2:
363  gu8HifBlOffset = 2;
364  break;
365  case 3:
366  gu8HifBlOffset = 3;
367  break;
368  // Additional case to be added each time hif minor increments.
369  // All additional cases to be removed in the event of a hif major increment.
370  // Default catches all cases in which hif minor is greater in Firmware than in Driver.
371  default:
372  gu8HifBlOffset = HIF_BLACKLIST_SZ;
373  break;
374  }
375  }
376  else
377  {
378  gu8HifBlOffset = 0;
379  M2M_ERR("HIF access limited to OTA Switch/Rollback only\n");
380  }
381  }
382  return ret;
383 }
394 sint8 hif_check_code(uint8 u8Gid, uint8 u8OpCode)
395 {
396  uint8 u8BlId;
397  uint16 u16HifCode = ((uint16)u8Gid<<8) | u8OpCode;
398  if((u16HifCode == HIFCODE_OTA_RB) || (u16HifCode == HIFCODE_OTA_SW))
399  {
400  return M2M_SUCCESS;
401  }
402  if(gu8HifBlOffset == 0)
403  {
404  M2M_ERR("HIF OTA rb/sw only\n");
405  return M2M_ERR_SEND;
406  }
407  for(u8BlId = gu8HifBlOffset; u8BlId < HIF_BLACKLIST_SZ; u8BlId++)
408  {
409  if(u16HifCode == gau16HifBlacklist[u8BlId])
410  {
411  M2M_ERR("HIF message unsupported\n");
412  return M2M_ERR_SEND;
413  }
414  }
415  return M2M_SUCCESS;
416 }
439 sint8 hif_send(uint8 u8Gid,uint8 u8Opcode,uint8 *pu8CtrlBuf,uint16 u16CtrlBufSize,
440  uint8 *pu8DataBuf,uint16 u16DataSize, uint16 u16DataOffset)
441 {
442  sint8 ret = M2M_ERR_SEND;
443  volatile tstrHifHdr strHif;
444 
445  strHif.u8Opcode = u8Opcode&(~NBIT7);
446  strHif.u8Gid = u8Gid;
447  strHif.u16Length = M2M_HIF_HDR_OFFSET;
448  if(pu8DataBuf != NULL)
449  {
450  strHif.u16Length += u16DataOffset + u16DataSize;
451  }
452  else
453  {
454  strHif.u16Length += u16CtrlBufSize;
455  }
456 
457  ret = hif_check_code(strHif.u8Gid, strHif.u8Opcode);
458  if(ret != M2M_SUCCESS)
459  {
460  goto ERR1;
461  }
462 
463  ret = hif_chip_wake();
464  if(ret == M2M_SUCCESS)
465  {
466  volatile uint32 reg, dma_addr = 0;
467  volatile uint16 cnt = 0;
468 
469  reg = 0UL;
470  reg |= (uint32)u8Gid;
471  reg |= ((uint32)u8Opcode<<8);
472  reg |= ((uint32)strHif.u16Length<<16);
473  ret = nm_write_reg(NMI_STATE_REG,reg);
474  if(M2M_SUCCESS != ret) goto ERR1;
475 
476  reg = 0;
477  reg |= (1<<1);
478  ret = nm_write_reg(WIFI_HOST_RCV_CTRL_2, reg);
479  if(M2M_SUCCESS != ret) goto ERR1;
480 
481 
482  if (ISNMC3400(nmi_get_chipid())) {
483 
484  ret = nm_write_reg(INTERRUPT_CORTUS_1_3000D0, 1);
485  if(M2M_SUCCESS != ret) goto ERR1;
486  }
487 
488  dma_addr = 0;
489 
490  //nm_bsp_interrupt_ctrl(0);
491 
492  for(cnt = 0; cnt < 1000*5; cnt ++)
493  {
494  ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_2,(uint32 *)&reg);
495  if(ret != M2M_SUCCESS) break;
496 
497  if (!(reg & 0x2))
498  {
499  ret = nm_read_reg_with_ret(0x150400,(uint32 *)&dma_addr);
500  if(ret != M2M_SUCCESS) {
501  /*in case of read error clear the dma address and return error*/
502  dma_addr = 0;
503  }
504  /*in case of success break */
505  break;
506  }
507  //If we are struggling to get a response, start waiting longer
508  if (cnt>=1000)
509  nm_bsp_sleep(5);
510  }
511  //nm_bsp_interrupt_ctrl(1);
512 
513  if (dma_addr != 0)
514  {
515  volatile uint32 u32CurrAddr;
516  u32CurrAddr = dma_addr;
517  strHif.u16Length=NM_BSP_B_L_16(strHif.u16Length);
518  M2M_DBG("Writing into %lx %ld\n", dma_addr, strHif.u16Length);
519  ret = nm_write_block(u32CurrAddr, (uint8*)&strHif, M2M_HIF_HDR_OFFSET);
520  if(M2M_SUCCESS != ret) goto ERR1;
521  u32CurrAddr += M2M_HIF_HDR_OFFSET;
522  if(pu8CtrlBuf != NULL)
523  {
524  ret = nm_write_block(u32CurrAddr, pu8CtrlBuf, u16CtrlBufSize);
525  if(M2M_SUCCESS != ret) goto ERR1;
526  u32CurrAddr += u16CtrlBufSize;
527  }
528  if(pu8DataBuf != NULL)
529  {
530  u32CurrAddr += (u16DataOffset - u16CtrlBufSize);
531  ret = nm_write_block(u32CurrAddr, pu8DataBuf, u16DataSize);
532  if(M2M_SUCCESS != ret) goto ERR1;
533  u32CurrAddr += u16DataSize;
534  }
535 
536  reg = dma_addr << 2;
537 
538  /* MERGEBUG: TODO: Following line of code is to generate the interrupt which
539  is not needed for 3400, need to check if there are any side effects of keeping it
540  */
541  reg |= (1 << 1);
542  ret = nm_write_reg(WIFI_HOST_RCV_CTRL_3, reg);
543  if(M2M_SUCCESS != ret) goto ERR1;
544 
545  if (ISNMC3400(nmi_get_chipid())) {
546  ret = nm_write_reg(INTERRUPT_CORTUS_2_3000D0, 1);
547  if(M2M_SUCCESS != ret) goto ERR1;
548  }
549  }
550  else
551  {
552  M2M_DBG("Failed to alloc rx size\n");
553  ret = M2M_ERR_MEM_ALLOC;
554  goto ERR1;
555  }
556 
557  }
558  else
559  {
560  M2M_ERR("(HIF)Fail to wakup the chip\n");
561  goto ERR1;
562  }
563  ret = hif_chip_sleep();
564 
565 ERR1:
566  return ret;
567 }
576 static sint8 hif_isr(void)
577 {
578  sint8 ret = M2M_SUCCESS;
579  uint32 reg;
580  volatile tstrHifHdr strHif;
581 
582 
583  //if(ret == M2M_SUCCESS)
584  {
585  ret = nm_read_reg_with_ret(0x1070, &reg);
586  if(M2M_SUCCESS == ret)
587  {
588  if(reg & 0x1) /* New interrupt has been received */
589  {
590  uint16 size;
591 
592  nm_bsp_interrupt_ctrl(0);
593  /*Clearing RX interrupt*/
594  ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0,&reg);
595  if(ret != M2M_SUCCESS)goto ERR1;
596  reg &= ~(1<<0);
597  ret = nm_write_reg(WIFI_HOST_RCV_CTRL_0,reg);
598  if(ret != M2M_SUCCESS)goto ERR1;
599  /* read the rx size */
600  ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0, &reg);
601  if(M2M_SUCCESS != ret)
602  {
603  M2M_ERR("(hif) WIFI_HOST_RCV_CTRL_0 bus fail\n");
604  nm_bsp_interrupt_ctrl(1);
605  goto ERR1;
606  }
607  gu8HifSizeDone = 0;
608  size = (uint16)((reg >> 2) & 0xfff);
609  if (size > 0) {
610  uint32 address = 0;
614  ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_1, &address);
615  if(M2M_SUCCESS != ret)
616  {
617  M2M_ERR("(hif) WIFI_HOST_RCV_CTRL_1 bus fail\n");
618  nm_bsp_interrupt_ctrl(1);
619  goto ERR1;
620  }
621  ret = nm_read_block(address, (uint8*)&strHif, sizeof(tstrHifHdr));
622  strHif.u16Length = NM_BSP_B_L_16(strHif.u16Length);
623  if(M2M_SUCCESS != ret)
624  {
625  M2M_ERR("(hif) address bus fail\n");
626  nm_bsp_interrupt_ctrl(1);
627  goto ERR1;
628  }
629  if(strHif.u16Length != size)
630  {
631  if((size - strHif.u16Length) > 4)
632  {
633  M2M_ERR("(hif) Corrupted packet Size = %u <L = %u, G = %u, OP = %02X>\n",
634  size, strHif.u16Length, strHif.u8Gid, strHif.u8Opcode);
635  nm_bsp_interrupt_ctrl(1);
636  ret = M2M_ERR_BUS_FAIL;
637  goto ERR1;
638  }
639  }
640 
641  if(M2M_REQ_GROUP_WIFI == strHif.u8Gid)
642  {
643  if(pfWifiCb)
644  pfWifiCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
645 
646  }
647  else if(M2M_REQ_GROUP_IP == strHif.u8Gid)
648  {
649  if(pfIpCb)
650  pfIpCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
651  }
652  else if(M2M_REQ_GROUP_OTA == strHif.u8Gid)
653  {
654  if(pfOtaCb)
655  pfOtaCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
656  }
657  else if(M2M_REQ_GROUP_SIGMA == strHif.u8Gid)
658  {
659  if(pfSigmaCb)
660  pfSigmaCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
661  }
662  else if(M2M_REQ_GROUP_SSL == strHif.u8Gid)
663  {
664  if(pfSSLCb)
665  pfSSLCb(strHif.u8Opcode,strHif.u16Length - M2M_HIF_HDR_OFFSET, address + M2M_HIF_HDR_OFFSET);
666  }
667  else
668  {
669  M2M_ERR("(hif) invalid group ID\n");
670  ret = M2M_ERR_BUS_FAIL;
671  goto ERR1;
672  }
673  #ifndef ENABLE_UNO_BOARD
674  if(!gu8HifSizeDone)
675  {
676  M2M_ERR("(hif) host app didn't set RX Done\n");
677  ret = hif_set_rx_done();
678  }
679  #endif
680  }
681  else
682  {
683  ret = M2M_ERR_RCV;
684  M2M_ERR("(hif) Wrong Size\n");
685  goto ERR1;
686  }
687  }
688  else
689  {
690 #ifndef WIN32
691  M2M_ERR("(hif) False interrupt %lx",reg);
692 #endif
693  }
694  }
695  else
696  {
697  M2M_ERR("(hif) Fail to Read interrupt reg\n");
698  }
699  }
700 
701 ERR1:
702  return ret;
703 }
704 
711 void hif_yield(void)
712 {
713  gu8Yield = 1;
714 }
715 
716 sint8 hif_handle_isr(void)
717 {
718  sint8 ret = M2M_SUCCESS;
719 
720  if (gu8Interrupt) {
721  ret = hif_chip_wake();
722  if(ret == M2M_SUCCESS)
723  {
724  gu8Yield = 0;
725  while (gu8Interrupt && !gu8Yield) {
726  /*must be at that place because of the race of interrupt increment and that decrement*/
727  /*when the interrupt enabled*/
728  gu8Interrupt--;
729  while(1)
730  {
731  ret = hif_isr();
732  if(ret == M2M_SUCCESS) {
733  /*we will try forever until we get that interrupt*/
734  /*Fail return errors here due to bus errors (reading expected values)*/
735  break;
736  } else {
737  M2M_ERR("(HIF) Fail to handle interrupt %d try Again..\n",ret);
738  }
739  }
740  }
741  ret = hif_chip_sleep();
742  }
743  else {
744  M2M_ERR("(hif) FAIL to wakeup the chip\n");
745  }
746  }
747  return ret;
748 }
749 /*
750 * @fn hif_receive
751 * @brief Host interface interrupt service routine
752 * @param [in] u32Addr
753 * Receive start address
754 * @param [out] pu8Buf
755 * Pointer to receive buffer. Allocated by the caller
756 * @param [in] u16Sz
757 * Receive buffer size
758 * @param [in] isDone
759 * If you don't need any more packets send True otherwise send false
760 * @return The function shall return ZERO for successful operation and a negative value otherwise.
761 */
762 sint8 hif_receive(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz, uint8 isDone)
763 {
764  uint32 address, reg;
765  uint16 size;
766  sint8 ret = M2M_SUCCESS;
767 
768  if(u32Addr == 0 || pu8Buf == NULL || u16Sz == 0)
769  {
770  if(isDone)
771  {
772  gu8HifSizeDone = 1;
773 
774  /* set RX done */
775  ret = hif_set_rx_done();
776 
777  if((u32Addr == 0) && (pu8Buf == NULL) && (u16Sz == 0))
778  return M2M_SUCCESS;
779  }
780 
781  ret = M2M_ERR_FAIL;
782  M2M_ERR(" hif_receive: Invalid argument\n");
783  goto ERR1;
784  }
785 
786  ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_0,&reg);
787  if(ret != M2M_SUCCESS)goto ERR1;
788 
789 
790  size = (uint16)((reg >> 2) & 0xfff);
791  ret = nm_read_reg_with_ret(WIFI_HOST_RCV_CTRL_1,&address);
792  if(ret != M2M_SUCCESS)goto ERR1;
793 
794  /* Receive the payload */
795  ret = nm_read_block(u32Addr, pu8Buf, u16Sz);
796  if(ret != M2M_SUCCESS)goto ERR1;
797 
798  if(u16Sz > size)
799  {
800  ret = M2M_ERR_FAIL;
801  M2M_ERR("APP Requested Size is larger than the recived buffer size <%d><%d>\n",u16Sz, size);
802  goto ERR1;
803  }
804  if((u32Addr < address)||((u32Addr + u16Sz)>(address+size)))
805  {
806  ret = M2M_ERR_FAIL;
807  M2M_ERR("APP Requested Address beyond the recived buffer address and length\n");
808  goto ERR1;
809  }
810 
811  /* check if this is the last packet */
812  if(isDone || (((address+size) - (u32Addr+u16Sz)) == 0) ||
813  ((4 - ((u32Addr+u16Sz) & 3)) == ((address+size) - (u32Addr+u16Sz)))) /* Length in the RCV CTRL 0 register is rounded off to 4 by the firmware,
814  but length inside the HIF header is not, Hence consider done if number
815  of rounding bytes equal to length left to read */
816  {
817  gu8HifSizeDone = 1;
818 
819  /* set RX done */
820  ret = hif_set_rx_done();
821  }
822 
823 
824 
825 ERR1:
826  return ret;
827 }
828 
839 sint8 hif_register_cb(uint8 u8Grp,tpfHifCallBack fn)
840 {
841  sint8 ret = M2M_SUCCESS;
842  switch(u8Grp)
843  {
844  case M2M_REQ_GROUP_IP:
845  pfIpCb = fn;
846  break;
847  case M2M_REQ_GROUP_WIFI:
848  pfWifiCb = fn;
849  break;
850  case M2M_REQ_GROUP_OTA:
851  pfOtaCb = fn;
852  break;
853  case M2M_REQ_GROUP_HIF:
854  pfHifCb = fn;
855  break;
856  case M2M_REQ_GROUP_SIGMA:
857  pfSigmaCb = fn;
858  break;
859  case M2M_REQ_GROUP_SSL:
860  pfSSLCb = fn;
861  break;
862  default:
863  M2M_ERR("GRp ? %d\n",u8Grp);
864  ret = M2M_ERR_FAIL;
865  break;
866  }
867  return ret;
868 }
869 
870 #endif
M2M_ERR_FAIL
#define M2M_ERR_FAIL
Definition: nm_common.h:63
hif_chip_wake
sint8 hif_chip_wake(void)
To Wakeup the chip.
Definition: m2m_hif.c:167
tpfHifCallBack
void(* tpfHifCallBack)(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr)
used to point to Wi-Fi call back function depend on Arduino project or other projects.
Definition: m2m_hif.h:86
m2m_periph.h
WINC3400 Peripherals Application Interface.
nm_read_block
sint8 nm_read_block(uint32 u32Addr, uint8 *puBuf, uint32 u32Sz)
Definition: nmbus.c:195
nm_common.h
This module contains common APIs declarations.
nm_get_hif_info
sint8 nm_get_hif_info(uint16 *pu16FwHifInfo, uint16 *pu16OtaHifInfo)
Get Hif info of images in both partitions (Firmware and Ota).
Definition: nmdrv.c:55
isr
static void isr(void)
Definition: m2m_hif.c:105
NMI_STATE_REG
#define NMI_STATE_REG
Definition: nmasic.h:45
M2M_HIF_BLOCK_VALUE
#define M2M_HIF_BLOCK_VALUE
Definition: m2m_types.h:133
sint8
signed char sint8
Range of values between -128 to 127.
Definition: nm_bsp.h:111
gu8ChipMode
static volatile uint8 gu8ChipMode
Definition: m2m_hif.c:70
NBIT7
#define NBIT7
Definition: nm_common.h:107
tstrHifHdr
Structure to hold HIF header.
Definition: m2m_hif.h:63
M2M_GET_HIF_MINOR
#define M2M_GET_HIF_MINOR(hif_info)
Definition: m2m_types.h:123
WIFI_HOST_RCV_CTRL_3
#define WIFI_HOST_RCV_CTRL_3
Definition: m2m_hif.c:59
ISNMC3400
#define ISNMC3400(id)
Definition: nmasic.h:65
M2M_ERR_RCV
#define M2M_ERR_RCV
Definition: nm_common.h:53
nm_read_reg_with_ret
sint8 nm_read_reg_with_ret(uint32 u32Addr, uint32 *pu32RetVal)
Definition: nmbus.c:130
nmdrv.h
This module contains WINC3400 M2M driver APIs declarations.
nm_write_block
sint8 nm_write_block(uint32 u32Addr, uint8 *puBuf, uint32 u32Sz)
Definition: nmbus.c:248
hif_yield
void hif_yield(void)
Yields control from interrupt event handler.
Definition: m2m_hif.c:711
nm_bsp_register_isr
void nm_bsp_register_isr(tpfNmBspIsr pfIsr)
Definition: nm_bsp_same70.c:130
M2M_REQ_GROUP_IP
Definition: m2m_types.h:404
hif_handle_isr
sint8 hif_handle_isr(void)
Handle interrupt received from NMC1500 firmware.
Definition: m2m_hif.c:716
gu8Yield
static volatile uint8 gu8Yield
Definition: m2m_hif.c:74
M2M_HIF_HDR_OFFSET
#define M2M_HIF_HDR_OFFSET
Definition: m2m_hif.h:56
M2M_GET_HIF_MAJOR
#define M2M_GET_HIF_MAJOR(hif_info)
Definition: m2m_types.h:122
M2M_ERR_MEM_ALLOC
#define M2M_ERR_MEM_ALLOC
Definition: nm_common.h:54
M2M_SUCCESS
#define M2M_SUCCESS
Definition: nm_common.h:51
HIFCODE_OTA_SW
#define HIFCODE_OTA_SW
Definition: m2m_hif.c:81
WIFI_HOST_RCV_CTRL_0
#define WIFI_HOST_RCV_CTRL_0
Definition: m2m_hif.c:56
pfWifiCb
tpfHifCallBack pfWifiCb
Definition: m2m_hif.c:98
NM_BSP_B_L_16
#define NM_BSP_B_L_16(x)
Definition: nm_bsp.h:241
gu8HifSizeDone
static volatile uint8 gu8HifSizeDone
Definition: m2m_hif.c:72
pfSigmaCb
tpfHifCallBack pfSigmaCb
Definition: m2m_hif.c:101
m2m_types.h
WINC3400 IoT Application Interface Internal Types.
WIFI_HOST_RCV_CTRL_2
#define WIFI_HOST_RCV_CTRL_2
Definition: m2m_hif.c:58
nm_bsp_interrupt_ctrl
void nm_bsp_interrupt_ctrl(uint8 u8Enable)
Enable/Disable interrupts.
Definition: nm_bsp_same70.c:154
NULL
#define NULL
Definition: nm_bsp.h:52
hif_init
sint8 hif_init(void *arg)
To initialize HIF layer.
Definition: m2m_hif.c:266
INTERRUPT_CORTUS_2_3000D0
#define INTERRUPT_CORTUS_2_3000D0
Definition: m2m_hif.c:66
pfHifCb
tpfHifCallBack pfHifCb
Definition: m2m_hif.c:102
uint16
unsigned short uint16
Range of values between 0 to 65535.
Definition: nm_bsp.h:96
pfSSLCb
tpfHifCallBack pfSSLCb
Definition: m2m_hif.c:103
hif_check_code
sint8 hif_check_code(uint8 u8Gid, uint8 u8OpCode)
To check that a particular hif message is supported with the current driver/firmware pair...
Definition: m2m_hif.c:394
hif_check_compatibility
sint8 hif_check_compatibility(uint16 u16HifInfo)
To check the compatibility of an image with the current driver.
Definition: m2m_hif.c:327
M2M_REQ_GROUP_SSL
Definition: m2m_types.h:407
tstrHifHdr::u8Gid
uint8 u8Gid
Definition: m2m_hif.h:65
M2M_DISABLE_PS
#define M2M_DISABLE_PS
Definition: nmasic.c:50
M2M_REQ_GROUP_SIGMA
Definition: m2m_types.h:408
M2M_NO_PS
Definition: m2m_types.h:943
M2M_DBG
#define M2M_DBG(...)
Definition: nm_debug.h:81
hif_register_cb
sint8 hif_register_cb(uint8 u8Grp, tpfHifCallBack fn)
Definition: m2m_hif.c:839
gau16HifBlacklist
static uint16 gau16HifBlacklist[]
Definition: m2m_hif.c:94
nmasic.h
This module contains WINC3400 ASIC specific internal APIs.
nm_bsp_sleep
void nm_bsp_sleep(uint32 u32TimeMsec)
Definition: nm_bsp_same70.c:117
hif_isr
static sint8 hif_isr(void)
Host interface interrupt service routine.
Definition: m2m_hif.c:576
WAKE_REG
#define WAKE_REG
Definition: m2m_hif.c:62
M2M_REQ_GROUP_OTA
Definition: m2m_types.h:406
nm_write_reg
sint8 nm_write_reg(uint32 u32Addr, uint32 u32Val)
Definition: nmbus.c:155
M2M_ERR
#define M2M_ERR(...)
Definition: nm_debug.h:80
hif_set_rx_done
static sint8 hif_set_rx_done(void)
Definition: m2m_hif.c:113
gu8ChipSleep
static volatile uint8 gu8ChipSleep
Definition: m2m_hif.c:71
INTERRUPT_CORTUS_1_3000D0
#define INTERRUPT_CORTUS_1_3000D0
Definition: m2m_hif.c:65
M2M_HIF_MAJOR_VALUE
#define M2M_HIF_MAJOR_VALUE
Definition: m2m_types.h:136
SLEEP_VALUE
#define SLEEP_VALUE
Definition: m2m_hif.c:61
WIFI_HOST_RCV_CTRL_1
#define WIFI_HOST_RCV_CTRL_1
Definition: m2m_hif.c:57
INTERRUPT_CORTUS_0_3000D0
#define INTERRUPT_CORTUS_0_3000D0
Definition: m2m_hif.c:64
hif_enable_access
sint8 hif_enable_access(void)
To enable access to HIF layer, based on HIF level of Firmware. This function reads HIF level directly...
Definition: m2m_hif.c:343
hif_send
sint8 hif_send(uint8 u8Gid, uint8 u8Opcode, uint8 *pu8CtrlBuf, uint16 u16CtrlBufSize, uint8 *pu8DataBuf, uint16 u16DataSize, uint16 u16DataOffset)
Send packet using host interface.
Definition: m2m_hif.c:439
M2M_ERR_SEND
#define M2M_ERR_SEND
Definition: nm_common.h:52
nmi_get_chipid
uint32 nmi_get_chipid(void)
Definition: nmasic.c:278
nmbus.h
This module contains WINC3400 bus APIs implementation.
WAKE_VALUE
#define WAKE_VALUE
Definition: m2m_hif.c:60
m2m_hif_cb
static void m2m_hif_cb(uint8 u8OpCode, uint16 u16DataSize, uint32 u32Addr)
WiFi call back function.
Definition: m2m_hif.c:156
hif_get_sleep_mode
uint8 hif_get_sleep_mode(void)
Get the sleep mode of the HIF layer.
Definition: m2m_hif.c:216
uint32
unsigned long uint32
Range of values between 0 to 4294967295.
Definition: nm_bsp.h:103
HIFCODE_OTA_RB
#define HIFCODE_OTA_RB
Definition: m2m_hif.c:80
nm_bsp.h
This module contains WINC3400 BSP APIs declarations.
M2M_PS_MANUAL
Definition: m2m_types.h:955
tstrHifHdr::u8Opcode
uint8 u8Opcode
Definition: m2m_hif.h:66
uint8
unsigned char uint8
Range of values between 0 to 255.
Definition: nm_bsp.h:89
pfOtaCb
tpfHifCallBack pfOtaCb
Definition: m2m_hif.c:100
gu8HifBlOffset
static uint8 gu8HifBlOffset
Definition: m2m_hif.c:96
M2M_PS_DEEP_AUTOMATIC
Definition: m2m_types.h:951
hif_chip_sleep
sint8 hif_chip_sleep(void)
To make the chip sleep.
Definition: m2m_hif.c:226
M2M_ERR_FW_VER_MISMATCH
#define M2M_ERR_FW_VER_MISMATCH
Definition: nm_common.h:64
M2M_REQ_GROUP_HIF
Definition: m2m_types.h:405
hif_set_sleep_mode
void hif_set_sleep_mode(uint8 u8Pstype)
Set the sleep mode of the HIF layer.
Definition: m2m_hif.c:201
tstrHifHdr::u16Length
uint16 u16Length
Definition: m2m_hif.h:67
m2m_hif.h
This module contains M2M host interface APIs implementation.
M2M_REQ_GROUP_WIFI
Definition: m2m_types.h:403
HIF_BLACKLIST_SZ
#define HIF_BLACKLIST_SZ
Definition: m2m_hif.c:95
NEW_HIF_LIST
#define NEW_HIF_LIST
Definition: m2m_hif.c:89
nm_clkless_wake
sint8 nm_clkless_wake(void)
Wakeup the chip using clockless registers.
Definition: nmasic.c:106
pfIpCb
tpfHifCallBack pfIpCb
Definition: m2m_hif.c:99
nm_read_reg
uint32 nm_read_reg(uint32 u32Addr)
Definition: nmbus.c:104
M2M_ERR_BUS_FAIL
#define M2M_ERR_BUS_FAIL
Definition: nm_common.h:57
M2M_GET_HIF_BLOCK
#define M2M_GET_HIF_BLOCK(hif_info)
Definition: m2m_types.h:120
gu8Interrupt
static volatile uint8 gu8Interrupt
Definition: m2m_hif.c:73
hif_receive
sint8 hif_receive(uint32 u32Addr, uint8 *pu8Buf, uint16 u16Sz, uint8 isDone)
Definition: m2m_hif.c:762
hif_deinit
sint8 hif_deinit(void *arg)
To Deinitialize HIF layer.
Definition: m2m_hif.c:289

inertial_sense_ros
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autogenerated on Sun Feb 28 2021 03:17:57