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Macros | |
| #define | REG_I2SC1_CR (*(__O uint32_t*)0x40090000U) | 
| (I2SC1) Control Register  More... | |
| #define | REG_I2SC1_IDR (*(__O uint32_t*)0x40090018U) | 
| (I2SC1) Interrupt Disable Register  More... | |
| #define | REG_I2SC1_IER (*(__O uint32_t*)0x40090014U) | 
| (I2SC1) Interrupt Enable Register  More... | |
| #define | REG_I2SC1_IMR (*(__I uint32_t*)0x4009001CU) | 
| (I2SC1) Interrupt Mask Register  More... | |
| #define | REG_I2SC1_MR (*(__IO uint32_t*)0x40090004U) | 
| (I2SC1) Mode Register  More... | |
| #define | REG_I2SC1_RHR (*(__I uint32_t*)0x40090020U) | 
| (I2SC1) Receiver Holding Register  More... | |
| #define | REG_I2SC1_SCR (*(__O uint32_t*)0x4009000CU) | 
| (I2SC1) Status Clear Register  More... | |
| #define | REG_I2SC1_SR (*(__I uint32_t*)0x40090008U) | 
| (I2SC1) Status Register  More... | |
| #define | REG_I2SC1_SSR (*(__O uint32_t*)0x40090010U) | 
| (I2SC1) Status Set Register  More... | |
| #define | REG_I2SC1_THR (*(__O uint32_t*)0x40090024U) | 
| (I2SC1) Transmitter Holding Register  More... | |
| #define | REG_I2SC1_VERSION (*(__I uint32_t*)0x40090028U) | 
| (I2SC1) Version Register  More... | |
Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file i2sc1.h.
| #define REG_I2SC1_CR (*(__O uint32_t*)0x40090000U) | 
| #define REG_I2SC1_IDR (*(__O uint32_t*)0x40090018U) | 
| #define REG_I2SC1_IER (*(__O uint32_t*)0x40090014U) | 
| #define REG_I2SC1_IMR (*(__I uint32_t*)0x4009001CU) | 
| #define REG_I2SC1_MR (*(__IO uint32_t*)0x40090004U) | 
| #define REG_I2SC1_RHR (*(__I uint32_t*)0x40090020U) | 
| #define REG_I2SC1_SCR (*(__O uint32_t*)0x4009000CU) | 
| #define REG_I2SC1_SR (*(__I uint32_t*)0x40090008U) | 
| #define REG_I2SC1_SSR (*(__O uint32_t*)0x40090010U) | 
| #define REG_I2SC1_THR (*(__O uint32_t*)0x40090024U) |