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Macros | |
| #define | REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) | 
| (I2SC0) Control Register  More... | |
| #define | REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) | 
| (I2SC0) Interrupt Disable Register  More... | |
| #define | REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) | 
| (I2SC0) Interrupt Enable Register  More... | |
| #define | REG_I2SC0_IMR (*(__I uint32_t*)0x4008C01CU) | 
| (I2SC0) Interrupt Mask Register  More... | |
| #define | REG_I2SC0_MR (*(__IO uint32_t*)0x4008C004U) | 
| (I2SC0) Mode Register  More... | |
| #define | REG_I2SC0_RHR (*(__I uint32_t*)0x4008C020U) | 
| (I2SC0) Receiver Holding Register  More... | |
| #define | REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) | 
| (I2SC0) Status Clear Register  More... | |
| #define | REG_I2SC0_SR (*(__I uint32_t*)0x4008C008U) | 
| (I2SC0) Status Register  More... | |
| #define | REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) | 
| (I2SC0) Status Set Register  More... | |
| #define | REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) | 
| (I2SC0) Transmitter Holding Register  More... | |
| #define | REG_I2SC0_VERSION (*(__I uint32_t*)0x4008C028U) | 
| (I2SC0) Version Register  More... | |
Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
Definition in file i2sc0.h.
| #define REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) | 
| #define REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) | 
| #define REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) | 
| #define REG_I2SC0_IMR (*(__I uint32_t*)0x4008C01CU) | 
| #define REG_I2SC0_MR (*(__IO uint32_t*)0x4008C004U) | 
| #define REG_I2SC0_RHR (*(__I uint32_t*)0x4008C020U) | 
| #define REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) | 
| #define REG_I2SC0_SR (*(__I uint32_t*)0x4008C008U) | 
| #define REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) | 
| #define REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) |