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| #define | REG_MCAN1_BTP (*(__IO uint32_t*)0x4003401CU) |
| | (MCAN1) Bit Timing and Prescaler Register More...
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| #define | REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) |
| | (MCAN1) CC Control Register More...
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| #define | REG_MCAN1_CREL (*(__I uint32_t*)0x40034000U) |
| | (MCAN1) Core Release Register More...
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| #define | REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) |
| | (MCAN1) Customer Register More...
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| #define | REG_MCAN1_DBTP (*(__IO uint32_t*)0x4003400CU) |
| | (MCAN1) Data Bit Timing and Prescaler Register More...
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| #define | REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) |
| | (MCAN1) Error Counter Register More...
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| #define | REG_MCAN1_ENDN (*(__I uint32_t*)0x40034004U) |
| | (MCAN1) Endian Register More...
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| #define | REG_MCAN1_FBTP (*(__IO uint32_t*)0x4003400CU) |
| | (MCAN1) Fast Bit Timing and Prescaler Register More...
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| #define | REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) |
| | (MCAN1) Global Filter Configuration Register More...
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| #define | REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) |
| | (MCAN1) High Priority Message Status Register More...
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| #define | REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) |
| | (MCAN1) Interrupt Enable Register More...
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| #define | REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) |
| | (MCAN1) Interrupt Line Enable Register More...
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| #define | REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) |
| | (MCAN1) Interrupt Line Select Register More...
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| #define | REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) |
| | (MCAN1) Interrupt Register More...
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| #define | REG_MCAN1_NBTP (*(__IO uint32_t*)0x4003401CU) |
| | (MCAN1) Nominal Bit Timing and Prescaler Register More...
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| #define | REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) |
| | (MCAN1) New Data 1 Register More...
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| #define | REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) |
| | (MCAN1) New Data 2 Register More...
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| #define | REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) |
| | (MCAN1) Protocol Status Register More...
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| #define | REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) |
| | (MCAN1) RAM Watchdog Register More...
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| #define | REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) |
| | (MCAN1) Receive Rx Buffer Configuration Register More...
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| #define | REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) |
| | (MCAN1) Receive Buffer / FIFO Element Size Configuration Register More...
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| #define | REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) |
| | (MCAN1) Receive FIFO 0 Acknowledge Register More...
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| #define | REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) |
| | (MCAN1) Receive FIFO 0 Configuration Register More...
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| #define | REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) |
| | (MCAN1) Receive FIFO 0 Status Register More...
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| #define | REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) |
| | (MCAN1) Receive FIFO 1 Acknowledge Register More...
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| #define | REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) |
| | (MCAN1) Receive FIFO 1 Configuration Register More...
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| #define | REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) |
| | (MCAN1) Receive FIFO 1 Status Register More...
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| #define | REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) |
| | (MCAN1) Standard ID Filter Configuration Register More...
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| #define | REG_MCAN1_TDCR (*(__IO uint32_t*)0x40034048U) |
| | (MCAN1) Transmit Delay Compensation Register More...
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| #define | REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) |
| | (MCAN1) Test Register More...
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| #define | REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) |
| | (MCAN1) Timeout Counter Configuration Register More...
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| #define | REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) |
| | (MCAN1) Timeout Counter Value Register More...
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| #define | REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) |
| | (MCAN1) Timestamp Counter Configuration Register More...
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| #define | REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) |
| | (MCAN1) Timestamp Counter Value Register More...
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| #define | REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) |
| | (MCAN1) Transmit Buffer Add Request Register More...
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| #define | REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) |
| | (MCAN1) Transmit Buffer Configuration Register More...
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| #define | REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) |
| | (MCAN1) Transmit Buffer Cancellation Finished Register More...
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| #define | REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) |
| | (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register More...
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| #define | REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) |
| | (MCAN1) Transmit Buffer Cancellation Request Register More...
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| #define | REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) |
| | (MCAN1) Transmit Buffer Request Pending Register More...
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| #define | REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) |
| | (MCAN1) Transmit Buffer Transmission Interrupt Enable Register More...
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| #define | REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) |
| | (MCAN1) Transmit Buffer Transmission Occurred Register More...
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| #define | REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) |
| | (MCAN1) Transmit Event FIFO Acknowledge Register More...
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| #define | REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) |
| | (MCAN1) Transmit Event FIFO Configuration Register More...
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| #define | REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) |
| | (MCAN1) Transmit Event FIFO Status Register More...
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| #define | REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) |
| | (MCAN1) Transmit Buffer Element Size Configuration Register More...
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| #define | REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) |
| | (MCAN1) Transmit FIFO/Queue Status Register More...
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| #define | REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) |
| | (MCAN1) Extended ID AND Mask Register More...
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| #define | REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) |
| | (MCAN1) Extended ID Filter Configuration Register More...
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