This file contains all the functions prototypes for the TIM firmware library. More...
#include "stm32f30x.h"
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Classes | |
| struct | TIM_BDTRInitTypeDef |
| BDTR structure definition. More... | |
| struct | TIM_ICInitTypeDef |
| TIM Input Capture Init structure definition. More... | |
| struct | TIM_OCInitTypeDef |
| TIM Output Compare Init structure definition. More... | |
| struct | TIM_TimeBaseInitTypeDef |
| TIM Time Base Init structure definition. More... | |
Macros | |
| #define | IS_TIM_ALL_PERIPH(PERIPH) |
| #define | IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) |
| #define | IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF) |
| #define | IS_TIM_BREAK1_POLARITY(POLARITY) |
| #define | IS_TIM_BREAK1_STATE(STATE) |
| #define | IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF) |
| #define | IS_TIM_BREAK2_POLARITY(POLARITY) |
| #define | IS_TIM_BREAK2_STATE(STATE) |
| #define | IS_TIM_BREAK_POLARITY(POLARITY) |
| #define | IS_TIM_BREAK_STATE(STATE) |
| #define | IS_TIM_CCX(CCX) |
| #define | IS_TIM_CCXN(CCXN) |
| #define | IS_TIM_CHANNEL(CHANNEL) |
| #define | IS_TIM_CKD_DIV(DIV) |
| #define | IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000)) |
| #define | IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) |
| #define | IS_TIM_COUNTER_MODE(MODE) |
| #define | IS_TIM_DMA_BASE(BASE) |
| #define | IS_TIM_DMA_LENGTH(LENGTH) |
| #define | IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) |
| #define | IS_TIM_ENCODER_MODE(MODE) |
| #define | IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000)) |
| #define | IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) |
| #define | IS_TIM_EXT_POLARITY(POLARITY) |
| #define | IS_TIM_EXT_PRESCALER(PRESCALER) |
| #define | IS_TIM_FORCED_ACTION(ACTION) |
| #define | IS_TIM_GET_FLAG(FLAG) |
| #define | IS_TIM_GET_IT(IT) |
| #define | IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) |
| #define | IS_TIM_IC_POLARITY(POLARITY) |
| #define | IS_TIM_IC_PRESCALER(PRESCALER) |
| #define | IS_TIM_IC_SELECTION(SELECTION) |
| #define | IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) |
| #define | IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) |
| #define | IS_TIM_LIST1_PERIPH(PERIPH) |
| #define | IS_TIM_LIST2_PERIPH(PERIPH) |
| #define | IS_TIM_LIST3_PERIPH(PERIPH) |
| #define | IS_TIM_LIST4_PERIPH(PERIPH) |
| #define | IS_TIM_LIST5_PERIPH(PERIPH) |
| #define | IS_TIM_LIST6_PERIPH(PERIPH) |
| #define | IS_TIM_LIST7_PERIPH(PERIPH) |
| #define | IS_TIM_LIST8_PERIPH(PERIPH) |
| #define | IS_TIM_LOCK_LEVEL(LEVEL) |
| #define | IS_TIM_MSM_STATE(STATE) |
| #define | IS_TIM_OC_MODE(MODE) |
| #define | IS_TIM_OC_POLARITY(POLARITY) |
| #define | IS_TIM_OCCLEAR_STATE(STATE) |
| #define | IS_TIM_OCFAST_STATE(STATE) |
| #define | IS_TIM_OCIDLE_STATE(STATE) |
| #define | IS_TIM_OCM(MODE) |
| #define | IS_TIM_OCN_POLARITY(POLARITY) |
| #define | IS_TIM_OCNIDLE_STATE(STATE) |
| #define | IS_TIM_OCPRELOAD_STATE(STATE) |
| #define | IS_TIM_OPM_MODE(MODE) |
| #define | IS_TIM_OSSI_STATE(STATE) |
| #define | IS_TIM_OSSR_STATE(STATE) |
| #define | IS_TIM_OUTPUT_STATE(STATE) |
| #define | IS_TIM_OUTPUTN_STATE(STATE) |
| #define | IS_TIM_PRESCALER_RELOAD(RELOAD) |
| #define | IS_TIM_PWMI_CHANNEL(CHANNEL) |
| #define | IS_TIM_REMAP(TIM_REMAP) |
| #define | IS_TIM_SLAVE_MODE(MODE) |
| #define | IS_TIM_TRGO2_SOURCE(SOURCE) |
| #define | IS_TIM_TRGO_SOURCE(SOURCE) |
| #define | IS_TIM_TRIGGER_SELECTION(SELECTION) |
| #define | IS_TIM_UPDATE_SOURCE(SOURCE) |
| #define | TIM16_GPIO ((uint16_t)0x0000) |
| #define | TIM16_HSEDiv32 ((uint16_t)0x0002) |
| #define | TIM16_MCO ((uint16_t)0x0003) |
| #define | TIM16_RTC_CLK ((uint16_t)0x0001) |
| #define | TIM1_ADC1_AWDG1 ((uint16_t)0x0001) |
| #define | TIM1_ADC1_AWDG2 ((uint16_t)0x0002) |
| #define | TIM1_ADC1_AWDG3 ((uint16_t)0x0003) |
| #define | TIM1_ADC4_AWDG1 ((uint16_t)0x0004) |
| #define | TIM1_ADC4_AWDG2 ((uint16_t)0x0008) |
| #define | TIM1_ADC4_AWDG3 ((uint16_t)0x000C) |
| #define | TIM8_ADC2_AWDG1 ((uint16_t)0x0001) |
| #define | TIM8_ADC2_AWDG2 ((uint16_t)0x0002) |
| #define | TIM8_ADC2_AWDG3 ((uint16_t)0x0003) |
| #define | TIM8_ADC3_AWDG1 ((uint16_t)0x0004) |
| #define | TIM8_ADC3_AWDG2 ((uint16_t)0x0008) |
| #define | TIM8_ADC3_AWDG3 ((uint16_t)0x000C) |
| #define | TIM_AutomaticOutput_Disable ((uint16_t)0x0000) |
| #define | TIM_AutomaticOutput_Enable ((uint16_t)0x4000) |
| #define | TIM_Break1_Disable ((uint32_t)0x00000000) |
| #define | TIM_Break1_Enable ((uint32_t)0x00001000) |
| #define | TIM_Break1Polarity_High ((uint32_t)0x00002000) |
| #define | TIM_Break1Polarity_Low ((uint32_t)0x00000000) |
| #define | TIM_Break2_Disable ((uint32_t)0x00000000) |
| #define | TIM_Break2_Enable ((uint32_t)0x01000000) |
| #define | TIM_Break2Polarity_High ((uint32_t)0x02000000) |
| #define | TIM_Break2Polarity_Low ((uint32_t)0x00000000) |
| #define | TIM_Break_Disable ((uint16_t)0x0000) |
| #define | TIM_Break_Enable ((uint16_t)0x1000) |
| #define | TIM_BreakPolarity_High ((uint16_t)0x2000) |
| #define | TIM_BreakPolarity_Low ((uint16_t)0x0000) |
| #define | TIM_CCx_Disable ((uint16_t)0x0000) |
| #define | TIM_CCx_Enable ((uint16_t)0x0001) |
| #define | TIM_CCxN_Disable ((uint16_t)0x0000) |
| #define | TIM_CCxN_Enable ((uint16_t)0x0004) |
| #define | TIM_Channel_1 ((uint16_t)0x0000) |
| #define | TIM_Channel_2 ((uint16_t)0x0004) |
| #define | TIM_Channel_3 ((uint16_t)0x0008) |
| #define | TIM_Channel_4 ((uint16_t)0x000C) |
| #define | TIM_Channel_5 ((uint16_t)0x0010) |
| #define | TIM_Channel_6 ((uint16_t)0x0014) |
| #define | TIM_CKD_DIV1 ((uint16_t)0x0000) |
| #define | TIM_CKD_DIV2 ((uint16_t)0x0100) |
| #define | TIM_CKD_DIV4 ((uint16_t)0x0200) |
| #define | TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) |
| #define | TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) |
| #define | TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) |
| #define | TIM_CounterMode_Down ((uint16_t)0x0010) |
| #define | TIM_CounterMode_Up ((uint16_t)0x0000) |
| #define | TIM_DMA_CC1 ((uint16_t)0x0200) |
| #define | TIM_DMA_CC2 ((uint16_t)0x0400) |
| #define | TIM_DMA_CC3 ((uint16_t)0x0800) |
| #define | TIM_DMA_CC4 ((uint16_t)0x1000) |
| #define | TIM_DMA_COM ((uint16_t)0x2000) |
| #define | TIM_DMA_Trigger ((uint16_t)0x4000) |
| #define | TIM_DMA_Update ((uint16_t)0x0100) |
| #define | TIM_DMABase_ARR ((uint16_t)0x000B) |
| #define | TIM_DMABase_BDTR ((uint16_t)0x0011) |
| #define | TIM_DMABase_CCER ((uint16_t)0x0008) |
| #define | TIM_DMABase_CCMR1 ((uint16_t)0x0006) |
| #define | TIM_DMABase_CCMR2 ((uint16_t)0x0007) |
| #define | TIM_DMABase_CCMR3 ((uint16_t)0x0014) |
| #define | TIM_DMABase_CCR1 ((uint16_t)0x000D) |
| #define | TIM_DMABase_CCR2 ((uint16_t)0x000E) |
| #define | TIM_DMABase_CCR3 ((uint16_t)0x000F) |
| #define | TIM_DMABase_CCR4 ((uint16_t)0x0010) |
| #define | TIM_DMABase_CCR5 ((uint16_t)0x0015) |
| #define | TIM_DMABase_CCR6 ((uint16_t)0x0016) |
| #define | TIM_DMABase_CNT ((uint16_t)0x0009) |
| #define | TIM_DMABase_CR1 ((uint16_t)0x0000) |
| #define | TIM_DMABase_CR2 ((uint16_t)0x0001) |
| #define | TIM_DMABase_DCR ((uint16_t)0x0012) |
| #define | TIM_DMABase_DIER ((uint16_t)0x0003) |
| #define | TIM_DMABase_EGR ((uint16_t)0x0005) |
| #define | TIM_DMABase_OR ((uint16_t)0x0013) |
| #define | TIM_DMABase_PSC ((uint16_t)0x000A) |
| #define | TIM_DMABase_RCR ((uint16_t)0x000C) |
| #define | TIM_DMABase_SMCR ((uint16_t)0x0002) |
| #define | TIM_DMABase_SR ((uint16_t)0x0004) |
| #define | TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers |
| #define | TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) |
| #define | TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers |
| #define | TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) |
| #define | TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers |
| #define | TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) |
| #define | TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers |
| #define | TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) |
| #define | TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers |
| #define | TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) |
| #define | TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers |
| #define | TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) |
| #define | TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers |
| #define | TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) |
| #define | TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers |
| #define | TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) |
| #define | TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers |
| #define | TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) |
| #define | TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer |
| #define | TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) |
| #define | TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers |
| #define | TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) |
| #define | TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers |
| #define | TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) |
| #define | TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers |
| #define | TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) |
| #define | TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers |
| #define | TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) |
| #define | TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers |
| #define | TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) |
| #define | TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers |
| #define | TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) |
| #define | TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers |
| #define | TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) |
| #define | TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers |
| #define | TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) |
| #define | TIM_EncoderMode_TI1 ((uint16_t)0x0001) |
| #define | TIM_EncoderMode_TI12 ((uint16_t)0x0003) |
| #define | TIM_EncoderMode_TI2 ((uint16_t)0x0002) |
| #define | TIM_EventSource_Break ((uint16_t)0x0080) |
| #define | TIM_EventSource_Break2 ((uint16_t)0x0100) |
| #define | TIM_EventSource_CC1 ((uint16_t)0x0002) |
| #define | TIM_EventSource_CC2 ((uint16_t)0x0004) |
| #define | TIM_EventSource_CC3 ((uint16_t)0x0008) |
| #define | TIM_EventSource_CC4 ((uint16_t)0x0010) |
| #define | TIM_EventSource_COM ((uint16_t)0x0020) |
| #define | TIM_EventSource_Trigger ((uint16_t)0x0040) |
| #define | TIM_EventSource_Update ((uint16_t)0x0001) |
| #define | TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) |
| #define | TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) |
| #define | TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) |
| #define | TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) |
| #define | TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) |
| #define | TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) |
| #define | TIM_FLAG_Break ((uint32_t)0x00080) |
| #define | TIM_FLAG_Break2 ((uint32_t)0x00100) |
| #define | TIM_FLAG_CC1 ((uint32_t)0x00002) |
| #define | TIM_FLAG_CC1OF ((uint32_t)0x00200) |
| #define | TIM_FLAG_CC2 ((uint32_t)0x00004) |
| #define | TIM_FLAG_CC2OF ((uint32_t)0x00400) |
| #define | TIM_FLAG_CC3 ((uint32_t)0x00008) |
| #define | TIM_FLAG_CC3OF ((uint32_t)0x00800) |
| #define | TIM_FLAG_CC4 ((uint32_t)0x00010) |
| #define | TIM_FLAG_CC4OF ((uint32_t)0x01000) |
| #define | TIM_FLAG_CC5 ((uint32_t)0x10000) |
| #define | TIM_FLAG_CC6 ((uint32_t)0x20000) |
| #define | TIM_FLAG_COM ((uint32_t)0x00020) |
| #define | TIM_FLAG_Trigger ((uint32_t)0x00040) |
| #define | TIM_FLAG_Update ((uint32_t)0x00001) |
| #define | TIM_ForcedAction_Active ((uint16_t)0x0050) |
| #define | TIM_ForcedAction_InActive ((uint16_t)0x0040) |
| #define | TIM_ICPolarity_BothEdge ((uint16_t)0x000A) |
| #define | TIM_ICPolarity_Falling ((uint16_t)0x0002) |
| #define | TIM_ICPolarity_Rising ((uint16_t)0x0000) |
| #define | TIM_ICPSC_DIV1 ((uint16_t)0x0000) |
| #define | TIM_ICPSC_DIV2 ((uint16_t)0x0004) |
| #define | TIM_ICPSC_DIV4 ((uint16_t)0x0008) |
| #define | TIM_ICPSC_DIV8 ((uint16_t)0x000C) |
| #define | TIM_ICSelection_DirectTI ((uint16_t)0x0001) |
| #define | TIM_ICSelection_IndirectTI ((uint16_t)0x0002) |
| #define | TIM_ICSelection_TRC ((uint16_t)0x0003) |
| #define | TIM_IT_Break ((uint16_t)0x0080) |
| #define | TIM_IT_CC1 ((uint16_t)0x0002) |
| #define | TIM_IT_CC2 ((uint16_t)0x0004) |
| #define | TIM_IT_CC3 ((uint16_t)0x0008) |
| #define | TIM_IT_CC4 ((uint16_t)0x0010) |
| #define | TIM_IT_COM ((uint16_t)0x0020) |
| #define | TIM_IT_Trigger ((uint16_t)0x0040) |
| #define | TIM_IT_Update ((uint16_t)0x0001) |
| #define | TIM_LOCKLevel_1 ((uint16_t)0x0100) |
| #define | TIM_LOCKLevel_2 ((uint16_t)0x0200) |
| #define | TIM_LOCKLevel_3 ((uint16_t)0x0300) |
| #define | TIM_LOCKLevel_OFF ((uint16_t)0x0000) |
| #define | TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) |
| #define | TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) |
| #define | TIM_OCClear_Disable ((uint16_t)0x0000) |
| #define | TIM_OCClear_Enable ((uint16_t)0x0080) |
| #define | TIM_OCFast_Disable ((uint16_t)0x0000) |
| #define | TIM_OCFast_Enable ((uint16_t)0x0004) |
| #define | TIM_OCIdleState_Reset ((uint16_t)0x0000) |
| #define | TIM_OCIdleState_Set ((uint16_t)0x0100) |
| #define | TIM_OCMode_Active ((uint32_t)0x00010) |
| #define | TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060) |
| #define | TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070) |
| #define | TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040) |
| #define | TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050) |
| #define | TIM_OCMode_Inactive ((uint32_t)0x00020) |
| #define | TIM_OCMode_PWM1 ((uint32_t)0x00060) |
| #define | TIM_OCMode_PWM2 ((uint32_t)0x00070) |
| #define | TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000) |
| #define | TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010) |
| #define | TIM_OCMode_Timing ((uint32_t)0x00000) |
| #define | TIM_OCMode_Toggle ((uint32_t)0x00030) |
| #define | TIM_OCNIdleState_Reset ((uint16_t)0x0000) |
| #define | TIM_OCNIdleState_Set ((uint16_t)0x0200) |
| #define | TIM_OCNPolarity_High ((uint16_t)0x0000) |
| #define | TIM_OCNPolarity_Low ((uint16_t)0x0008) |
| #define | TIM_OCPolarity_High ((uint16_t)0x0000) |
| #define | TIM_OCPolarity_Low ((uint16_t)0x0002) |
| #define | TIM_OCPreload_Disable ((uint16_t)0x0000) |
| #define | TIM_OCPreload_Enable ((uint16_t)0x0008) |
| #define | TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) |
| #define | TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) |
| #define | TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) |
| #define | TIM_OPMode_Repetitive ((uint16_t)0x0000) |
| #define | TIM_OPMode_Single ((uint16_t)0x0008) |
| #define | TIM_OSSIState_Disable ((uint16_t)0x0000) |
| #define | TIM_OSSIState_Enable ((uint16_t)0x0400) |
| #define | TIM_OSSRState_Disable ((uint16_t)0x0000) |
| #define | TIM_OSSRState_Enable ((uint16_t)0x0800) |
| #define | TIM_OutputNState_Disable ((uint16_t)0x0000) |
| #define | TIM_OutputNState_Enable ((uint16_t)0x0004) |
| #define | TIM_OutputState_Disable ((uint16_t)0x0000) |
| #define | TIM_OutputState_Enable ((uint16_t)0x0001) |
| #define | TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) |
| #define | TIM_PSCReloadMode_Update ((uint16_t)0x0000) |
| #define | TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000) |
| #define | TIM_SlaveMode_External1 ((uint32_t)0x00007) |
| #define | TIM_SlaveMode_Gated ((uint32_t)0x00005) |
| #define | TIM_SlaveMode_Reset ((uint32_t)0x00004) |
| #define | TIM_SlaveMode_Trigger ((uint32_t)0x00006) |
| #define | TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) |
| #define | TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) |
| #define | TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) |
| #define | TIM_TRGO2Source_Enable ((uint32_t)0x00100000) |
| #define | TIM_TRGO2Source_OC1 ((uint32_t)0x00300000) |
| #define | TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000) |
| #define | TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000) |
| #define | TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000) |
| #define | TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000) |
| #define | TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000) |
| #define | TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000) |
| #define | TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000) |
| #define | TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000) |
| #define | TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000) |
| #define | TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000) |
| #define | TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000) |
| #define | TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000) |
| #define | TIM_TRGO2Source_Reset ((uint32_t)0x00000000) |
| #define | TIM_TRGO2Source_Update ((uint32_t)0x00200000) |
| #define | TIM_TRGOSource_Enable ((uint16_t)0x0010) |
| #define | TIM_TRGOSource_OC1 ((uint16_t)0x0030) |
| #define | TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) |
| #define | TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) |
| #define | TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) |
| #define | TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) |
| #define | TIM_TRGOSource_Reset ((uint16_t)0x0000) |
| #define | TIM_TRGOSource_Update ((uint16_t)0x0020) |
| #define | TIM_TS_ETRF ((uint16_t)0x0070) |
| #define | TIM_TS_ITR0 ((uint16_t)0x0000) |
| #define | TIM_TS_ITR1 ((uint16_t)0x0010) |
| #define | TIM_TS_ITR2 ((uint16_t)0x0020) |
| #define | TIM_TS_ITR3 ((uint16_t)0x0030) |
| #define | TIM_TS_TI1F_ED ((uint16_t)0x0040) |
| #define | TIM_TS_TI1FP1 ((uint16_t)0x0050) |
| #define | TIM_TS_TI2FP2 ((uint16_t)0x0060) |
| #define | TIM_UpdateSource_Global ((uint16_t)0x0000) |
| #define | TIM_UpdateSource_Regular ((uint16_t)0x0001) |
Functions | |
| void | TIM_ARRPreloadConfig (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Enables or disables TIMx peripheral Preload register on ARR. More... | |
| void | TIM_BDTRConfig (TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) |
| Configures the Break feature, dead time, Lock level, OSSI/OSSR State and the AOE(automatic output enable). More... | |
| void | TIM_BDTRStructInit (TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) |
| Fills each TIM_BDTRInitStruct member with its default value. More... | |
| void | TIM_Break1Cmd (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Enables or disables the TIM Break1 input. More... | |
| void | TIM_Break1Config (TIM_TypeDef *TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter) |
| Configures the Break1 feature. More... | |
| void | TIM_Break2Cmd (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Enables or disables the TIM Break2 input. More... | |
| void | TIM_Break2Config (TIM_TypeDef *TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter) |
| Configures the Break2 feature. More... | |
| void | TIM_CCPreloadControl (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Sets or Resets the TIM peripheral Capture Compare Preload Control bit. More... | |
| void | TIM_CCxCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) |
| Enables or disables the TIM Capture Compare Channel x. More... | |
| void | TIM_CCxNCmd (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) |
| Enables or disables the TIM Capture Compare Channel xN. More... | |
| void | TIM_ClearFlag (TIM_TypeDef *TIMx, uint16_t TIM_FLAG) |
| Clears the TIMx's pending flags. More... | |
| void | TIM_ClearITPendingBit (TIM_TypeDef *TIMx, uint16_t TIM_IT) |
| Clears the TIMx's interrupt pending bits. More... | |
| void | TIM_ClearOC1Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear) |
| Clears or safeguards the OCREF1 signal on an external event. More... | |
| void | TIM_ClearOC2Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear) |
| Clears or safeguards the OCREF2 signal on an external event. More... | |
| void | TIM_ClearOC3Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear) |
| Clears or safeguards the OCREF3 signal on an external event. More... | |
| void | TIM_ClearOC4Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear) |
| Clears or safeguards the OCREF4 signal on an external event. More... | |
| void | TIM_ClearOC5Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear) |
| Clears or safeguards the OCREF5 signal on an external event. More... | |
| void | TIM_ClearOC6Ref (TIM_TypeDef *TIMx, uint16_t TIM_OCClear) |
| Clears or safeguards the OCREF6 signal on an external event. More... | |
| void | TIM_Cmd (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Enables or disables the specified TIM peripheral. More... | |
| void | TIM_CounterModeConfig (TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) |
| Specifies the TIMx Counter Mode to be used. More... | |
| void | TIM_CtrlPWMOutputs (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Enables or disables the TIM peripheral Main Outputs. More... | |
| void | TIM_DeInit (TIM_TypeDef *TIMx) |
| Deinitializes the TIMx peripheral registers to their default reset values. More... | |
| void | TIM_DMACmd (TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) |
| Enables or disables the TIMx's DMA Requests. More... | |
| void | TIM_DMAConfig (TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) |
| Configures the TIMx's DMA interface. More... | |
| void | TIM_EncoderInterfaceConfig (TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) |
| Configures the TIMx Encoder Interface. More... | |
| void | TIM_ETRClockMode1Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) |
| Configures the External clock Mode1. More... | |
| void | TIM_ETRClockMode2Config (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) |
| Configures the External clock Mode2. More... | |
| void | TIM_ETRConfig (TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) |
| Configures the TIMx External Trigger (ETR). More... | |
| void | TIM_ForcedOC1Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) |
| Forces the TIMx output 1 waveform to active or inactive level. More... | |
| void | TIM_ForcedOC2Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) |
| Forces the TIMx output 2 waveform to active or inactive level. More... | |
| void | TIM_ForcedOC3Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) |
| Forces the TIMx output 3 waveform to active or inactive level. More... | |
| void | TIM_ForcedOC4Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) |
| Forces the TIMx output 4 waveform to active or inactive level. More... | |
| void | TIM_ForcedOC5Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) |
| Forces the TIMx output 5 waveform to active or inactive level. More... | |
| void | TIM_ForcedOC6Config (TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) |
| Forces the TIMx output 6 waveform to active or inactive level. More... | |
| void | TIM_GenerateEvent (TIM_TypeDef *TIMx, uint16_t TIM_EventSource) |
| Configures the TIMx event to be generate by software. More... | |
| uint32_t | TIM_GetCapture1 (TIM_TypeDef *TIMx) |
| Gets the TIMx Input Capture 1 value. More... | |
| uint32_t | TIM_GetCapture2 (TIM_TypeDef *TIMx) |
| Gets the TIMx Input Capture 2 value. More... | |
| uint32_t | TIM_GetCapture3 (TIM_TypeDef *TIMx) |
| Gets the TIMx Input Capture 3 value. More... | |
| uint32_t | TIM_GetCapture4 (TIM_TypeDef *TIMx) |
| Gets the TIMx Input Capture 4 value. More... | |
| uint32_t | TIM_GetCounter (TIM_TypeDef *TIMx) |
| Gets the TIMx Counter value. More... | |
| FlagStatus | TIM_GetFlagStatus (TIM_TypeDef *TIMx, uint32_t TIM_FLAG) |
| Checks whether the specified TIM flag is set or not. More... | |
| ITStatus | TIM_GetITStatus (TIM_TypeDef *TIMx, uint16_t TIM_IT) |
| Checks whether the TIM interrupt has occurred or not. More... | |
| uint16_t | TIM_GetPrescaler (TIM_TypeDef *TIMx) |
| Gets the TIMx Prescaler value. More... | |
| void | TIM_ICInit (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) |
| Initializes the TIM peripheral according to the specified parameters in the TIM_ICInitStruct. More... | |
| void | TIM_ICStructInit (TIM_ICInitTypeDef *TIM_ICInitStruct) |
| Fills each TIM_ICInitStruct member with its default value. More... | |
| void | TIM_InternalClockConfig (TIM_TypeDef *TIMx) |
| Configures the TIMx internal Clock. More... | |
| void | TIM_ITConfig (TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) |
| Enables or disables the specified TIM interrupts. More... | |
| void | TIM_ITRxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) |
| Configures the TIMx Internal Trigger as External Clock. More... | |
| void | TIM_OC1FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast) |
| Configures the TIMx Output Compare 1 Fast feature. More... | |
| void | TIM_OC1Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) |
| Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct. More... | |
| void | TIM_OC1NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) |
| Configures the TIMx Channel 1N polarity. More... | |
| void | TIM_OC1PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) |
| Configures the TIMx channel 1 polarity. More... | |
| void | TIM_OC1PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) |
| Enables or disables the TIMx peripheral Preload register on CCR1. More... | |
| void | TIM_OC2FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast) |
| Configures the TIMx Output Compare 2 Fast feature. More... | |
| void | TIM_OC2Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) |
| Initializes the TIMx Channel2 according to the specified parameters in the TIM_OCInitStruct. More... | |
| void | TIM_OC2NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) |
| Configures the TIMx Channel 2N polarity. More... | |
| void | TIM_OC2PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) |
| Configures the TIMx channel 2 polarity. More... | |
| void | TIM_OC2PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) |
| Enables or disables the TIMx peripheral Preload register on CCR2. More... | |
| void | TIM_OC3FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast) |
| Configures the TIMx Output Compare 3 Fast feature. More... | |
| void | TIM_OC3Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) |
| Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct. More... | |
| void | TIM_OC3NPolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) |
| Configures the TIMx Channel 3N polarity. More... | |
| void | TIM_OC3PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) |
| Configures the TIMx channel 3 polarity. More... | |
| void | TIM_OC3PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) |
| Enables or disables the TIMx peripheral Preload register on CCR3. More... | |
| void | TIM_OC4FastConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCFast) |
| Configures the TIMx Output Compare 4 Fast feature. More... | |
| void | TIM_OC4Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) |
| Initializes the TIMx Channel4 according to the specified parameters in the TIM_OCInitStruct. More... | |
| void | TIM_OC4PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) |
| Configures the TIMx channel 4 polarity. More... | |
| void | TIM_OC4PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) |
| Enables or disables the TIMx peripheral Preload register on CCR4. More... | |
| void | TIM_OC5Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) |
| Initializes the TIMx Channel5 according to the specified parameters in the TIM_OCInitStruct. More... | |
| void | TIM_OC5PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) |
| Configures the TIMx channel 5 polarity. More... | |
| void | TIM_OC5PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) |
| Enables or disables the TIMx peripheral Preload register on CCR5. More... | |
| void | TIM_OC6Init (TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) |
| Initializes the TIMx Channel6 according to the specified parameters in the TIM_OCInitStruct. More... | |
| void | TIM_OC6PolarityConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) |
| Configures the TIMx channel 6 polarity. More... | |
| void | TIM_OC6PreloadConfig (TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) |
| Enables or disables the TIMx peripheral Preload register on CCR6. More... | |
| void | TIM_OCStructInit (TIM_OCInitTypeDef *TIM_OCInitStruct) |
| Fills each TIM_OCInitStruct member with its default value. More... | |
| void | TIM_PrescalerConfig (TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) |
| Configures the TIMx Prescaler. More... | |
| void | TIM_PWMIConfig (TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) |
| Configures the TIM peripheral according to the specified parameters in the TIM_ICInitStruct to measure an external PWM signal. More... | |
| void | TIM_RemapConfig (TIM_TypeDef *TIMx, uint16_t TIM_Remap) |
| Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. More... | |
| void | TIM_SelectCCDMA (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Selects the TIMx peripheral Capture Compare DMA source. More... | |
| void | TIM_SelectCOM (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Selects the TIM peripheral Commutation event. More... | |
| void | TIM_SelectGC5C1 (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Selects the TIM Group Channel 5 and Channel 1, OC1REFC is the logical AND of OC1REFC and OC5REF. More... | |
| void | TIM_SelectGC5C2 (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Selects the TIM Group Channel 5 and Channel 2, OC2REFC is the logical AND of OC2REFC and OC5REF. More... | |
| void | TIM_SelectGC5C3 (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Selects the TIM Group Channel 5 and Channel 3, OC3REFC is the logical AND of OC3REFC and OC5REF. More... | |
| void | TIM_SelectHallSensor (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Enables or disables the TIMx's Hall sensor interface. More... | |
| void | TIM_SelectInputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) |
| Selects the Input Trigger source. More... | |
| void | TIM_SelectMasterSlaveMode (TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) |
| Sets or Resets the TIMx Master/Slave Mode. More... | |
| void | TIM_SelectOCREFClear (TIM_TypeDef *TIMx, uint16_t TIM_OCReferenceClear) |
| Selects the OCReference Clear source. More... | |
| void | TIM_SelectOCxM (TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode) |
| Selects the TIM Output Compare Mode. More... | |
| void | TIM_SelectOnePulseMode (TIM_TypeDef *TIMx, uint16_t TIM_OPMode) |
| Selects the TIMx's One Pulse Mode. More... | |
| void | TIM_SelectOutputTrigger (TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) |
| Selects the TIMx Trigger Output Mode. More... | |
| void | TIM_SelectOutputTrigger2 (TIM_TypeDef *TIMx, uint32_t TIM_TRGO2Source) |
| Selects the TIMx Trigger Output Mode2 (TRGO2). More... | |
| void | TIM_SelectSlaveMode (TIM_TypeDef *TIMx, uint32_t TIM_SlaveMode) |
| Selects the TIMx Slave Mode. More... | |
| void | TIM_SetAutoreload (TIM_TypeDef *TIMx, uint32_t Autoreload) |
| Sets the TIMx Autoreload Register value. More... | |
| void | TIM_SetClockDivision (TIM_TypeDef *TIMx, uint16_t TIM_CKD) |
| Sets the TIMx Clock Division value. More... | |
| void | TIM_SetCompare1 (TIM_TypeDef *TIMx, uint32_t Compare1) |
| Sets the TIMx Capture Compare1 Register value. More... | |
| void | TIM_SetCompare2 (TIM_TypeDef *TIMx, uint32_t Compare2) |
| Sets the TIMx Capture Compare2 Register value. More... | |
| void | TIM_SetCompare3 (TIM_TypeDef *TIMx, uint32_t Compare3) |
| Sets the TIMx Capture Compare3 Register value. More... | |
| void | TIM_SetCompare4 (TIM_TypeDef *TIMx, uint32_t Compare4) |
| Sets the TIMx Capture Compare4 Register value. More... | |
| void | TIM_SetCompare5 (TIM_TypeDef *TIMx, uint32_t Compare5) |
| Sets the TIMx Capture Compare5 Register value. More... | |
| void | TIM_SetCompare6 (TIM_TypeDef *TIMx, uint32_t Compare6) |
| Sets the TIMx Capture Compare6 Register value. More... | |
| void | TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter) |
| Sets the TIMx Counter Register value. More... | |
| void | TIM_SetIC1Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) |
| Sets the TIMx Input Capture 1 prescaler. More... | |
| void | TIM_SetIC2Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) |
| Sets the TIMx Input Capture 2 prescaler. More... | |
| void | TIM_SetIC3Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) |
| Sets the TIMx Input Capture 3 prescaler. More... | |
| void | TIM_SetIC4Prescaler (TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) |
| Sets the TIMx Input Capture 4 prescaler. More... | |
| void | TIM_TimeBaseInit (TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) |
| Initializes the TIMx Time Base Unit peripheral according to the specified parameters in the TIM_TimeBaseInitStruct. More... | |
| void | TIM_TimeBaseStructInit (TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) |
| Fills each TIM_TimeBaseInitStruct member with its default value. More... | |
| void | TIM_TIxExternalClockConfig (TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, uint16_t TIM_ICPolarity, uint16_t ICFilter) |
| Configures the TIMx Trigger as External Clock. More... | |
| void | TIM_UIFRemap (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Sets or resets the update interrupt flag (UIF)status bit Remapping. when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31]. More... | |
| void | TIM_UpdateDisableConfig (TIM_TypeDef *TIMx, FunctionalState NewState) |
| Enables or Disables the TIMx Update event. More... | |
| void | TIM_UpdateRequestConfig (TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) |
| Configures the TIMx Update Request Interrupt source. More... | |
Detailed Description
This file contains all the functions prototypes for the TIM firmware library.
- Version
- V1.1.1
- Date
- 04-April-2014
- Attention
© COPYRIGHT 2014 STMicroelectronics
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:
http://www.st.com/software_license_agreement_liberty_v2
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
Definition in file stm32f30x_tim.h.