This file contains all the functions prototypes for the HRTIM firmware library. More...
#include "stm32f30x.h"
Go to the source code of this file.
Classes | |
struct | HRTIM_ADCTriggerCfgTypeDef |
ADC trigger configuration definition. More... | |
struct | HRTIM_BaseInitTypeDef |
HRTIM Configuration Structure definition - Time base related parameters. More... | |
struct | HRTIM_BasicCaptureChannelCfgTypeDef |
Basic capture mode configuration definition. More... | |
struct | HRTIM_BasicOCChannelCfgTypeDef |
Basic output compare mode configuration definition. More... | |
struct | HRTIM_BasicOnePulseChannelCfgTypeDef |
Basic One Pulse mode configuration definition. More... | |
struct | HRTIM_BasicPWMChannelCfgTypeDef |
Basic PWM output mode configuration definition. More... | |
struct | HRTIM_BurstModeCfgTypeDef |
Burst mode configuration definition. More... | |
struct | HRTIM_CaptureCfgTypeDef |
Capture unit configuration definition. More... | |
struct | HRTIM_ChopperModeCfgTypeDef |
Chopper mode configuration definition. More... | |
struct | HRTIM_CompareCfgTypeDef |
Compare unit configuration definition. More... | |
struct | HRTIM_DeadTimeCfgTypeDef |
Dead time feature configuration definition. More... | |
struct | HRTIM_EventCfgTypeDef |
External event channel configuration definition. More... | |
struct | HRTIM_FaultCfgTypeDef |
Fault channel configuration definition. More... | |
struct | HRTIM_OutputCfgTypeDef |
Output configuration definition. More... | |
struct | HRTIM_SynchroCfgTypeDef |
Master synchronization configuration definition. More... | |
struct | HRTIM_TimerCfgTypeDef |
Timer configuration definition. More... | |
struct | HRTIM_TimerEventFilteringCfgTypeDef |
External event filtering in timing units configuration definition. More... | |
struct | HRTIM_TimerInitTypeDef |
Waveform mode initialization parameters definition. More... | |
Macros | |
#define | __HRTIM_DISABLE(__HANDLE__, __TIMERS__) |
#define | __HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->HRTIM_MASTER.MCR |= (__TIMERS__)) |
Enables or disables the timer counter(s) More... | |
#define | HRIM_BURSTMODEPRELOAD_DISABLED ((uint32_t)0x00000000) |
#define | HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) |
#define | HRTIM_ADCTRIGGER_1 (uint32_t)0x00000001 |
#define | HRTIM_ADCTRIGGER_2 (uint32_t)0x00000002 |
#define | HRTIM_ADCTRIGGER_3 (uint32_t)0x00000004 |
#define | HRTIM_ADCTRIGGER_4 (uint32_t)0x00000008 |
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) |
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) |
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) |
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) |
#define | HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) |
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) |
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) |
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) |
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) |
#define | HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) |
#define | HRTIM_ADCTRIGGEREVENT13_NONE (uint32_t)0x00000000 |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) |
#define | HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) |
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) |
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) |
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) |
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) |
#define | HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) |
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) |
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) |
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) |
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) |
#define | HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) |
#define | HRTIM_ADCTRIGGEREVENT24_NONE (uint32_t)0x00000000 |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) |
#define | HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) |
#define | HRTIM_ADCTRIGGERUPDATE_MASTER (uint32_t)0x00000000 |
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) |
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) |
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) |
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) |
#define | HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) |
#define | HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) |
#define | HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) |
#define | HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) |
#define | HRTIM_AUTODELAYEDMODE_REGULAR ((uint32_t)0x00000000) |
#define | HRTIM_BASICOCMODE_ACTIVE ((uint32_t)0x00000003) |
#define | HRTIM_BASICOCMODE_INACTIVE ((uint32_t)0x00000002) |
#define | HRTIM_BASICOCMODE_TOGGLE ((uint32_t)0x00000001) |
#define | HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) |
#define | HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) |
#define | HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) |
#define | HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) |
#define | HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) |
#define | HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) |
#define | HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) |
#define | HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) |
#define | HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) |
#define | HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) |
#define | HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) |
#define | HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) |
#define | HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) |
#define | HRTIM_BURSTDMA_NONE (uint32_t)0x00000000 |
#define | HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) |
#define | HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) |
#define | HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) |
#define | HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) |
#define | HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) |
#define | HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) |
#define | HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) |
#define | HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) |
#define | HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) |
#define | HRTIM_BURSTMODE_SINGLESHOT ((uint32_t)0x00000000) |
#define | HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) |
#define | HRTIM_BURSTMODECLOCKSOURCE_MASTER ((uint32_t)0x00000000) |
#define | HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_1 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) |
#define | HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_2 (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) |
#define | HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_3 (HRTIM_BMCR_BMCLK_3) |
#define | HRTIM_BURSTMODECLOCKSOURCE_ONCHIPEV_4 (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_0) |
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) |
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) |
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) |
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) |
#define | HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) |
#define | HRTIM_BURSTMODECTL_DISABLED (uint32_t)0x00000000 |
#define | HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) |
#define | HRTIM_BURSTMODEPRESCALER_DIV1 ((uint32_t)0x00000000) |
#define | HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1) |
#define | HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) |
#define | HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPSC_2) |
#define | HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) |
#define | HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPSC_0) |
#define | HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) |
#define | HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPSC_3) |
#define | HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) |
#define | HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) |
#define | HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPSC_1) |
#define | HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2) |
#define | HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_0) |
#define | HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_1) |
#define | HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPSC_1 | HRTIM_BMCR_BMPSC_0) |
#define | HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPSC_3 | HRTIM_BMCR_BMPSC_2 | HRTIM_BMCR_BMPSC_0) |
#define | HRTIM_BURSTMODESTATUS_NORMAL (uint32_t) 0x00000000 |
#define | HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) |
#define | HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) |
#define | HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) |
#define | HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) |
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) |
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) |
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) |
#define | HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) |
#define | HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) |
#define | HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) |
#define | HRTIM_BURSTMODETRIGGER_NONE (uint32_t)0x00000000 |
#define | HRTIM_BURSTMODETRIGGER_SOFTWARE (HRTIM_BMTRGR_SW) |
#define | HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) |
#define | HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) |
#define | HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) |
#define | HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) |
#define | HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) |
#define | HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) |
#define | HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) |
#define | HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) |
#define | HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) |
#define | HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) |
#define | HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) |
#define | HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) |
#define | HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) |
#define | HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) |
#define | HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) |
#define | HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) |
#define | HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) |
#define | HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) |
#define | HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) |
#define | HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) |
#define | HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) |
#define | HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) |
#define | HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) |
#define | HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) |
#define | HRTIM_CALIBRATIONRATE_7300 (uint32_t)0x00000000 |
#define | HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) |
#define | HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) |
#define | HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) |
#define | HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) |
#define | HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) |
#define | HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) |
#define | HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) |
#define | HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) |
#define | HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) |
#define | HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) |
#define | HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) |
#define | HRTIM_CAPTURETRIGGER_NONE (uint32_t)0x00000000 |
#define | HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) |
#define | HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) |
#define | HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) |
#define | HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) |
#define | HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) |
#define | HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) |
#define | HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) |
#define | HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) |
#define | HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) |
#define | HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) |
#define | HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TA1CMP1) |
#define | HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TA1CMP2) |
#define | HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TB1CMP1) |
#define | HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TB1CMP2) |
#define | HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TC1CMP1) |
#define | HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TC1CMP2) |
#define | HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TD1CMP1) |
#define | HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TD1CMP2) |
#define | HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TE1CMP1) |
#define | HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TE1CMP2) |
#define | HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) |
#define | HRTIM_CAPTUREUNIT_1 (uint32_t)0x00000001 |
#define | HRTIM_CAPTUREUNIT_2 (uint32_t)0x00000002 |
#define | HRTIM_COMMONINDEX (uint32_t)0x6 |
#define | HRTIM_COMPAREUNIT_1 (uint32_t)0x00000001 |
#define | HRTIM_COMPAREUNIT_2 (uint32_t)0x00000002 |
#define | HRTIM_COMPAREUNIT_3 (uint32_t)0x00000004 |
#define | HRTIM_COMPAREUNIT_4 (uint32_t)0x00000008 |
#define | HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) |
#define | HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) |
#define | HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) |
#define | HRTIM_DACSYNC_NONE (uint32_t)0x00000000 |
#define | HRTIM_EVENT_1 ((uint32_t)0x00000001) |
#define | HRTIM_EVENT_10 ((uint32_t)0x00000200) |
#define | HRTIM_EVENT_2 ((uint32_t)0x00000002) |
#define | HRTIM_EVENT_3 ((uint32_t)0x00000004) |
#define | HRTIM_EVENT_4 ((uint32_t)0x00000008) |
#define | HRTIM_EVENT_5 ((uint32_t)0x00000010) |
#define | HRTIM_EVENT_6 ((uint32_t)0x00000020) |
#define | HRTIM_EVENT_7 ((uint32_t)0x00000040) |
#define | HRTIM_EVENT_8 ((uint32_t)0x00000080) |
#define | HRTIM_EVENT_9 ((uint32_t)0x00000100) |
#define | HRTIM_EVENT_NONE ((uint32_t)0x00000000) |
#define | HRTIM_EVENTFASTMODE_DISABLE ((uint32_t)0x00000000) |
#define | HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) |
#define | HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) |
#define | HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) |
#define | HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) |
#define | HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) |
#define | HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) |
#define | HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) |
#define | HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) |
#define | HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) |
#define | HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) |
#define | HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) |
#define | HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) |
#define | HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) |
#define | HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) |
#define | HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) |
#define | HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) |
#define | HRTIM_EVENTFILTER_NONE ((uint32_t)0x00000000) |
#define | HRTIM_EVENTPOLARITY_HIGH ((uint32_t)0x00000000) |
#define | HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) |
#define | HRTIM_EVENTPRESCALER_DIV1 ((uint32_t)0x00000000) |
#define | HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) |
#define | HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) |
#define | HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) |
#define | HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) |
#define | HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) |
#define | HRTIM_EVENTSENSITIVITY_LEVEL ((uint32_t)0x00000000) |
#define | HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) |
#define | HRTIM_EVENTSRC_1 ((uint32_t)0x00000000) |
#define | HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) |
#define | HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) |
#define | HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) |
#define | HRTIM_FAULT_1 ((uint32_t)0x01) |
#define | HRTIM_FAULT_2 ((uint32_t)0x02) |
#define | HRTIM_FAULT_3 ((uint32_t)0x04) |
#define | HRTIM_FAULT_4 ((uint32_t)0x08) |
#define | HRTIM_FAULT_5 ((uint32_t)0x10) |
#define | HRTIM_FAULT_DISABLED (uint32_t)0x00000000 |
#define | HRTIM_FAULT_ENABLED (HRTIM_FLTINR1_FLT1E) |
#define | HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) |
#define | HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) |
#define | HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) |
#define | HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) |
#define | HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) |
#define | HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) |
#define | HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) |
#define | HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) |
#define | HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) |
#define | HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) |
#define | HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) |
#define | HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) |
#define | HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) |
#define | HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) |
#define | HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) |
#define | HRTIM_FAULTFILTER_NONE ((uint32_t)0x00000000) |
#define | HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) |
#define | HRTIM_FAULTLOCK_READWRITE ((uint32_t)0x00000000) |
#define | HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) |
#define | HRTIM_FAULTPOLARITY_LOW ((uint32_t)0x00000000) |
#define | HRTIM_FAULTPRESCALER_DIV1 ((uint32_t)0x00000000) |
#define | HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) |
#define | HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) |
#define | HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) |
#define | HRTIM_FAULTSOURCE_DIGITALINPUT ((uint32_t)0x00000000) |
#define | HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) |
#define | HRTIM_FLAG_BMPER HRTIM_ISR_BMPER |
#define | HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY |
#define | HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 |
#define | HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 |
#define | HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 |
#define | HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 |
#define | HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 |
#define | HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT |
#define | HRTIM_HALFMODE_DISABLED ((uint32_t)0x00000000) |
#define | HRTIM_HALFMODE_ENABLED ((uint32_t)0x00000020) |
#define | HRTIM_IT_BMPER HRTIM_ISR_BMPER |
#define | HRTIM_IT_DLLRDY HRTIM_ISR_DLLRDY |
#define | HRTIM_IT_FLT1 HRTIM_ISR_FLT1 |
#define | HRTIM_IT_FLT2 HRTIM_ISR_FLT2 |
#define | HRTIM_IT_FLT3 HRTIM_ISR_FLT3 |
#define | HRTIM_IT_FLT4 HRTIM_ISR_FLT4 |
#define | HRTIM_IT_FLT5 HRTIM_ISR_FLT5 |
#define | HRTIM_IT_SYSFLT HRTIM_ISR_SYSFLT |
#define | HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE |
#define | HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE |
#define | HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE |
#define | HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE |
#define | HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE |
#define | HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE |
#define | HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE |
#define | HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 |
#define | HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 |
#define | HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 |
#define | HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 |
#define | HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP |
#define | HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD |
#define | HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC |
#define | HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE |
#define | HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE |
#define | HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE |
#define | HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE |
#define | HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE |
#define | HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE |
#define | HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE |
#define | HRTIM_MODE_CONTINOUS ((uint32_t)0x00000008) |
#define | HRTIM_MODE_SINGLESHOT ((uint32_t)0x00000000) |
#define | HRTIM_MODE_SINGLESHOT_RETRIGGERABLE ((uint32_t)0x00000010) |
#define | HRTIM_OUTPUT_TA1 (uint32_t)0x00000001 |
#define | HRTIM_OUTPUT_TA2 (uint32_t)0x00000002 |
#define | HRTIM_OUTPUT_TB1 (uint32_t)0x00000004 |
#define | HRTIM_OUTPUT_TB2 (uint32_t)0x00000008 |
#define | HRTIM_OUTPUT_TC1 (uint32_t)0x00000010 |
#define | HRTIM_OUTPUT_TC2 (uint32_t)0x00000020 |
#define | HRTIM_OUTPUT_TD1 (uint32_t)0x00000040 |
#define | HRTIM_OUTPUT_TD2 (uint32_t)0x00000080 |
#define | HRTIM_OUTPUT_TE1 (uint32_t)0x00000100 |
#define | HRTIM_OUTPUT_TE2 (uint32_t)0x00000200 |
#define | HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) |
#define | HRTIM_OUTPUTBURSTMODEENTRY_REGULAR (uint32_t)0x00000000 |
#define | HRTIM_OUTPUTCHOPPERMODE_DISABLED (uint32_t)0x00000000 |
#define | HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) |
#define | HRTIM_OUTPUTFAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) |
#define | HRTIM_OUTPUTFAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) |
#define | HRTIM_OUTPUTFAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) |
#define | HRTIM_OUTPUTFAULTSTATE_NONE (uint32_t)0x00000000 |
#define | HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) |
#define | HRTIM_OUTPUTIDLEMODE_NONE (uint32_t)0x00000000 |
#define | HRTIM_OUTPUTIDLESTATE_ACTIVE (HRTIM_OUTR_IDLES1) |
#define | HRTIM_OUTPUTIDLESTATE_INACTIVE (uint32_t)0x00000000 |
#define | HRTIM_OUTPUTLEVEL_ACTIVE (uint32_t)0x00000001 |
#define | HRTIM_OUTPUTLEVEL_INACTIVE (uint32_t)0x00000002 |
#define | HRTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) |
#define | HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) |
#define | HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) |
#define | HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) |
#define | HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) |
#define | HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) |
#define | HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) |
#define | HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) |
#define | HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) |
#define | HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) |
#define | HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) |
#define | HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) |
#define | HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) |
#define | HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) |
#define | HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) |
#define | HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) |
#define | HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) |
#define | HRTIM_OUTPUTRESET_NONE (uint32_t)0x00000000 |
#define | HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) |
#define | HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) |
#define | HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) |
#define | HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) |
#define | HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) |
#define | HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) |
#define | HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) |
#define | HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) |
#define | HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) |
#define | HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) |
#define | HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) |
#define | HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) |
#define | HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) |
#define | HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) |
#define | HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) |
#define | HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) |
#define | HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) |
#define | HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) |
#define | HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) |
#define | HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) |
#define | HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) |
#define | HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) |
#define | HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) |
#define | HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) |
#define | HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) |
#define | HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) |
#define | HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) |
#define | HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) |
#define | HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) |
#define | HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) |
#define | HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) |
#define | HRTIM_OUTPUTSET_NONE (uint32_t)0x00000000 |
#define | HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) |
#define | HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) |
#define | HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) |
#define | HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) |
#define | HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) |
#define | HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) |
#define | HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) |
#define | HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) |
#define | HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) |
#define | HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) |
#define | HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) |
#define | HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) |
#define | HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) |
#define | HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) |
#define | HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) |
#define | HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) |
#define | HRTIM_OUTPUTSTATE_FAULT (uint32_t)0x00000003 |
#define | HRTIM_OUTPUTSTATE_IDLE (uint32_t)0x00000001 |
#define | HRTIM_OUTPUTSTATE_RUN (uint32_t)0x00000002 |
#define | HRTIM_PRELOAD_DISABLED ((uint32_t)0x00000000) |
#define | HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) |
#define | HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005) |
#define | HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006) |
#define | HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007) |
#define | HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001) |
#define | HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004) |
#define | HRTIM_PRESCALERRATIO_MUL32 ((uint32_t)0x00000000) |
#define | HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003) |
#define | HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002) |
#define | HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 (uint32_t) 0x00000000 |
#define | HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) |
#define | HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 (uint32_t) 0x00000000 |
#define | HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) |
#define | HRTIM_SINGLE_CALIBRATION (uint32_t)0xFFFFFFFF |
#define | HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) |
#define | HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 |
#define | HRTIM_SYNCINPUTSOURCE_NONE (uint32_t)0x00000000 |
#define | HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) |
#define | HRTIM_SYNCOUTPUTPOLARITY_NONE (uint32_t)0x00000000 |
#define | HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_0) |
#define | HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) |
#define | HRTIM_SYNCOUTPUTSOURCE_MASTER_START (uint32_t)0x00000000 |
#define | HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) |
#define | HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) |
#define | HRTIM_SYNCRESET_DISABLED ((uint32_t)0x00000000) |
#define | HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) |
#define | HRTIM_SYNCSTART_DISABLED ((uint32_t)0x00000000) |
#define | HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) |
#define | HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN) |
#define | HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN) |
#define | HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN) |
#define | HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN) |
#define | HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN) |
#define | HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE |
#define | HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE |
#define | HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE |
#define | HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE |
#define | HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE |
#define | HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE |
#define | HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE |
#define | HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE |
#define | HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE |
#define | HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE |
#define | HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE |
#define | HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE |
#define | HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE |
#define | HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE |
#define | HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 |
#define | HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 |
#define | HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 |
#define | HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 |
#define | HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 |
#define | HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 |
#define | HRTIM_TIM_FLAG_DLYPRT1 HRTIM_TIMISR_DLYPRT |
#define | HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP |
#define | HRTIM_TIM_FLAG_RST HRTIM_TIMDIER_RSTIE |
#define | HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 |
#define | HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 |
#define | HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 |
#define | HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 |
#define | HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD |
#define | HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE |
#define | HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE |
#define | HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE |
#define | HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE |
#define | HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE |
#define | HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE |
#define | HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE |
#define | HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE |
#define | HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE |
#define | HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE |
#define | HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE |
#define | HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE |
#define | HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE |
#define | HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE |
#define | HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) |
#define | HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE ((uint32_t)0x00000000) |
#define | HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) |
#define | HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE ((uint32_t)0x00000000) |
#define | HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) |
#define | HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE ((uint32_t)0x00000000) |
#define | HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) |
#define | HRTIM_TIMDEADTIME_RISINGLOCK_WRITE ((uint32_t)0x00000000) |
#define | HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) |
#define | HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE ((uint32_t)0x00000000) |
#define | HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) |
#define | HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE ((uint32_t)0x00000000) |
#define | HRTIM_TIMDEADTIMEINSERTION_DISABLED ((uint32_t)0x00000000) |
#define | HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN |
#define | HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) |
#define | HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) |
#define | HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) |
#define | HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) |
#define | HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) |
#define | HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 (HRTIM_OUTR_DLYPRTEN) |
#define | HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) |
#define | HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) |
#define | HRTIM_TIMDELAYEDPROTECTION_DISABLED ((uint32_t)0x00000000) |
#define | HRTIM_TIMERBURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 |
#define | HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) |
#define | HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) |
#define | HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) |
#define | HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) |
#define | HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) |
#define | HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) |
#define | HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) |
#define | HRTIM_TIMERINDEX_MASTER (uint32_t)0x5 |
#define | HRTIM_TIMERINDEX_TIMER_A (uint32_t)0x0 |
#define | HRTIM_TIMERINDEX_TIMER_B (uint32_t)0x1 |
#define | HRTIM_TIMERINDEX_TIMER_C (uint32_t)0x2 |
#define | HRTIM_TIMERINDEX_TIMER_D (uint32_t)0x3 |
#define | HRTIM_TIMERINDEX_TIMER_E (uint32_t)0x4 |
#define | HRTIM_TIMERRESET_A (HRTIM_CR2_TARST) |
#define | HRTIM_TIMERRESET_B (HRTIM_CR2_TBRST) |
#define | HRTIM_TIMERRESET_C (HRTIM_CR2_TCRST) |
#define | HRTIM_TIMERRESET_D (HRTIM_CR2_TDRST) |
#define | HRTIM_TIMERRESET_E (HRTIM_CR2_TERST) |
#define | HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) |
#define | HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) |
#define | HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) |
#define | HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) |
#define | HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) |
#define | HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) |
#define | HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) |
#define | HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) |
#define | HRTIM_TIMEVENTFILTER_NONE (0x00000000) |
#define | HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) |
#define | HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) |
#define | HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) |
#define | HRTIM_TIMEVENTLATCH_DISABLED ((uint32_t)0x00000000) |
#define | HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event 1 is latched and delayed till the end of the blanking or windowing period */ |
#define | HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) |
#define | HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) |
#define | HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) |
#define | HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) |
#define | HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) |
#define | HRTIM_TIMFAULTENABLE_NONE (uint32_t)0x00000000 |
#define | HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTCLK) |
#define | HRTIM_TIMFAULTLOCK_READWRITE ((uint32_t)0x00000000) |
#define | HRTIM_TIMPUSHPULLMODE_DISABLED ((uint32_t)0x00000000) |
#define | HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) |
#define | HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) |
#define | HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) |
#define | HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) |
#define | HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) |
#define | HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) |
#define | HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) |
#define | HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) |
#define | HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) |
#define | HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) |
#define | HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) |
#define | HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) |
#define | HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) |
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) |
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) |
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) |
#define | HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) |
#define | HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) |
#define | HRTIM_TIMRESETTRIGGER_NONE (uint32_t)0x00000000 |
#define | HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) |
#define | HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) |
#define | HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) |
#define | HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) |
#define | HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) |
#define | HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) |
#define | HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) |
#define | HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) |
#define | HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) |
#define | HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) |
#define | HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) |
#define | HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) |
#define | HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) |
#define | HRTIM_TIMUPDATEONRESET_DISABLED (uint32_t)0x00000000 |
#define | HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) |
#define | HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) |
#define | HRTIM_TIMUPDATETRIGGER_NONE (uint32_t)0x00000000 |
#define | HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) |
#define | HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) |
#define | HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) |
#define | HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) |
#define | HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) |
#define | HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) |
#define | HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) |
#define | HRTIM_UPDATEGATING_INDEPENDENT (uint32_t)0x00000000 |
#define | HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) |
#define | HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) |
#define | HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) |
#define | HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) |
#define | HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) |
#define | HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) |
#define | HRTIM_UPDATEONREPETITION_DISABLED (uint32_t)0x00000000 |
#define | HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) |
#define | IS_HRTIM_ADCTRIGGER(ADCTRIGGER) |
#define | IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE) |
#define | IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE) |
#define | IS_HRTIM_BASICOCMODE(BASICOCMODE) |
#define | IS_HRTIM_BURSTMODE(BURSTMODE) |
#define | IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE) |
#define | IS_HRTIM_BURSTMODECTL(BURSTMODECTL) |
#define | IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD) |
#define | IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER) |
#define | IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE) |
#define | IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT) |
#define | IS_HRTIM_COMPAREUNIT(COMPAREUNIT) |
#define | IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) |
#define | IS_HRTIM_DACSYNC(DACSYNC) |
#define | IS_HRTIM_EVENT(EVENT) |
#define | IS_HRTIM_EVENTFASTMODE(EVENTFASTMODE) |
#define | IS_HRTIM_EVENTFILTER(EVENTFILTER) |
#define | IS_HRTIM_EVENTPOLARITY(EVENTPOLARITY) |
#define | IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER) |
#define | IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY) |
#define | IS_HRTIM_EVENTSRC(EVENTSRC) |
#define | IS_HRTIM_FASTMODE_AVAILABLE(EVENT) |
#define | IS_HRTIM_FAULT(FAULT) |
#define | IS_HRTIM_FAULTCTL(FAULTCTL) |
#define | IS_HRTIM_FAULTFILTER(FAULTFILTER) |
#define | IS_HRTIM_FAULTLOCK(FAULTLOCK) |
#define | IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY) |
#define | IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER) |
#define | IS_HRTIM_FAULTSOURCE(FAULTSOURCE) |
#define | IS_HRTIM_FLAG(FLAG) |
#define | IS_HRTIM_HALFMODE(HALFMODE) |
#define | IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER) |
#define | IS_HRTIM_INSTANCE(INSTANCE) (INSTANCE) == HRTIM1) |
#define | IS_HRTIM_IT(IT) |
#define | IS_HRTIM_MASTER_DMA(DMA) |
#define | IS_HRTIM_MASTER_FLAG(FLAG) |
#define | IS_HRTIM_MASTER_IT(IT) |
#define | IS_HRTIM_MODE(MODE) |
#define | IS_HRTIM_MODE_ONEPULSE(MODE) |
#define | IS_HRTIM_OUTPUT(OUTPUT) |
#define | IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY) |
#define | IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE) |
#define | IS_HRTIM_OUTPUTFAULTSTATE(OUTPUTFAULTSTATE) |
#define | IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE) |
#define | IS_HRTIM_OUTPUTIDLESTATE(OUTPUTIDLESTATE) |
#define | IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL) |
#define | IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY) |
#define | IS_HRTIM_OUTPUTRESET(OUTPUTRESET) |
#define | IS_HRTIM_OUTPUTSET(OUTPUTSET) |
#define | IS_HRTIM_PRELOAD(PRELOAD) |
#define | IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO) |
#define | IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE) |
#define | IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY) |
#define | IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE) |
#define | IS_HRTIM_SYNCRESET(SYNCRESET) |
#define | IS_HRTIM_SYNCSTART(SYNCSTART) |
#define | IS_HRTIM_TIM_DMA(DMA) |
#define | IS_HRTIM_TIM_FLAG(FLAG) |
#define | IS_HRTIM_TIM_IT(IT) |
#define | IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK) |
#define | IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN) |
#define | IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK) |
#define | IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK) |
#define | IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN) |
#define | IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK) |
#define | IS_HRTIM_TIMDEADTIMEINSERTION(TIMDEADTIMEINSERTION) |
#define | IS_HRTIM_TIMDELAYEDPROTECTION(TIMDELAYEDPROTECTION) |
#define | IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) |
#define | IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) |
#define | IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT) |
#define | IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) |
#define | IS_HRTIM_TIMERID(TIMERID) |
#define | IS_HRTIM_TIMERINDEX(TIMERINDEX) |
#define | IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FF) == 0x00000000) |
#define | IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0) == 0x00000000) |
#define | IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER) |
#define | IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH) |
#define | IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0) == 0x00000000) |
#define | IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK) |
#define | IS_HRTIM_TIMING_UNIT(TIMERINDEX) |
#define | IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE) |
#define | IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001) == 0x00000000) |
#define | IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) |
#define | IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFF) == 0x00000000) |
#define | IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING) |
#define | IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING) |
#define | IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) |
Functions | |
void | HRTIM_ADCTriggerConfig (HRTIM_TypeDef *HRTIMx, uint32_t ADCTrigger, HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg) |
Configures both the ADC trigger register update source and the ADC trigger source. More... | |
void | HRTIM_BurstDMAConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t RegistersToUpdate) |
Configures the burst DMA controller for a timer. More... | |
void | HRTIM_BurstModeConfig (HRTIM_TypeDef *HRTIMx, HRTIM_BurstModeCfgTypeDef *pBurstModeCfg) |
Configures the burst mode feature of the HRTIMx. More... | |
void | HRTIM_BurstModeCtl (HRTIM_TypeDef *HRTIMx, uint32_t Enable) |
Enables or disables the HRTIMx burst mode controller. More... | |
void | HRTIM_ChopperModeConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg) |
Configures the chopper mode feature for a timer. More... | |
void | HRTIM_ClearCommonFlag (HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonFLAG) |
Clears the common interrupt flags. More... | |
void | HRTIM_ClearCommonITPendingBit (HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonIT) |
Clears the common interrupt pending bits. More... | |
void | HRTIM_ClearFlag (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG) |
Clears the Master and slaves interrupt flags. More... | |
void | HRTIM_ClearITPendingBit (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT) |
Clears the Master and slaves interrupt request pending bits. More... | |
void | HRTIM_DeadTimeConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg) |
Configures the dead time insertion feature for a timer. More... | |
void | HRTIM_DeInit (HRTIM_TypeDef *HRTIMx) |
De-initializes a timer operating in all mode. More... | |
void | HRTIM_DLLCalibrationStart (HRTIM_TypeDef *HRTIMx, uint32_t CalibrationRate) |
Starts the DLL calibration. More... | |
void | HRTIM_DMACmd (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState) |
Enables or disables the HRTIMx's DMA Requests. More... | |
void | HRTIM_EventConfig (HRTIM_TypeDef *HRTIMx, uint32_t Event, HRTIM_EventCfgTypeDef *pEventCfg) |
Configures the conditioning of an external event. More... | |
void | HRTIM_EventPrescalerConfig (HRTIM_TypeDef *HRTIMx, uint32_t Prescaler) |
Configures the external event conditioning block prescaler. More... | |
void | HRTIM_FaultConfig (HRTIM_TypeDef *hrtim, HRTIM_FaultCfgTypeDef *pFaultCfg, uint32_t Fault) |
Configures the conditioning of fault input. More... | |
void | HRTIM_FaultModeCtl (HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Enable) |
Enables or disables the HRTIMx Fault mode. More... | |
void | HRTIM_FaultPrescalerConfig (HRTIM_TypeDef *HRTIMx, uint32_t Prescaler) |
Configures the fault conditioning block prescaler. More... | |
uint32_t | HRTIM_GetBurstStatus (HRTIM_TypeDef *HRTIMx) |
Returns the actual status (active or inactive) of the burst mode controller. More... | |
uint32_t | HRTIM_GetCapturedValue (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit) |
Returns actual value of the capture register of the designated capture unit. More... | |
FlagStatus | HRTIM_GetCommonFlagStatus (HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonFLAG) |
Checks whether the specified HRTIM common flag is set or not. More... | |
ITStatus | HRTIM_GetCommonITStatus (HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonIT) |
Checks whether the specified HRTIM common interrupt has occurred or not. More... | |
uint32_t | HRTIM_GetCurrentPushPullStatus (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx) |
Indicates on which output the signal is currently active (when the push pull mode is enabled) More... | |
uint32_t | HRTIM_GetDelayedProtectionStatus (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output) |
Returns the level (active or inactive) of the designated output when the delayed protection was triggered. More... | |
FlagStatus | HRTIM_GetFlagStatus (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG) |
Checks whether the specified HRTIM flag is set or not. More... | |
uint32_t | HRTIM_GetIdlePushPullStatus (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx) |
Indicates on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered. More... | |
ITStatus | HRTIM_GetITStatus (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT) |
Checks whether the specified HRTIM interrupt has occurred or not. More... | |
void | HRTIM_ITCommonConfig (HRTIM_TypeDef *HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState) |
Enables or disables the common interrupt request. More... | |
void | HRTIM_ITConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_TIM_IT, FunctionalState NewState) |
Enables or disables the Master and slaves interrupt request. More... | |
void | HRTIM_MasterSetCompare (HRTIM_TypeDef *HRTIMx, uint32_t CompareUnit, uint32_t Compare) |
Sets the HRTIMx Master Comparex Register value. More... | |
void | HRTIM_SimpleBase_Init (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct) |
Initializes the HRTIMx timer in basic time base mode. More... | |
void | HRTIM_SimpleBaseStart (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx) |
Starts the counter of a timer operating in basic time base mode. More... | |
void | HRTIM_SimpleBaseStop (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx) |
Stops the counter of a timer operating in basic time base mode. More... | |
void | HRTIM_SimpleCapture_Init (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct) |
Initializes a timer operating in basic capture mode. More... | |
void | HRTIM_SimpleCaptureChannelConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureChannel, HRTIM_BasicCaptureChannelCfgTypeDef *pBasicCaptureChannelCfg) |
Configures a basic capture. More... | |
void | HRTIM_SimpleCaptureStart (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureChannel) |
Enables a basic capture on the designed capture unit. More... | |
void | HRTIM_SimpleCaptureStop (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureChannel) |
Disables a basic capture on the designed capture unit. More... | |
void | HRTIM_SimpleOC_Init (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct) |
Initializes the HRTIMx timer in basic output compare mode. More... | |
void | HRTIM_SimpleOCChannelConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OCChannel, HRTIM_BasicOCChannelCfgTypeDef *pBasicOCChannelCfg) |
Configures an output in basic output compare mode. More... | |
void | HRTIM_SimpleOCStart (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OCChannel) |
Starts the output compare signal generation on the designed timer output. More... | |
void | HRTIM_SimpleOCStop (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OCChannel) |
Stops the output compare signal generation on the designed timer output. More... | |
void | HRTIM_SimpleOnePulse_Init (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct) |
Initializes the HRTIMx timer in basic one pulse mode. More... | |
void | HRTIM_SimpleOnePulseChannelConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OnePulseChannel, HRTIM_BasicOnePulseChannelCfgTypeDef *pBasicOnePulseChannelCfg) |
Configures an output basic one pulse mode. More... | |
void | HRTIM_SimpleOnePulseStart (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t OnePulseChannel) |
Enables the basic one pulse signal generation on the designed output. More... | |
void | HRTIM_SimpleOnePulseStop (HRTIM_TypeDef *HRTIM_, uint32_t TimerIdx, uint32_t OnePulseChannel) |
Disables the basic one pulse signal generation on the designed output. More... | |
void | HRTIM_SimplePWM_Init (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct) |
Initializes the HRTIMx timer in basic PWM mode. More... | |
void | HRTIM_SimplePWMChannelConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t PWMChannel, HRTIM_BasicPWMChannelCfgTypeDef *pBasicPWMChannelCfg) |
Configures an output in basic PWM mode. More... | |
void | HRTIM_SimplePWMStart (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t PWMChannel) |
Starts the PWM output signal generation on the designed timer output. More... | |
void | HRTIM_SimplePWMStop (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t PWMChannel) |
Stops the PWM output signal generation on the designed timer output. More... | |
void | HRTIM_SlaveSetCompare (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CompareUnit, uint32_t Compare) |
Sets the HRTIMx Slave Comparex Register value. More... | |
void | HRTIM_SoftwareCapture (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit) |
Triggers a software capture on the designed capture unit. More... | |
void | HRTIM_SoftwareReset (HRTIM_TypeDef *HRTIMx, uint32_t TimersToReset) |
Triggers the reset of one or several timers. More... | |
void | HRTIM_SoftwareUpdate (HRTIM_TypeDef *HRTIMx, uint32_t TimersToUpdate) |
Triggers the update of the registers of one or several timers. More... | |
void | HRTIM_SynchronizationConfig (HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef *pSynchroCfg) |
Configures the external input/output synchronization of the HRTIMx. More... | |
void | HRTIM_TimerEventFilteringConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Event, HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg) |
Configures the event filtering capabilities of a timer (blanking, windowing) More... | |
void | HRTIM_Waveform_Init (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef *HRTIM_BaseInitStruct, HRTIM_TimerInitTypeDef *HRTIM_TimerInitStruct) |
Initializes a timer operating in waveform mode. More... | |
void | HRTIM_WaveformCaptureConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CaptureUnit, HRTIM_CaptureCfgTypeDef *pCaptureCfg) |
Configures the capture unit of a timer operating in waveform mode. More... | |
void | HRTIM_WaveformCompareConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t CompareUnit, HRTIM_CompareCfgTypeDef *pCompareCfg) |
Configures the compare unit of a timer operating in waveform mode. More... | |
void | HRTIM_WaveformCounterStart (HRTIM_TypeDef *HRTIMx, uint32_t TimersToStart) |
Starts the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter start. More... | |
void | HRTIM_WaveformCounterStop (HRTIM_TypeDef *HRTIMx, uint32_t TimersToStop) |
Stops the counter of the designated timer(s) operating in waveform mode Timers can be combined (ORed) to allow for simultaneous counter stop. More... | |
uint32_t | HRTIM_WaveformGetOutputLevel (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output) |
Returns actual level (active or inactive) of the designated output. More... | |
uint32_t | HRTIM_WaveformGetOutputState (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output) |
Returns actual state (RUN, IDLE, FAULT) of the designated output. More... | |
void | HRTIM_WaveformOuputConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg) |
void | HRTIM_WaveformOutputConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output, HRTIM_OutputCfgTypeDef *pOutputCfg) |
Configures the output of a timer operating in waveform mode. More... | |
void | HRTIM_WaveformOutputStart (HRTIM_TypeDef *HRTIMx, uint32_t OuputsToStart) |
Enables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output enabling. More... | |
void | HRTIM_WaveformOutputStop (HRTIM_TypeDef *HRTIM_, uint32_t OuputsToStop) |
Disables the generation of the waveform signal on the designated output(s) Outputs can be combined (ORed) to allow for simultaneous output disabling. More... | |
void | HRTIM_WaveformSetOutputLevel (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, uint32_t Output, uint32_t OutputLevel) |
Forces the timer output to its active or inactive state. More... | |
void | HRTIM_WaveformTimerConfig (HRTIM_TypeDef *HRTIMx, uint32_t TimerIdx, HRTIM_TimerCfgTypeDef *HRTIM_TimerCfgStruct) |
Configures the general behavior of a timer operating in waveform mode. More... | |
This file contains all the functions prototypes for the HRTIM firmware library.
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:
http://www.st.com/software_license_agreement_liberty_v2
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
Definition in file stm32f30x_hrtim.h.