#include <bsp.h>
#include <kern.h>
#include <config.h>
#include <bfin_dma.h>
#include <string.h>
#include "lw_emac.h"
Go to the source code of this file.
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static ethernet_data_t rxBuffer[ETH_RX_BUF_SIZE] | __attribute__ ((section(".dma"))) |
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int | bfin_EMAC_init (uint8_t *ethAddr) |
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int | bfin_EMAC_recv (uint8_t *packet, size_t size) |
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int | bfin_EMAC_send (void *packet, int length) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, mmc_ctl)==0x80) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, mmc_rxc_dmaovf)==0x110) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, mmc_rxc_ge1024)==0x15c) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, mmc_rxc_ok)==0x100) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, mmc_tirqe)==0x90) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, opmode)==0x0) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, rx_stat)==0x68) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, staadd)==0x14) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, sysctl)==0x60) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, wkup_ctl)==0x2c) |
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| COMPILETIME_ASSERT (offsetof(bfin_emac_regs_t, wkup_ffcrc1)==0x4c) |
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| COMPILETIME_ASSERT (sizeof(ethernet_data_t)==0x618) |
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static uint8_t | lw_emac_init_registers (uint8_t *ethAddr) |
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static uint32_t | lw_emac_read_phy_reg (uint8_t phy_addr, uint8_t reg_addr) |
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static void | lw_emac_set_mac_addr (uint8_t *ethAddr) |
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static void | lw_emac_write_phy_reg (uint8_t phy_addr, uint8_t reg_addr, uint32_t data) |
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◆ ETH_FRAME_SIZE
#define ETH_FRAME_SIZE 0x614 |
◆ ETH_RX_BUF_SIZE
#define ETH_RX_BUF_SIZE 2 |
◆ ETH_TX_BUF_SIZE
#define ETH_TX_BUF_SIZE 1 |
◆ MII_ANAR_100_FD
#define MII_ANAR_100_FD BIT (8) /* Can do 100BASE-TX full duplex */ |
◆ MII_ANAR_10_FD
#define MII_ANAR_10_FD BIT (6) /* Can do 10BASE-T full duplex */ |
◆ MII_BMCR
#define MII_BMCR 0x00 /* Basic Mode Control Register */ |
◆ MII_BMCR_ANEG_EN
#define MII_BMCR_ANEG_EN BIT (12) |
◆ MII_BMCR_ANEG_RST
#define MII_BMCR_ANEG_RST BIT (9) |
◆ MII_BMCR_RST
#define MII_BMCR_RST BIT (15) |
◆ MII_BMSR
#define MII_BMSR 0x01 /* Basic Mode Status Register */ |
◆ MII_BMSR_ANEGACK
#define MII_BMSR_ANEGACK BIT (5) |
◆ MII_BMSR_LINK
#define MII_BMSR_LINK BIT (2) |
◆ MII_LPAR
#define MII_LPAR 0x05 /* Auto-Negotiation Link Partner Ability Register */ |
◆ MII_PHYIDR1
#define MII_PHYIDR1 0x02 /* PHY Identifier Register 1 */ |
◆ MII_PHYIDR2
#define MII_PHYIDR2 0x03 /* PHY Identifier Register 2 */ |
◆ PHY_ADDR
◆ PHY_MDC_Hz
#define PHY_MDC_Hz 2500000 |
◆ PHY_RETRIES
◆ bfin_emac_regs_t
◆ ethernet_data_t
◆ __attribute__()
◆ bfin_EMAC_init()
int bfin_EMAC_init |
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uint8_t * |
ethAddr | ) |
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◆ bfin_EMAC_recv()
int bfin_EMAC_recv |
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uint8_t * |
packet, |
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size_t |
size |
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) |
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◆ bfin_EMAC_send()
int bfin_EMAC_send |
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void * |
packet, |
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int |
length |
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) |
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◆ COMPILETIME_ASSERT() [1/12]
◆ COMPILETIME_ASSERT() [2/12]
◆ COMPILETIME_ASSERT() [3/12]
◆ COMPILETIME_ASSERT() [4/12]
◆ COMPILETIME_ASSERT() [5/12]
◆ COMPILETIME_ASSERT() [6/12]
◆ COMPILETIME_ASSERT() [7/12]
◆ COMPILETIME_ASSERT() [8/12]
◆ COMPILETIME_ASSERT() [9/12]
◆ COMPILETIME_ASSERT() [10/12]
◆ COMPILETIME_ASSERT() [11/12]
◆ COMPILETIME_ASSERT() [12/12]
◆ lw_emac_init_registers()
◆ lw_emac_read_phy_reg()
◆ lw_emac_set_mac_addr()
static void lw_emac_set_mac_addr |
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uint8_t * |
ethAddr | ) |
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static |
◆ lw_emac_write_phy_reg()
◆ pEth
◆ rxIdx
◆ txIdx