RCC PLL configuration structure definition. More...
#include <stm32f4xx_hal_rcc_ex.h>
Public Attributes | |
| uint32_t | PLLFRACN |
| uint32_t | PLLM |
| uint32_t | PLLN |
| uint32_t | PLLP |
| uint32_t | PLLQ |
| uint32_t | PLLR |
| uint32_t | PLLRGE |
| uint32_t | PLLSource |
| uint32_t | PLLState |
| uint32_t | PLLVCOSEL |
RCC PLL configuration structure definition.
Definition at line 47 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
| uint32_t RCC_PLLInitTypeDef::PLLFRACN |
PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for PLL1 VCO It should be a value between 0 and 8191
Definition at line 78 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h.
| uint32_t RCC_PLLInitTypeDef::PLLM |
PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 0 and Max_Data = 63
PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 2 and Max_Data = 63
PLLM: Division factor for PLL VCO input clock. This parameter must be a number between Min_Data = 1 and Max_Data = 63
Definition at line 55 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
| uint32_t RCC_PLLInitTypeDef::PLLN |
PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432 except for STM32F411xE devices where the Min_Data = 192
PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 50 and Max_Data = 432
PLLN: Multiplication factor for PLL VCO output clock. This parameter must be a number between Min_Data = 4 and Max_Data = 512 or between Min_Data = 8 and Max_Data = 420(*) (*) : For stm32h7a3xx and stm32h7b3xx family lines.
Definition at line 58 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
| uint32_t RCC_PLLInitTypeDef::PLLP |
PLLP: Division factor for main system clock (SYSCLK). This parameter must be a value of PLLP Clock Divider
PLLP: Division factor for system clock. This parameter must be a number between Min_Data = 2 and Max_Data = 128 odd division factors are not allowed
Definition at line 62 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
| uint32_t RCC_PLLInitTypeDef::PLLQ |
PLLQ: Division factor for OTG FS, SDIO and RNG clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 15
PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. This parameter must be a number between Min_Data = 2 and Max_Data = 15
PLLQ: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128
Definition at line 65 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
| uint32_t RCC_PLLInitTypeDef::PLLR |
PLLR: Division factor for peripheral clocks. This parameter must be a number between Min_Data = 1 and Max_Data = 128
Definition at line 71 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h.
| uint32_t RCC_PLLInitTypeDef::PLLRGE |
PLLRGE: PLL1 clock Input range This parameter must be a value of RCC PLL1 VCI Range
Definition at line 73 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h.
| uint32_t RCC_PLLInitTypeDef::PLLSource |
RCC_PLLSource: PLL entry clock source. This parameter must be a value of PLL Clock Source
Definition at line 52 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
| uint32_t RCC_PLLInitTypeDef::PLLState |
The new state of the PLL. This parameter can be a value of PLL Config
Definition at line 49 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h.
| uint32_t RCC_PLLInitTypeDef::PLLVCOSEL |
PLLVCOSEL: PLL1 clock Output range This parameter must be a value of RCC PLL1 VCO Range
Definition at line 75 of file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rcc.h.