stm32f7xx_hal_dma2d.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F7xx_HAL_DMA2D_H
22 #define STM32F7xx_HAL_DMA2D_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 #if defined (DMA2D)
29 
30 /* Includes ------------------------------------------------------------------*/
31 #include "stm32f7xx_hal_def.h"
32 
42 /* Exported types ------------------------------------------------------------*/
46 #define MAX_DMA2D_LAYER 2U
51 typedef struct
52 {
53  uint32_t *pCLUT;
55  uint32_t CLUTColorMode;
58  uint32_t Size;
60 } DMA2D_CLUTCfgTypeDef;
61 
65 typedef struct
66 {
67  uint32_t Mode;
70  uint32_t ColorMode;
73  uint32_t OutputOffset;
75 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
76  uint32_t AlphaInverted;
79  uint32_t RedBlueSwap;
83 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
84 
85 
86 
87 
88 } DMA2D_InitTypeDef;
89 
90 
94 typedef struct
95 {
96  uint32_t InputOffset;
99  uint32_t InputColorMode;
102  uint32_t AlphaMode;
105  uint32_t InputAlpha;
113 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
114  uint32_t AlphaInverted;
117  uint32_t RedBlueSwap;
119 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
120 
121 
122 } DMA2D_LayerCfgTypeDef;
123 
127 typedef enum
128 {
129  HAL_DMA2D_STATE_RESET = 0x00U,
130  HAL_DMA2D_STATE_READY = 0x01U,
131  HAL_DMA2D_STATE_BUSY = 0x02U,
132  HAL_DMA2D_STATE_TIMEOUT = 0x03U,
133  HAL_DMA2D_STATE_ERROR = 0x04U,
134  HAL_DMA2D_STATE_SUSPEND = 0x05U
135 }HAL_DMA2D_StateTypeDef;
136 
140 typedef struct __DMA2D_HandleTypeDef
141 {
142  DMA2D_TypeDef *Instance;
144  DMA2D_InitTypeDef Init;
146  void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);
148  void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d);
150 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
151  void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d);
153  void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d);
155  void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d);
157  void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d);
159 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
160 
161  DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER];
163  HAL_LockTypeDef Lock;
165  __IO HAL_DMA2D_StateTypeDef State;
167  __IO uint32_t ErrorCode;
168 } DMA2D_HandleTypeDef;
169 
170 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
171 
174 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d);
175 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
176 
180 /* Exported constants --------------------------------------------------------*/
188 #define HAL_DMA2D_ERROR_NONE 0x00000000U
189 #define HAL_DMA2D_ERROR_TE 0x00000001U
190 #define HAL_DMA2D_ERROR_CE 0x00000002U
191 #define HAL_DMA2D_ERROR_CAE 0x00000004U
192 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U
193 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
194 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U
195 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
196 
204 #define DMA2D_M2M 0x00000000U
205 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0
206 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1
207 #define DMA2D_R2M DMA2D_CR_MODE
215 #define DMA2D_OUTPUT_ARGB8888 0x00000000U
216 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0
217 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1
218 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
219 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2
227 #define DMA2D_INPUT_ARGB8888 0x00000000U
228 #define DMA2D_INPUT_RGB888 0x00000001U
229 #define DMA2D_INPUT_RGB565 0x00000002U
230 #define DMA2D_INPUT_ARGB1555 0x00000003U
231 #define DMA2D_INPUT_ARGB4444 0x00000004U
232 #define DMA2D_INPUT_L8 0x00000005U
233 #define DMA2D_INPUT_AL44 0x00000006U
234 #define DMA2D_INPUT_AL88 0x00000007U
235 #define DMA2D_INPUT_L4 0x00000008U
236 #define DMA2D_INPUT_A8 0x00000009U
237 #define DMA2D_INPUT_A4 0x0000000AU
245 #define DMA2D_NO_MODIF_ALPHA 0x00000000U
246 #define DMA2D_REPLACE_ALPHA 0x00000001U
247 #define DMA2D_COMBINE_ALPHA 0x00000002U
253 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
254 
257 #define DMA2D_REGULAR_ALPHA 0x00000000U
258 #define DMA2D_INVERTED_ALPHA 0x00000001U
266 #define DMA2D_RB_REGULAR 0x00000000U
267 #define DMA2D_RB_SWAP 0x00000001U
271 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
272 
273 
274 
275 
276 
280 #define DMA2D_CCM_ARGB8888 0x00000000U
281 #define DMA2D_CCM_RGB888 0x00000001U
289 #define DMA2D_IT_CE DMA2D_CR_CEIE
290 #define DMA2D_IT_CTC DMA2D_CR_CTCIE
291 #define DMA2D_IT_CAE DMA2D_CR_CAEIE
292 #define DMA2D_IT_TW DMA2D_CR_TWIE
293 #define DMA2D_IT_TC DMA2D_CR_TCIE
294 #define DMA2D_IT_TE DMA2D_CR_TEIE
302 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF
303 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
304 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
305 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF
306 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF
307 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF
315 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort
320 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
321 
324 typedef enum
325 {
326  HAL_DMA2D_MSPINIT_CB_ID = 0x00U,
327  HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U,
328  HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U,
329  HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U,
330  HAL_DMA2D_LINEEVENT_CB_ID = 0x04U,
331  HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U,
332 }HAL_DMA2D_CallbackIDTypeDef;
333 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
334 
335 
339 /* Exported macros ------------------------------------------------------------*/
348 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
349 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
350  (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
351  (__HANDLE__)->MspInitCallback = NULL; \
352  (__HANDLE__)->MspDeInitCallback = NULL; \
353  }while(0)
354 #else
355 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
356 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
357 
358 
364 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
365 
366 
367 /* Interrupt & Flag management */
381 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
382 
396 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
397 
411 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
412 
426 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
427 
441 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
442 
447 /* Exported functions --------------------------------------------------------*/
456 /* Initialization and de-initialization functions *******************************/
457 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
458 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
459 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
460 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
461 /* Callbacks Register/UnRegister functions ***********************************/
462 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
463 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
464 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
465 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
466 
476 /* IO operation functions *******************************************************/
477 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
478 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
479 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
480 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
481 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
482 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
483 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
484 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
485 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
486 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
487 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
488 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
489 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
490 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
491 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
492 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
493 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
494 
503 /* Peripheral Control functions *************************************************/
504 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
505 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
506 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
507 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
508 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
509 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
510 
519 /* Peripheral State functions ***************************************************/
520 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
521 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
522 
531 /* Private constants ---------------------------------------------------------*/
532 
540 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW
548 #define DMA2D_COLOR_VALUE 0x000000FFU
556 #define DMA2D_MAX_LAYER 2U
564 #define DMA2D_BACKGROUND_LAYER 0x00000000U
565 #define DMA2D_FOREGROUND_LAYER 0x00000001U
573 #define DMA2D_OFFSET DMA2D_FGOR_LO
581 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)
582 #define DMA2D_LINE DMA2D_NLR_NL
590 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U)
600 /* Private macros ------------------------------------------------------------*/
601 
604 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
605 
606 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
607  ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
608 
609 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
610  ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
611  ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
612 
613 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
614 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
615 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
616 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
617 
618 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
619  ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
620  ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
621  ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
622  ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
623  ((INPUT_CM) == DMA2D_INPUT_A4))
624 
625 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
626  ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
627  ((AlphaMode) == DMA2D_COMBINE_ALPHA))
628 
629 #if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
630 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
631  ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
632 
633 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
634  ((RB_Swap) == DMA2D_RB_SWAP))
635 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
636 
637 
638 
639 
640 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
641 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
642 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
643 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
644  ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
645  ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
646 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
647  ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
648  ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
649 
661 #endif /* defined (DMA2D) */
662 
663 #ifdef __cplusplus
664 }
665 #endif
666 
667 #endif /* STM32F7xx_HAL_DMA2D_H */
668 
669 
670 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
Init
napi_value Init(napi_env env, napi_value exports)
Definition: porcupine/demo/c/pvrecorder/node/pv_recorder_napi.c:197
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32f469xx.h:377
stm32f7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745

picovoice_driver
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autogenerated on Fri Apr 1 2022 02:14:53