Header file of SMBUS HAL module. More...
#include "stm32f4xx_hal_def.h"
Go to the source code of this file.
Classes | |
| struct | __SMBUS_HandleTypeDef | 
| SMBUS handle Structure definition.  More... | |
| struct | SMBUS_InitTypeDef | 
| SMBUS Configuration Structure definition.  More... | |
Macros | |
| #define | __HAL_SMBUS_CLEAR_ADDRFLAG(__HANDLE__) | 
| Clears the SMBUS ADDR pending flag.  More... | |
| #define | __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & SMBUS_FLAG_MASK)) | 
| Clears the SMBUS pending flags which are cleared by writing 0 in a specific bit.  More... | |
| #define | __HAL_SMBUS_CLEAR_STOPFLAG(__HANDLE__) | 
| Clears the SMBUS STOPF pending flag.  More... | |
| #define | __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) | 
| Disable the SMBUS peripheral.  More... | |
| #define | __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) | 
| #define | __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) | 
| Enable the SMBUS peripheral.  More... | |
| #define | __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) | 
| Enable or disable the specified SMBUS interrupts.  More... | |
| #define | __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_ACK)) | 
| Generate a Non-Acknowledge SMBUS peripheral in Slave mode.  More... | |
| #define | __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) | 
| Checks whether the specified SMBUS flag is set or not.  More... | |
| #define | __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) | 
| Checks if the specified SMBUS interrupt source is enabled or disabled.  More... | |
| #define | __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) | 
| Reset SMBUS handle state.  More... | |
| #define | HAL_SMBUS_ERROR_AF 0x00000004U | 
| #define | HAL_SMBUS_ERROR_ALERT 0x00000020U | 
| #define | HAL_SMBUS_ERROR_ARLO 0x00000002U | 
| #define | HAL_SMBUS_ERROR_BERR 0x00000001U | 
| #define | HAL_SMBUS_ERROR_NONE 0x00000000U | 
| #define | HAL_SMBUS_ERROR_OVR 0x00000008U | 
| #define | HAL_SMBUS_ERROR_PECERR 0x00000040U | 
| #define | HAL_SMBUS_ERROR_TIMEOUT 0x00000010U | 
| #define | IS_SMBUS_ADDRESSING_MODE(ADDRESS) | 
| #define | IS_SMBUS_CLOCK_SPEED(SPEED) (((SPEED) > 0U) && ((SPEED) <= 100000U)) | 
| #define | IS_SMBUS_DUAL_ADDRESS(ADDRESS) | 
| #define | IS_SMBUS_GENERAL_CALL(CALL) | 
| #define | IS_SMBUS_NO_STRETCH(STRETCH) | 
| #define | IS_SMBUS_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & 0xFFFFFC00U) == 0U) | 
| #define | IS_SMBUS_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & 0xFFFFFF01U) == 0U) | 
| #define | IS_SMBUS_PEC(PEC) | 
| #define | IS_SMBUS_PERIPHERAL_MODE(MODE) | 
| #define | IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) | 
| #define | SMBUS_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF))) | 
| #define | SMBUS_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)(0x00F1)))) | 
| #define | SMBUS_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0x0300)) >> 7) | (uint16_t)0x00F0))) | 
| #define | SMBUS_7BIT_ADD_READ(__ADDRESS__) ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0)) | 
| #define | SMBUS_7BIT_ADD_WRITE(__ADDRESS__) ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0))) | 
| #define | SMBUS_ADDRESSINGMODE_10BIT (I2C_OAR1_ADDMODE | 0x00004000U) | 
| #define | SMBUS_ADDRESSINGMODE_7BIT 0x00004000U | 
| #define | SMBUS_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF | 
| #define | SMBUS_ANALOGFILTER_ENABLE 0x00000000U | 
| #define | SMBUS_DIRECTION_RECEIVE 0x00000000U | 
| #define | SMBUS_DIRECTION_TRANSMIT 0x00000001U | 
| #define | SMBUS_DUALADDRESS_DISABLE 0x00000000U | 
| #define | SMBUS_DUALADDRESS_ENABLE I2C_OAR2_ENDUAL | 
| #define | SMBUS_FIRST_AND_LAST_FRAME_NO_PEC 0x00000003U | 
| #define | SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC 0x00000005U | 
| #define | SMBUS_FIRST_FRAME 0x00000001U | 
| #define | SMBUS_FLAG_ADD10 0x00010008U | 
| #define | SMBUS_FLAG_ADDR 0x00010002U | 
| #define | SMBUS_FLAG_AF 0x00010400U | 
| #define | SMBUS_FLAG_ARLO 0x00010200U | 
| #define | SMBUS_FLAG_BERR 0x00010100U | 
| #define | SMBUS_FLAG_BTF 0x00010004U | 
| #define | SMBUS_FLAG_BUSY 0x00100002U | 
| #define | SMBUS_FLAG_DUALF 0x00100080U | 
| #define | SMBUS_FLAG_GENCALL 0x00100010U | 
| #define | SMBUS_FLAG_MASK 0x0000FFFFU | 
| #define | SMBUS_FLAG_MSL 0x00100001U | 
| #define | SMBUS_FLAG_OVR 0x00010800U | 
| #define | SMBUS_FLAG_PECERR 0x00011000U | 
| #define | SMBUS_FLAG_RXNE 0x00010040U | 
| #define | SMBUS_FLAG_SB 0x00010001U | 
| #define | SMBUS_FLAG_SMBALERT 0x00018000U | 
| #define | SMBUS_FLAG_SMBDEFAULT 0x00100020U | 
| #define | SMBUS_FLAG_SMBHOST 0x00100040U | 
| #define | SMBUS_FLAG_STOPF 0x00010010U | 
| #define | SMBUS_FLAG_TIMEOUT 0x00014000U | 
| #define | SMBUS_FLAG_TRA 0x00100004U | 
| #define | SMBUS_FLAG_TXE 0x00010080U | 
| #define | SMBUS_FREQRANGE(__PCLK__) ((__PCLK__)/1000000U) | 
| #define | SMBUS_GENERALCALL_DISABLE 0x00000000U | 
| #define | SMBUS_GENERALCALL_ENABLE I2C_CR1_ENGC | 
| #define | SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ENPEC) | 
| #define | SMBUS_GET_PEC_VALUE(__HANDLE__) ((__HANDLE__)->XferPEC) | 
| #define | SMBUS_IT_BUF I2C_CR2_ITBUFEN | 
| #define | SMBUS_IT_ERR I2C_CR2_ITERREN | 
| #define | SMBUS_IT_EVT I2C_CR2_ITEVTEN | 
| #define | SMBUS_LAST_FRAME_NO_PEC 0x00000004U | 
| #define | SMBUS_LAST_FRAME_WITH_PEC 0x00000006U | 
| #define | SMBUS_NEXT_FRAME 0x00000002U | 
| #define | SMBUS_NOSTRETCH_DISABLE 0x00000000U | 
| #define | SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH | 
| #define | SMBUS_PEC_DISABLE 0x00000000U | 
| #define | SMBUS_PEC_ENABLE I2C_CR1_ENPEC | 
| #define | SMBUS_PERIPHERAL_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) | 
| #define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE I2C_CR1_SMBUS | 
| #define | SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) | 
| #define | SMBUS_RISE_TIME(__FREQRANGE__) ( ((__FREQRANGE__) + 1U)) | 
| #define | SMBUS_SPEED_STANDARD(__PCLK__, __SPEED__) (((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) | 
Typedefs | |
| typedef struct __SMBUS_HandleTypeDef | SMBUS_HandleTypeDef | 
| SMBUS handle Structure definition.  More... | |
Enumerations | |
| enum | HAL_SMBUS_ModeTypeDef { HAL_SMBUS_MODE_NONE = 0x00U, HAL_SMBUS_MODE_MASTER = 0x10U, HAL_SMBUS_MODE_SLAVE = 0x20U } | 
| HAL Mode structure definition.  More... | |
| enum | HAL_SMBUS_StateTypeDef {  HAL_SMBUS_STATE_RESET = 0x00U, HAL_SMBUS_STATE_READY = 0x20U, HAL_SMBUS_STATE_BUSY = 0x24U, HAL_SMBUS_STATE_BUSY_TX = 0x21U, HAL_SMBUS_STATE_BUSY_RX = 0x22U, HAL_SMBUS_STATE_LISTEN = 0x28U, HAL_SMBUS_STATE_BUSY_TX_LISTEN = 0x29U, HAL_SMBUS_STATE_BUSY_RX_LISTEN = 0x2AU, HAL_SMBUS_STATE_ABORT = 0x60U, HAL_SMBUS_STATE_TIMEOUT = 0xA0U, HAL_SMBUS_STATE_ERROR = 0xE0U }  | 
| HAL State structure definition.  More... | |
Header file of SMBUS HAL module.
This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause
Definition in file stm32f4xx_hal_smbus.h.