This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral: More...
#include "stm32f30x_rcc.h"
Include dependency graph for stm32f30x_rcc.c:
Go to the source code of this file.
Functions | |
| void | RCC_ADCCLKConfig (uint32_t RCC_PLLCLK) |
| Configures the ADC clock (ADCCLK). More... | |
| void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue) |
| Adjusts the Internal High Speed oscillator (HSI) calibration value. More... | |
| void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState) |
| Enables or disables the AHB peripheral clock. More... | |
| void | RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState) |
| Forces or releases AHB peripheral reset. More... | |
| void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
| Enables or disables the Low Speed APB (APB1) peripheral clock. More... | |
| void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
| Forces or releases Low Speed APB (APB1) peripheral reset. More... | |
| void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
| Enables or disables the High Speed APB (APB2) peripheral clock. More... | |
| void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
| Forces or releases High Speed APB (APB2) peripheral reset. More... | |
| void | RCC_BackupResetCmd (FunctionalState NewState) |
| Forces or releases the Backup domain reset. More... | |
| void | RCC_ClearFlag (void) |
| Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More... | |
| void | RCC_ClearITPendingBit (uint8_t RCC_IT) |
| Clears the RCC's interrupt pending bits. More... | |
| void | RCC_ClockSecuritySystemCmd (FunctionalState NewState) |
| Enables or disables the Clock Security System. More... | |
| void | RCC_DeInit (void) |
| Resets the RCC clock configuration to the default reset state. More... | |
| void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks) |
| Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2. More... | |
| FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG) |
| Checks whether the specified RCC flag is set or not. More... | |
| ITStatus | RCC_GetITStatus (uint8_t RCC_IT) |
| Checks whether the specified RCC interrupt has occurred or not. More... | |
| uint8_t | RCC_GetSYSCLKSource (void) |
| Returns the clock source used as system clock. More... | |
| void | RCC_HCLKConfig (uint32_t RCC_SYSCLK) |
| Configures the AHB clock (HCLK). More... | |
| void | RCC_HRTIM1CLKConfig (uint32_t RCC_HRTIMCLK) |
| Configures the HRTIM1 clock sources(HRTIM1CLK). More... | |
| void | RCC_HSEConfig (uint8_t RCC_HSE) |
| Configures the External High Speed oscillator (HSE). More... | |
| void | RCC_HSICmd (FunctionalState NewState) |
| Enables or disables the Internal High Speed oscillator (HSI). More... | |
| void | RCC_I2CCLKConfig (uint32_t RCC_I2CCLK) |
| Configures the I2C clock (I2CCLK). More... | |
| void | RCC_I2SCLKConfig (uint32_t RCC_I2SCLKSource) |
| Configures the I2S clock source (I2SCLK). More... | |
| void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState) |
| Enables or disables the specified RCC interrupts. More... | |
| void | RCC_LSEConfig (uint32_t RCC_LSE) |
| Configures the External Low Speed oscillator (LSE). More... | |
| void | RCC_LSEDriveConfig (uint32_t RCC_LSEDrive) |
| Configures the External Low Speed oscillator (LSE) drive capability. More... | |
| void | RCC_LSICmd (FunctionalState NewState) |
| Enables or disables the Internal Low Speed oscillator (LSI). More... | |
| void | RCC_MCOConfig (uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler) |
| Selects the clock source to output on MCO pin (PA8) and the corresponding prescsaler. More... | |
| void | RCC_PCLK1Config (uint32_t RCC_HCLK) |
| Configures the Low Speed APB clock (PCLK1). More... | |
| void | RCC_PCLK2Config (uint32_t RCC_HCLK) |
| Configures the High Speed APB clock (PCLK2). More... | |
| void | RCC_PLLCmd (FunctionalState NewState) |
| Enables or disables the main PLL. More... | |
| void | RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) |
| Configures the PLL clock source and multiplication factor. More... | |
| void | RCC_PREDIV1Config (uint32_t RCC_PREDIV1_Div) |
| Configures the PREDIV1 division factor. More... | |
| void | RCC_RTCCLKCmd (FunctionalState NewState) |
| Enables or disables the RTC clock. More... | |
| void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource) |
| Configures the RTC clock (RTCCLK). More... | |
| void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource) |
| Configures the system clock (SYSCLK). More... | |
| void | RCC_TIMCLKConfig (uint32_t RCC_TIMCLK) |
| Configures the TIMx clock sources(TIMCLK). More... | |
| void | RCC_USARTCLKConfig (uint32_t RCC_USARTCLK) |
| Configures the USART clock (USARTCLK). More... | |
| void | RCC_USBCLKConfig (uint32_t RCC_USBCLKSource) |
| Configures the USB clock (USBCLK). More... | |
| ErrorStatus | RCC_WaitForHSEStartUp (void) |
| Waits for HSE start-up. More... | |
Variables | |
| static __I uint16_t | ADCPrescTable [16] = {1, 2, 4, 6, 8, 10, 12, 16, 32, 64, 128, 256, 0, 0, 0, 0 } |
| static __I uint8_t | APBAHBPrescTable [16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9} |
Detailed Description
This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral:
- Version
- V1.1.1
- Date
- 04-April-2014
- Internal/external clocks, PLL, CSS and MCO configuration
- System, AHB and APB busses clocks configuration
- Peripheral clocks configuration
- Interrupts and flags management
===============================================================================
##### RCC specific features #####
===============================================================================
[..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
all peripherals are off except internal SRAM, Flash and SWD.
(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
all peripherals mapped on these busses are running at HSI speed.
(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
(+) All GPIOs are in input floating state, except the SWD pins which
are assigned to be used for debug purpose.
[..] Once the device starts from reset, the user application has to:
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance).
(+) Configure the System clock frequency and Flash settings.
(+) Configure the AHB and APB busses prescalers.
(+) Enable the clock for the peripheral(s) to be used.
(+) Configure the clock source(s) for peripherals which clocks are not
derived from the System clock (ADC, TIM, I2C, USART, RTC and IWDG). - Attention
© COPYRIGHT 2014 STMicroelectronics
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:
http://www.st.com/software_license_agreement_liberty_v2
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
Definition in file stm32f30x_rcc.c.