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00039 #ifndef __ORO_ARCH_x86_64__
00040 #define __ORO_ARCH_x86_64__
00041
00042 #ifndef CONFIG_FORCE_UP
00043 #define ORO_LOCK "lock ; "
00044 #else
00045 #define ORO_LOCK ""
00046 #endif
00047
00048 typedef struct
00049 {
00050 volatile int counter;
00051 } oro_atomic_t;
00052
00053 #define ORO_ATOMIC_SETUP oro_atomic_set
00054 #define ORO_ATOMIC_CLEANUP(v)
00055
00056 #define oro_atomic_read(v) ((v)->counter)
00057
00058 #define oro_atomic_set(v,i) (((v)->counter) = (i))
00059
00060 static __inline__ void oro_atomic_add(oro_atomic_t *v, int i)
00061 {
00062 __asm__ __volatile__(
00063 ORO_LOCK "addl %1,%0"
00064 :"=m" (v->counter)
00065 :"ir" (i), "m" (v->counter));
00066 }
00067
00068 static __inline__ void oro_atomic_sub(oro_atomic_t *v, int i)
00069 {
00070 __asm__ __volatile__(
00071 ORO_LOCK "subl %1,%0"
00072 :"=m" (v->counter)
00073 :"ir" (i), "m" (v->counter));
00074 }
00075
00076 static __inline__ int oro_atomic_sub_and_test(oro_atomic_t *v, int i)
00077 {
00078 unsigned char c;
00079
00080 __asm__ __volatile__(
00081 ORO_LOCK "subl %2,%0; sete %1"
00082 :"=m" (v->counter), "=qm" (c)
00083 :"ir" (i), "m" (v->counter) : "memory");
00084 return c;
00085 }
00086
00087 static __inline__ void oro_atomic_inc(oro_atomic_t *v)
00088 {
00089 __asm__ __volatile__(
00090 ORO_LOCK "incl %0"
00091 :"=m" (v->counter)
00092 :"m" (v->counter));
00093 }
00094
00095 static __inline__ void oro_atomic_dec(oro_atomic_t *v)
00096 {
00097 __asm__ __volatile__(
00098 ORO_LOCK "decl %0"
00099 :"=m" (v->counter)
00100 :"m" (v->counter));
00101 }
00102
00103 static __inline__ int oro_atomic_dec_and_test(oro_atomic_t *v)
00104 {
00105 unsigned char c;
00106
00107 __asm__ __volatile__(
00108 ORO_LOCK "decl %0; sete %1"
00109 :"=m" (v->counter), "=qm" (c)
00110 :"m" (v->counter) : "memory");
00111 return c != 0;
00112 }
00113
00114 static __inline__ int oro_atomic_inc_and_test(oro_atomic_t *v)
00115 {
00116 unsigned char c;
00117
00118 __asm__ __volatile__(
00119 ORO_LOCK "incl %0; sete %1"
00120 :"=m" (v->counter), "=qm" (c)
00121 :"m" (v->counter) : "memory");
00122 return c != 0;
00123 }
00124
00125 static __inline__ int oro_atomic_add_negative(int i, oro_atomic_t *v)
00126 {
00127 unsigned char c;
00128
00129 __asm__ __volatile__(
00130 ORO_LOCK "addl %2,%0; sets %1"
00131 :"=m" (v->counter), "=qm" (c)
00132 :"ir" (i), "m" (v->counter) : "memory");
00133 return c;
00134 }
00135
00136 #ifndef CONFIG_FORCE_UP
00137 #define ORO_LOCK_PREFIX "lock ; "
00138 #else
00139 #define ORO_LOCK_PREFIX ""
00140 #endif
00141
00142 struct oro__xchg_dummy
00143 {
00144 unsigned long a[100];
00145 };
00146 #define oro__xg(x) ((struct oro__xchg_dummy *)(x))
00147
00148 static inline unsigned long __oro_cmpxchg(volatile void *ptr, unsigned long old, unsigned long _new, int size)
00149 {
00150 unsigned long prev;
00151 switch (size)
00152 {
00153 case 1:
00154 __asm__ __volatile__(ORO_LOCK_PREFIX "cmpxchgb %b1,%2"
00155 : "=a"(prev)
00156 : "q"(_new), "m"(*oro__xg(ptr)), "0"(old)
00157 : "memory");
00158 return prev;
00159 case 2:
00160 __asm__ __volatile__(ORO_LOCK_PREFIX "cmpxchgw %w1,%2"
00161 : "=a"(prev)
00162 : "q"(_new), "m"(*oro__xg(ptr)), "0"(old)
00163 : "memory");
00164 return prev;
00165 case 4:
00166 __asm__ __volatile__(ORO_LOCK_PREFIX "cmpxchgl %k1,%2"
00167 : "=a"(prev)
00168 : "q"(_new), "m"(*oro__xg(ptr)), "0"(old)
00169 : "memory");
00170 return prev;
00171 case 8:
00172 __asm__ __volatile__(ORO_LOCK_PREFIX "cmpxchgq %1,%2"
00173 : "=a"(prev)
00174 : "q"(_new), "m"(*oro__xg(ptr)), "0"(old)
00175 : "memory");
00176 return prev;
00177
00178 }
00179 return old;
00180 }
00181
00182 #define oro_cmpxchg(ptr,o,n)\
00183 ((__typeof__(*(ptr)))__oro_cmpxchg((ptr),(unsigned long)(o),\
00184 (unsigned long)(n),sizeof(*(ptr))))
00185
00186 #undef ORO_LOCK_PREFIX
00187 #undef ORO_LOCK
00188 #endif