sub20: sub_if.h Source File

00001 /*
00002 * Internal libsub header file
00003 * Copyright (C) 2008-2009 Alex Kholodenko <sub20@xdimax.net>
00004 * 
00005 * This library is free software; you can redistribute it and/or
00006 * modify it under the terms of the GNU Lesser General Public
00007 * License as published by the Free Software Foundation; either
00008 * version 2.1 of the License, or (at your option) any later version.
00009 * 
00010 * This library is distributed in the hope that it will be useful,
00011 * but WITHOUT ANY WARRANTY; without even the implied warranty of
00012 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00013 * Lesser General Public License for more details.
00014 * 
00015 * You should have received a copy of the GNU Lesser General Public
00016 * License along with this library; if not, write to the Free Software
00017 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
00018 */
00019 
00020 /*
00021 *-------------------------------------------------------------------
00022 * $Id: sub_if.h,v 1.49 2010-08-23 13:55:37 avr32 Exp $
00023 *-------------------------------------------------------------------
00024 */
00025 #ifndef SUB_IF_H_INCLUDED
00026 #define SUB_IF_H_INCLUDED
00027 
00028 
00029 /*
00030 *-----------------------------------------------------------------------------
00031 * Types
00032 *-----------------------------------------------------------------------------
00033 */
00034 
00035 #ifndef AVR
00036  #pragma pack(1)
00037 #endif
00038 typedef struct 
00039 {
00040         uint8_t         code;
00041                 #define SUB_UNKNOWN                     0xFF
00042                 #define SUB_GET_VERSION         0x00
00043                 
00044                 #define SUB_I2C_START           0x10
00045                 #define SUB_I2C_STOP            0x11
00046                 #define SUB_I2C_GENERIC         0x12
00047                 #define SUB_I2C_RDWR            0x14
00048                 #define SUB_I2C_SCAN            0x15
00049                 #define SUB_I2C_FREQ            0x20
00050                 #define SUB_I2C_CONFIG          0x21
00051                 
00052                 #define SUB_SPI_CONFIG          0x40
00053                 #define SUB_SPI_READ            0x41
00054                 #define SUB_SPI_WRITE           0x42
00055                 #define SUB_SPI_RDWR            0x43
00056                 #define SUB_SPI_SDIO_RDWR       0x44
00057                 
00058                 #define SUB_MDIO_XFER           0x48
00059                 
00060                 #define SUB_LCD_WRITE           0x50
00061                 
00062                 #define SUB_ADC_CONFIG          0x58
00063                 #define SUB_ADC_READ            0x59
00064                 
00065                 #define SUB_GPIO_CONFIG         0x60
00066                 #define SUB_GPIO_READ           0x61
00067                 #define SUB_GPIO_WRITE          0x62
00068                 #define SUB_GPIOB_CONFIG        0x63
00069                 #define SUB_GPIOB_READ          0x64
00070                 #define SUB_GPIOB_WRITE         0x65
00071                 #define SUB_FAST_PWM_CONFIG     0x66
00072                 #define SUB_FAST_PWM_SET        0x67
00073                 #define SUB_PWM_CONFIG          0x6C
00074                 #define SUB_PWM_SET                     0x6D
00075                 
00076                 #define SUB_RS_CONFIG           0x68
00077                 #define SUB_RS_TIMING           0x69
00078                 #define SUB_RS_XFER                     0x6A
00079                 
00080                 #define SUB_FIFO_CONFIG         0x70
00081                 
00082                 #define SUB_BB_I2C_START        0x80
00083                 #define SUB_BB_I2C_STOP         0x81
00084                 #define SUB_BB_I2C_CONFIG       0x82
00085                 #define SUB_BB_I2C_SCAN         0x83
00086                 #define SUB_BB_I2C_RDWR         0x84
00087                 
00088                 #define SUB_IR_CONFIG           0x90
00089                 #define SUB_IR_TX                       0x91
00090         
00091     uint8_t             size;
00092 
00093         union
00094         {
00095                 uint8_t         data[0];
00096 
00097                 /* Get Version */
00098                 struct get_version_resp_st
00099                 {
00100                         uint8_t         micro;
00101                         uint8_t         minor;
00102                         uint8_t         major;
00103                         uint8_t         boot;
00104                 }get_version_resp;
00105 
00106                 /* I2C Start */
00107                 struct i2c_start_req_st
00108                 {
00109                         uint8_t         restart;
00110                 }i2c_start_req;
00111 
00112                 struct i2c_start_resp_st
00113                 {
00114                         uint8_t         status;
00115                 }i2c_start_resp;
00116 
00117                 /* I2C Stop */
00118                 struct i2c_stop_resp_st
00119                 {
00120                         uint8_t         status;
00121                 }i2c_stop_resp;
00122 
00123                 /* I2C Generic */
00124                 struct i2c_generic_req_st
00125                 {
00126                         uint8_t         sa;                     /* Slave Address */
00127                         uint8_t         flags;
00128                                 #define __GENF_RESTART  0x01    /* Repeated START */
00129                                 #define __GENF_NOSTOP   0x02    /* No STOP */
00130                                 #define __GENF_NOSLA    0x04    /* Do not issue SLA+R/W */
00131                         uint8_t         sz;                              
00132                         uint8_t         data[0];
00133                 }i2c_generic_req;
00134 
00135                 struct i2c_generic_resp_st
00136                 {
00137                         uint8_t         status;
00138                         uint8_t         data[0];
00139                 }i2c_generic_resp;
00140 
00141                 /* I2C Read/Write */
00142                 struct i2c_rdwr_req_st
00143                 {
00144                         uint8_t         sa;
00145                         uint8_t         flags;          /* __GENF flags are also respected */
00146                         uint8_t         ma_sz;          /* Memory address size */
00147                         uint8_t         sz;                     /* Data szie */
00148                         uint8_t         ma[0];
00149                 }i2c_rdwr_req;
00150 #define SUB_MAX_I2C_READ  (SUB_MAX_PACK-1-offsetof(sub_tag_t,i2c_rdwr_resp.data))
00151 #define SUB_MAX_I2C_WRITE (SUB_MAX_PACK-1-offsetof(sub_tag_t,i2c_rdwr_req.ma))
00152 
00153                 struct i2c_rdwr_resp_st
00154                 {
00155                         uint8_t         status;
00156                         uint8_t         data[0];
00157                 }i2c_rdwr_resp;
00158 
00159                 /* I2C Baud */
00160                 struct i2c_baud_req_st
00161                 {
00162                         uint8_t         twi_TWBR;
00163                         uint8_t         twi_TWPS;
00164                 }i2c_baud_req;
00165                 
00166                 struct i2c_baud_resp_st
00167                 {
00168                         uint8_t         twi_TWBR;
00169                         uint8_t         twi_TWPS;
00170                 }i2c_baud_resp;
00171 
00172                 /* I2C Config */
00173                 struct i2c_config_req_st
00174                 {
00175                         uint8_t         sa;
00176                         uint8_t         flags;
00177 
00178                 }i2c_config_req;
00179 
00180                 /* I2C Scan */
00181                 struct i2c_scan_resp_st
00182                 {
00183                         uint8_t         slave_n;
00184                         uint8_t         slave_buf[0];
00185                 }i2c_scan_resp;
00186 #define SUB_MAX_I2C_SCAN (SUB_MAX_PACK-1-offsetof(sub_tag_t,i2c_scan_resp.slave_buf))
00187 
00188                 /* SPI Config */
00189                 struct spi_config_req_st
00190                 {
00191                         uint8_t         spi_SPCR;
00192                 }spi_config_req;
00193 
00194                 struct spi_config_resp_st
00195                 {
00196                         uint8_t         spi_SPCR;
00197                 }spi_config_resp;
00198 
00199                 /* SPI Read/Write */
00200                 struct spi_rdwr_req_st
00201                 {
00202                         uint8_t         SS_config;
00203                         uint8_t         sz;
00204                         uint8_t         data[0];
00205                 }spi_rdwr_req;
00206 #define SUB_MAX_SPI_RDWR                (SUB_MAX_PACK-1-offsetof(sub_tag_t,spi_rdwr_req.data))
00207 #define SUB_MAX_SPI_RDWR_LONG   (SUB_MAX_PACK_LONG-1-offsetof(sub_tag_t,spi_rdwr_req.data))
00208 
00209                 struct spi_rdwr_resp_st
00210                 {
00211                         uint8_t         sz;
00212                         uint8_t         data[0];
00213                 }spi_rdwr_resp;
00214                 
00215                 /* SPI SDIO rdwr */
00216                 struct spi_sdio_rdwr_req_st
00217                 {
00218                         uint8_t         SS_config;
00219                         uint8_t         out_sz;
00220                         uint8_t         in_sz;
00221                         uint8_t         data[0];
00222                 }spi_sdio_rdwr_req;
00223 #define SUB_MAX_SPI_SDIO_RDWR (SUB_MAX_PACK-1-offsetof(sub_tag_t,spi_sdio_rdwr_req.data))
00224 
00225                 struct spi_sdio_rdwr_resp_st
00226                 {
00227                         uint8_t         in_sz;
00228                         uint8_t         data[0];
00229                 }spi_sdio_rdwr_resp;
00230 
00231                 /* MDIO Xfer */
00232                 struct mdio_xfer_req_st
00233                 {
00234                         uint8_t         n;
00235                         struct mdio_xfer_st
00236                         {
00237                                 uint8_t op_prtad;       /* bit7:Clause22, bit6,5:op, bit4,0:prtad */
00238                                 uint8_t devad;          /* bit6,5:channel */
00239                                 uint8_t data_lo;
00240                                 uint8_t data_hi;
00241                         }xfer[0];
00242                 }mdio_xfer_req;
00243 #define SUB_MAX_MDIO_XFER ((SUB_MAX_PACK-1-offsetof(sub_tag_t,mdio_xfer_req.xfer[0]))/sizeof(struct mdio_xfer_st))
00244 
00245                 /* GPIO */
00246                 struct gpio_req_st
00247                 {
00248                         uint8_t         mask[4];
00249                         uint8_t         val[4];
00250                 }gpio_req;
00251 
00252                 struct gpio_resp_st
00253                 {
00254                         uint8_t         val[4];
00255                 }gpio_resp;
00256 
00257                 /* GPIOB */
00258                 struct gpiob_req_st
00259                 {
00260                         uint8_t         mask;
00261                         uint8_t         val;
00262                 }gpiob_req;
00263 
00264                 struct gpiob_resp_st
00265                 {
00266                         uint8_t         val;
00267                 }gpiob_resp;
00268 
00269                 /* Fast PWM */
00270                 struct fast_pwm_config_req_st
00271                 {
00272                         uint8_t         TCCRA;
00273                         uint8_t         TCCRB;
00274                         uint8_t         TCCRC;
00275                         uint8_t         ICRL;
00276                         uint8_t         ICRH;
00277                 }fast_pwm_config_req;
00278 
00279                 struct fast_pwm_set_req_st
00280                 {
00281                         uint8_t         pwm_n;
00282                         uint8_t         duty_lo;
00283                         uint8_t         duty_hi;
00284                 }fast_pwm_set_req;
00285 
00286                 /* PWM */
00287                 struct pwm_config_req_st
00288                 {
00289                         uint8_t         TCCRA;
00290                         uint8_t         TCCRB;
00291                         uint8_t         OCRA;
00292                         uint8_t         limit;
00293                 }pwm_config_req;
00294 
00295                 struct pwm_set_req_st
00296                 {
00297                         uint8_t         pwm_n;
00298                         uint8_t         duty;
00299                 }pwm_set_req;
00300 
00301                 /* ADC */
00302                 struct adc_config_req_st
00303                 {
00304                         uint8_t         admux;
00305                         uint8_t         adcsra;
00306                 }adc_config_req;
00307 
00308                 struct adc_read_req_st
00309                 {
00310                         uint8_t         reads;
00311 #define MAX_ADC_READS 30
00312                         uint8_t         mux[0];
00313                 }adc_read_req;
00314                 struct adc_read_resp_st
00315                 {
00316                         uint8_t         reads;
00317                         uint8_t         adc_lh[0];
00318                 }adc_read_resp;
00319 
00320                 /* LCD */
00321                 struct LCD_write_req_st
00322                 {
00323         #define SUB_MAX_LCD_STR 60
00324                         char            str[SUB_MAX_LCD_STR];
00325                 }LCD_write_req;
00326 
00327                 struct LCD_write_resp_st
00328                 {
00329                         uint8_t         status;
00330                                 #define __LCD_NOT_SUPPORTED     0xFF
00331                 }LCD_write_resp;
00332 
00333                 /* RS232/RS485 */
00334                 struct RS_config_req_st
00335                 {
00336                         uint8_t         UCSRC;
00337                         uint8_t         UBRRL;
00338                         uint8_t         UBRRH;
00339                 }RS_config_req;
00340 
00341                 struct RS_config_resp_st
00342                 {
00343                         uint8_t         UCSRC;
00344                         uint8_t         UBRRL;
00345                         uint8_t         UBRRH;
00346                 }RS_config_resp;
00347 
00348                 struct RS_timing_req_st
00349                 {
00350                         uint8_t         flags;
00351                         uint16_t        tx_space;               /* LSB first */
00352                         uint16_t        rx_msg_to;
00353                         uint16_t        rx_byte_to;
00354                 }RS_timing_req;
00355 
00356                 struct RS_xfer_req_st
00357                 {
00358                         uint8_t         rx_sz;
00359                         uint8_t         tx_buf[0];
00360                 }RS_xfer_req;
00361 
00362                 struct RS_xfer_resp_st
00363                 {
00364                         uint8_t         rx_sz;
00365                         uint8_t         rx_buf[0];
00366                 }RS_xfer_resp;
00367 #define SUB_MAX_RS_XFER (SUB_MAX_PACK-1-offsetof(sub_tag_t,RX_xfer_req.tx_buf))
00368 
00369                 /* FIFO */
00370                 struct FIFO_config_req_st
00371                 {
00372                         uint8_t         selector;
00373                         uint8_t         flags;
00374                 }FIFO_config_req;
00375 
00376                 /* BB I2C Start */
00377                 struct bb_i2c_start_req_st
00378                 {
00379                         uint8_t         channel;
00380                         uint8_t         restart;
00381                 }bb_i2c_start_req;
00382 
00383                 struct bb_i2c_start_resp_st
00384                 {
00385                         uint8_t         status;
00386                 }bb_i2c_start_resp;
00387 
00388                 /* BB I2C Stop */
00389                 struct bb_i2c_stop_req_st
00390                 {
00391                         uint8_t         channel;
00392                 }bb_i2c_stop_req;
00393 
00394                 struct bb_i2c_stop_resp_st
00395                 {
00396                         uint8_t         status;
00397                 }bb_i2c_stop_resp;
00398 
00399                 /* BB I2C Read/Write */
00400                 struct bb_i2c_rdwr_req_st
00401                 {
00402                         uint8_t         channel;
00403                         uint8_t         sa;
00404                         uint8_t         flags;          /* __GENF flags are also respected */
00405                         uint8_t         ma_sz;          /* Memory address size */
00406                         uint8_t         sz;                     /* Data szie */
00407                         uint8_t         ma[0];
00408                 }bb_i2c_rdwr_req;
00409 #define SUB_MAX_BB_I2C_READ  (SUB_MAX_PACK_LONG-1-offsetof(sub_tag_t,bb_i2c_rdwr_resp.data))
00410 #define SUB_MAX_BB_I2C_WRITE (SUB_MAX_PACK_LONG-1-offsetof(sub_tag_t,bb_i2c_rdwr_req.ma))
00411 
00412                 struct bb_i2c_rdwr_resp_st
00413                 {
00414                         uint8_t         status;
00415                         uint8_t         data[0];
00416                 }bb_i2c_rdwr_resp;
00417 
00418                 /* BB I2C Config */
00419                 struct bb_i2c_config_req_st
00420                 {
00421                         uint8_t         mode;
00422                         uint8_t         stretch;
00423                 }bb_i2c_config_req;
00424                 
00425                 /* BB I2C Scan */
00426                 struct bb_i2c_scan_req_st
00427                 {
00428                         uint8_t         channel;
00429                 }bb_i2c_scan_req;
00430 
00431                 /* IR Config */
00432                 struct ir_config_req_st
00433                 {
00434                         uint8_t         ICRL;   
00435                         uint8_t         ICRH;           /* Fcarrier = 16MHz/(ICR+1) */
00436                         uint8_t         OCRL;
00437                         uint8_t         OCRH;       /* Carrier duty = OCR/ICR */ 
00438                         uint8_t         mode;
00439                         union ir_config_mode_un
00440                         {
00441                                 struct
00442                                 {
00443                                         uint8_t pp_bit; /* Carrier pulses per bit */
00444                                 }uart_mode;
00445                                 struct
00446                                 {
00447                                         uint8_t pp_bit; /* Carrier pulses per bit */
00448                                 }row_mode;
00449                         }ir_config_mode;
00450                 }ir_config_req;
00451 
00452                 /* IR Tx */
00453                 struct ir_tx_req_st
00454                 {
00455                         uint8_t         sz;
00456                         uint8_t         buf[0];
00457                 }ir_tx_req;
00458 #define SUB_MAX_IR_TX  (SUB_MAX_PACK_LONG-1-offsetof(sub_tag_t,ir_tx_req.buf))
00459                 struct ir_tx_resp_st
00460                 {
00461                         uint8_t         status;
00462                 }ir_tx_resp;
00463         };
00464 }sub_tag_t;
00465 
00466 
00467 /*
00468 *-----------------------------------------------------------------------------
00469 * Constants
00470 *-----------------------------------------------------------------------------
00471 */
00472 
00473 /* Vendor Specific Control Request wIndex */
00474 #define SUB_VENDOR_REQUEST      0x80
00475  #define SUB_WINDEX_BOOT                0x00
00476  #define SUB_WINDEX_MODE                0x01
00477  #define SUB_WINDEX_VER                 0x02
00478  #define SUB_WINDEX_CFG_VPD             0x03
00479 
00480 /* Vendor requests in boot mode */
00481 #define SUB_BOOT_WRITE_NVRAM    1
00482 
00483 #define SUB_MAX_PACK            64
00484 #define SUB_MAX_PACK_LONG       256
00485 
00486 /*
00487 * I2C Status
00488 */
00489 #define __I2C_START     0x08    /* A START condition transmitted                        */
00490 #define __I2C_RESTART   0x10    /* A repeated START condition transmitted       */
00491 #define __I2C_SLAW_ACK  0x18    /* SLA+W transmitted; ACK received                      */
00492 #define __I2C_SLAW_NAK  0x20    /* SLA+W transmitted; NAK received                      */
00493 #define __I2C_DATA_ACK  0x28    /* Data byte transmitted; ACK received          */
00494 #define __I2C_DATA_NAK  0x30    /* Data byte transmitted; NAK received          */
00495 #define __I2C_SLA_ARB   0x38    /* Arbitration lost in SLA or NAK received      */
00496 #define __I2C_SLAR_ACK  0x40    /* SLA+R transmitted; ACK received                      */ 
00497 #define __I2C_SLAR_NAK  0x48    /* SLA+R transmitted; NAK received                      */
00498 #define __I2C_READ_ACK  0x50    /* Data received; ACK has been returned         */
00499 #define __I2C_READ_NAK  0x58    /* Data received; NAK has been returned         */
00500 
00501 #define __I2C_WAIT_TO   0xE0    /* Arbitration lost                                                     */
00502 #define __I2C_START_TO  0xE1    /* Arbitration lost in START                            */
00503 #define __I2C_STOP_TO   0xE2    /* Arbitration lost in STOP                                     */
00504 #define __I2C_READ_ACK_TO 0xE3  /* Arbitration lost in read ACK                         */
00505 #define __I2C_READ_NAK_TO 0xE4  /* Arbitration lost in read NAK                         */
00506 #define __I2C_WRITE_TO  0xE5    /* Arbitration lost in write                            */
00507 #define __I2C_ERROR             0xF8    /* Unknown error                                                        */
00508 #define __I2C_ILLEGAL   0xFF    /* Illegal START or STOP condition                      */
00509 
00510 #endif /*_H_INCLUDED*/
00511