#include <stm32h747xx.h>
Public Attributes | |
| __IO uint32_t | ADC1R |
| __IO uint32_t | ADC2R |
| __IO uint32_t | ADC3R |
| __IO uint32_t | ADC4R |
| __IO uint32_t | BDMADR |
| __IO uint32_t | BDMUPR |
| __IO uint32_t | BDTAUPR |
| __IO uint32_t | BDTBUPR |
| __IO uint32_t | BDTCUPR |
| __IO uint32_t | BDTDUPR |
| __IO uint32_t | BDTEUPR |
| __IO uint32_t | BMCMPR |
| __IO uint32_t | BMCR |
| __IO uint32_t | BMPER |
| __IO uint32_t | BMTRGR |
| __IO uint32_t | CR1 |
| __IO uint32_t | CR2 |
| __IO uint32_t | EECR1 |
| __IO uint32_t | EECR2 |
| __IO uint32_t | EECR3 |
| __IO uint32_t | FLTINR1 |
| __IO uint32_t | FLTINR2 |
| __IO uint32_t | ICR |
| __IO uint32_t | IER |
| __IO uint32_t | ISR |
| __IO uint32_t | ODISR |
| __IO uint32_t | ODSR |
| __IO uint32_t | OENR |
| __IO uint32_t | RESERVED0 |
Definition at line 1864 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::ADC1R |
HRTIM ADC Trigger 1 register, Address offset: 0x3C
Definition at line 1881 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::ADC2R |
HRTIM ADC Trigger 2 register, Address offset: 0x40
Definition at line 1882 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::ADC3R |
HRTIM ADC Trigger 3 register, Address offset: 0x44
Definition at line 1883 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::ADC4R |
HRTIM ADC Trigger 4 register, Address offset: 0x48
Definition at line 1884 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BDMADR |
HRTIM Burst DMA Master Data register, Address offset: 0x70
Definition at line 1894 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BDMUPR |
HRTIM Burst DMA Master Timer update register, Address offset: 0x58
Definition at line 1888 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BDTAUPR |
HRTIM Burst DMA Timerx update register, Address offset: 0x5C
Definition at line 1889 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BDTBUPR |
HRTIM Burst DMA Timerx update register, Address offset: 0x60
Definition at line 1890 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BDTCUPR |
HRTIM Burst DMA Timerx update register, Address offset: 0x64
Definition at line 1891 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BDTDUPR |
HRTIM Burst DMA Timerx update register, Address offset: 0x68
Definition at line 1892 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BDTEUPR |
HRTIM Burst DMA Timerx update register, Address offset: 0x6C
Definition at line 1893 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BMCMPR |
HRTIM Burst mode compare register, Address offset: 0x28
Definition at line 1876 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BMCR |
HRTIM Burst mode control register, Address offset: 0x20
Definition at line 1874 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BMPER |
HRTIM Burst mode period register, Address offset: 0x2C
Definition at line 1877 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::BMTRGR |
HRTIM Busrt mode trigger register, Address offset: 0x24
Definition at line 1875 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::CR1 |
HRTIM control register1, Address offset: 0x00
Definition at line 1866 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::CR2 |
HRTIM control register2, Address offset: 0x04
Definition at line 1867 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::EECR1 |
HRTIM Timer external event control register1, Address offset: 0x30
Definition at line 1878 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::EECR2 |
HRTIM Timer external event control register2, Address offset: 0x34
Definition at line 1879 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::EECR3 |
HRTIM Timer external event control register3, Address offset: 0x38
Definition at line 1880 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::FLTINR1 |
HRTIM Fault input register1, Address offset: 0x50
Definition at line 1886 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::FLTINR2 |
HRTIM Fault input register2, Address offset: 0x54
Definition at line 1887 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::ICR |
HRTIM interrupt clear register, Address offset: 0x0C
Definition at line 1869 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::IER |
HRTIM interrupt enable register, Address offset: 0x10
Definition at line 1870 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::ISR |
HRTIM interrupt status register, Address offset: 0x08
Definition at line 1868 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::ODISR |
HRTIM Output disable register, Address offset: 0x18
Definition at line 1872 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::ODSR |
HRTIM Output disable status register, Address offset: 0x1C
Definition at line 1873 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::OENR |
HRTIM Output enable register, Address offset: 0x14
Definition at line 1871 of file stm32h747xx.h.
| __IO uint32_t HRTIM_Common_TypeDef::RESERVED0 |
Reserved, Address offset: 0x4C
Definition at line 1885 of file stm32h747xx.h.