stm32h7xx_hal_spi.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_SPI_H
22 #define STM32H7xx_HAL_SPI_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t Mode;
52  uint32_t Direction;
55  uint32_t DataSize;
58  uint32_t CLKPolarity;
61  uint32_t CLKPhase;
64  uint32_t NSS;
68  uint32_t BaudRatePrescaler;
74  uint32_t FirstBit;
77  uint32_t TIMode;
80  uint32_t CRCCalculation;
83  uint32_t CRCPolynomial;
86  uint32_t CRCLength;
89  uint32_t NSSPMode;
95  uint32_t NSSPolarity;
99  uint32_t FifoThreshold;
102  uint32_t TxCRCInitializationPattern;
105  uint32_t RxCRCInitializationPattern;
108  uint32_t MasterSSIdleness;
112  uint32_t MasterInterDataIdleness;
116  uint32_t MasterReceiverAutoSusp;
120  uint32_t MasterKeepIOState;
123  uint32_t IOSwap;
126 } SPI_InitTypeDef;
127 
131 typedef enum
132 {
133  HAL_SPI_STATE_RESET = 0x00UL,
134  HAL_SPI_STATE_READY = 0x01UL,
135  HAL_SPI_STATE_BUSY = 0x02UL,
136  HAL_SPI_STATE_BUSY_TX = 0x03UL,
137  HAL_SPI_STATE_BUSY_RX = 0x04UL,
138  HAL_SPI_STATE_BUSY_TX_RX = 0x05UL,
139  HAL_SPI_STATE_ERROR = 0x06UL,
140  HAL_SPI_STATE_ABORT = 0x07UL
141 } HAL_SPI_StateTypeDef;
142 
143 #if defined(USE_SPI_RELOAD_TRANSFER)
144 
147 typedef struct
148 {
149  uint8_t *pTxBuffPtr;
151  uint16_t TxXferSize;
153  uint8_t *pRxBuffPtr;
155  uint16_t RxXferSize;
157  uint32_t Requested;
159 } SPI_ReloadTypeDef;
160 #endif /* USE_HSPI_RELOAD_TRANSFER */
161 
165 typedef struct __SPI_HandleTypeDef
166 {
167  SPI_TypeDef *Instance;
169  SPI_InitTypeDef Init;
171  uint8_t *pTxBuffPtr;
173  uint16_t TxXferSize;
175  __IO uint16_t TxXferCount;
177  uint8_t *pRxBuffPtr;
179  uint16_t RxXferSize;
181  __IO uint16_t RxXferCount;
183  uint32_t CRCSize;
185  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);
187  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);
189  DMA_HandleTypeDef *hdmatx;
191  DMA_HandleTypeDef *hdmarx;
193  HAL_LockTypeDef Lock;
195  __IO HAL_SPI_StateTypeDef State;
197  __IO uint32_t ErrorCode;
199 #if defined(USE_SPI_RELOAD_TRANSFER)
200 
201  SPI_ReloadTypeDef Reload;
203 #endif /* USE_HSPI_RELOAD_TRANSFER */
204 
205 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
206  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);
207  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);
208  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);
209  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);
210  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);
211  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);
212  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);
213  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);
214  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);
215  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);
217 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
218 } SPI_HandleTypeDef;
219 
220 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
221 
224 typedef enum
225 {
226  HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL,
227  HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL,
228  HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL,
229  HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL,
230  HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL,
231  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL,
232  HAL_SPI_ERROR_CB_ID = 0x06UL,
233  HAL_SPI_ABORT_CB_ID = 0x07UL,
234  HAL_SPI_MSPINIT_CB_ID = 0x08UL,
235  HAL_SPI_MSPDEINIT_CB_ID = 0x09UL
237 } HAL_SPI_CallbackIDTypeDef;
238 
242 typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi);
244 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
245 
249 /* Exported constants --------------------------------------------------------*/
250 
258 #define SPI_LOWEND_FIFO_SIZE 8UL
259 #define SPI_HIGHEND_FIFO_SIZE 16UL
260 
267 #define HAL_SPI_ERROR_NONE (0x00000000UL)
268 #define HAL_SPI_ERROR_MODF (0x00000001UL)
269 #define HAL_SPI_ERROR_CRC (0x00000002UL)
270 #define HAL_SPI_ERROR_OVR (0x00000004UL)
271 #define HAL_SPI_ERROR_FRE (0x00000008UL)
272 #define HAL_SPI_ERROR_DMA (0x00000010UL)
273 #define HAL_SPI_ERROR_FLAG (0x00000020UL)
274 #define HAL_SPI_ERROR_ABORT (0x00000040UL)
275 #define HAL_SPI_ERROR_UDR (0x00000080UL)
276 #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL)
277 #define HAL_SPI_ERROR_UNKNOW (0x00000200UL)
278 #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL)
279 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
280 #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000800UL)
281 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
282 
289 #define SPI_MODE_SLAVE (0x00000000UL)
290 #define SPI_MODE_MASTER SPI_CFG2_MASTER
291 
298 #define SPI_DIRECTION_2LINES (0x00000000UL)
299 #define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
300 #define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
301 #define SPI_DIRECTION_1LINE SPI_CFG2_COMM
302 
309 #define SPI_DATASIZE_4BIT (0x00000003UL)
310 #define SPI_DATASIZE_5BIT (0x00000004UL)
311 #define SPI_DATASIZE_6BIT (0x00000005UL)
312 #define SPI_DATASIZE_7BIT (0x00000006UL)
313 #define SPI_DATASIZE_8BIT (0x00000007UL)
314 #define SPI_DATASIZE_9BIT (0x00000008UL)
315 #define SPI_DATASIZE_10BIT (0x00000009UL)
316 #define SPI_DATASIZE_11BIT (0x0000000AUL)
317 #define SPI_DATASIZE_12BIT (0x0000000BUL)
318 #define SPI_DATASIZE_13BIT (0x0000000CUL)
319 #define SPI_DATASIZE_14BIT (0x0000000DUL)
320 #define SPI_DATASIZE_15BIT (0x0000000EUL)
321 #define SPI_DATASIZE_16BIT (0x0000000FUL)
322 #define SPI_DATASIZE_17BIT (0x00000010UL)
323 #define SPI_DATASIZE_18BIT (0x00000011UL)
324 #define SPI_DATASIZE_19BIT (0x00000012UL)
325 #define SPI_DATASIZE_20BIT (0x00000013UL)
326 #define SPI_DATASIZE_21BIT (0x00000014UL)
327 #define SPI_DATASIZE_22BIT (0x00000015UL)
328 #define SPI_DATASIZE_23BIT (0x00000016UL)
329 #define SPI_DATASIZE_24BIT (0x00000017UL)
330 #define SPI_DATASIZE_25BIT (0x00000018UL)
331 #define SPI_DATASIZE_26BIT (0x00000019UL)
332 #define SPI_DATASIZE_27BIT (0x0000001AUL)
333 #define SPI_DATASIZE_28BIT (0x0000001BUL)
334 #define SPI_DATASIZE_29BIT (0x0000001CUL)
335 #define SPI_DATASIZE_30BIT (0x0000001DUL)
336 #define SPI_DATASIZE_31BIT (0x0000001EUL)
337 #define SPI_DATASIZE_32BIT (0x0000001FUL)
338 
345 #define SPI_POLARITY_LOW (0x00000000UL)
346 #define SPI_POLARITY_HIGH SPI_CFG2_CPOL
347 
354 #define SPI_PHASE_1EDGE (0x00000000UL)
355 #define SPI_PHASE_2EDGE SPI_CFG2_CPHA
356 
363 #define SPI_NSS_SOFT SPI_CFG2_SSM
364 #define SPI_NSS_HARD_INPUT (0x00000000UL)
365 #define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
366 
373 #define SPI_NSS_PULSE_DISABLE (0x00000000UL)
374 #define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
375 
382 #define SPI_BAUDRATEPRESCALER_2 (0x00000000UL)
383 #define SPI_BAUDRATEPRESCALER_4 (0x10000000UL)
384 #define SPI_BAUDRATEPRESCALER_8 (0x20000000UL)
385 #define SPI_BAUDRATEPRESCALER_16 (0x30000000UL)
386 #define SPI_BAUDRATEPRESCALER_32 (0x40000000UL)
387 #define SPI_BAUDRATEPRESCALER_64 (0x50000000UL)
388 #define SPI_BAUDRATEPRESCALER_128 (0x60000000UL)
389 #define SPI_BAUDRATEPRESCALER_256 (0x70000000UL)
390 
397 #define SPI_FIRSTBIT_MSB (0x00000000UL)
398 #define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
399 
406 #define SPI_TIMODE_DISABLE (0x00000000UL)
407 #define SPI_TIMODE_ENABLE SPI_CFG2_SP_0
408 
415 #define SPI_CRCCALCULATION_DISABLE (0x00000000UL)
416 #define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
417 
424 #define SPI_CRC_LENGTH_DATASIZE (0x00000000UL)
425 #define SPI_CRC_LENGTH_4BIT (0x00030000UL)
426 #define SPI_CRC_LENGTH_5BIT (0x00040000UL)
427 #define SPI_CRC_LENGTH_6BIT (0x00050000UL)
428 #define SPI_CRC_LENGTH_7BIT (0x00060000UL)
429 #define SPI_CRC_LENGTH_8BIT (0x00070000UL)
430 #define SPI_CRC_LENGTH_9BIT (0x00080000UL)
431 #define SPI_CRC_LENGTH_10BIT (0x00090000UL)
432 #define SPI_CRC_LENGTH_11BIT (0x000A0000UL)
433 #define SPI_CRC_LENGTH_12BIT (0x000B0000UL)
434 #define SPI_CRC_LENGTH_13BIT (0x000C0000UL)
435 #define SPI_CRC_LENGTH_14BIT (0x000D0000UL)
436 #define SPI_CRC_LENGTH_15BIT (0x000E0000UL)
437 #define SPI_CRC_LENGTH_16BIT (0x000F0000UL)
438 #define SPI_CRC_LENGTH_17BIT (0x00100000UL)
439 #define SPI_CRC_LENGTH_18BIT (0x00110000UL)
440 #define SPI_CRC_LENGTH_19BIT (0x00120000UL)
441 #define SPI_CRC_LENGTH_20BIT (0x00130000UL)
442 #define SPI_CRC_LENGTH_21BIT (0x00140000UL)
443 #define SPI_CRC_LENGTH_22BIT (0x00150000UL)
444 #define SPI_CRC_LENGTH_23BIT (0x00160000UL)
445 #define SPI_CRC_LENGTH_24BIT (0x00170000UL)
446 #define SPI_CRC_LENGTH_25BIT (0x00180000UL)
447 #define SPI_CRC_LENGTH_26BIT (0x00190000UL)
448 #define SPI_CRC_LENGTH_27BIT (0x001A0000UL)
449 #define SPI_CRC_LENGTH_28BIT (0x001B0000UL)
450 #define SPI_CRC_LENGTH_29BIT (0x001C0000UL)
451 #define SPI_CRC_LENGTH_30BIT (0x001D0000UL)
452 #define SPI_CRC_LENGTH_31BIT (0x001E0000UL)
453 #define SPI_CRC_LENGTH_32BIT (0x001F0000UL)
454 
461 #define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL)
462 #define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL)
463 #define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL)
464 #define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL)
465 #define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL)
466 #define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL)
467 #define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL)
468 #define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL)
469 #define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL)
470 #define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL)
471 #define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL)
472 #define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL)
473 #define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL)
474 #define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL)
475 #define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL)
476 #define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL)
477 
484 #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL)
485 #define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL)
486 
493 #define SPI_NSS_POLARITY_LOW (0x00000000UL)
494 #define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
495 
502 #define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL)
503 #define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
504 
511 #define SPI_IO_SWAP_DISABLE (0x00000000UL)
512 #define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
513 
520 #define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL)
521 #define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL)
522 #define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL)
523 #define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL)
524 #define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL)
525 #define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL)
526 #define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL)
527 #define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL)
528 #define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL)
529 #define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL)
530 #define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL)
531 #define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL)
532 #define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL)
533 #define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL)
534 #define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL)
535 #define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL)
536 
543 #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL)
544 #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL)
545 #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL)
546 #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL)
547 #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL)
548 #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL)
549 #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL)
550 #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL)
551 #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL)
552 #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL)
553 #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL)
554 #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL)
555 #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL)
556 #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL)
557 #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL)
558 #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL)
559 
566 #define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL)
567 #define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
568 
575 #define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
576 #define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
577 #define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
578 
585 #define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL)
586 #define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
587 #define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
588 
595 #define SPI_IT_RXP SPI_IER_RXPIE
596 #define SPI_IT_TXP SPI_IER_TXPIE
597 #define SPI_IT_DXP SPI_IER_DXPIE
598 #define SPI_IT_EOT SPI_IER_EOTIE
599 #define SPI_IT_TXTF SPI_IER_TXTFIE
600 #define SPI_IT_UDR SPI_IER_UDRIE
601 #define SPI_IT_OVR SPI_IER_OVRIE
602 #define SPI_IT_CRCERR SPI_IER_CRCEIE
603 #define SPI_IT_FRE SPI_IER_TIFREIE
604 #define SPI_IT_MODF SPI_IER_MODFIE
605 #define SPI_IT_TSERF SPI_IER_TSERFIE
606 #define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)
607 
614 #define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */
615 #define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */
616 #define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */
617 #define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */
618 #define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */
619 #define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */
620 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */
621 #define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */
622 #define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */
623 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */
624 #define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */
625 #define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */
626 #define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */
627 #define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */
628 #define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */
629 
636 #define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */
637 #define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
638 #define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
639 #define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
640 
648 /* Exported macros -----------------------------------------------------------*/
658 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)
659 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
660  (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
661  (__HANDLE__)->MspInitCallback = NULL; \
662  (__HANDLE__)->MspDeInitCallback = NULL; \
663  } while(0)
664 #else
665 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
666 #endif
667 
687 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
688 
708 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
709 
729 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
730 
753 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
754 
759 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
760 
765 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
766 
771 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
772 
777 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
778 
783 #define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
784 
789 #define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
790 
795 #define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
796 
801 #define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
802 
807 #define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)
808 
813 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
814 
819 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
820 
825 /* Include SPI HAL Extension module */
826 #include "stm32h7xx_hal_spi_ex.h"
827 
828 
829 /* Exported functions --------------------------------------------------------*/
837 /* Initialization/de-initialization functions ********************************/
838 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
839 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
840 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
841 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
842 
843 /* Callbacks Register/UnRegister functions ***********************************/
844 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
845 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
846 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
847 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
848 
855 /* I/O operation functions ***************************************************/
856 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
857 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
858 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
859  uint32_t Timeout);
860 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
861 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
862 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
863 
864 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
865 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
866 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
867 
868 #if defined(USE_SPI_RELOAD_TRANSFER)
869 HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
870 HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
871 HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
872 #endif /* USE_HSPI_RELOAD_TRANSFER */
873 
874 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
875 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
876 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
877 
878 /* Transfer Abort functions */
879 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
880 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
881 
882 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
883 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
884 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
885 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
886 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
887 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
888 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
889 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
890 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
899 /* Peripheral State and Error functions ***************************************/
900 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
901 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
910 /* Private macros ------------------------------------------------------------*/
920 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
921 
927 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
928 
929 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
930  ((MODE) == SPI_MODE_MASTER))
931 
932 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
933  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
934  ((MODE) == SPI_DIRECTION_1LINE) || \
935  ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
936 
937 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
938 
939 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \
940  ((MODE) == SPI_DIRECTION_2LINES)|| \
941  ((MODE) == SPI_DIRECTION_1LINE) || \
942  ((MODE) == SPI_DIRECTION_2LINES_TXONLY))
943 
944 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \
945  ((MODE) == SPI_DIRECTION_2LINES)|| \
946  ((MODE) == SPI_DIRECTION_1LINE) || \
947  ((MODE) == SPI_DIRECTION_2LINES_RXONLY))
948 
949 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
950  ((DATASIZE) == SPI_DATASIZE_31BIT) || \
951  ((DATASIZE) == SPI_DATASIZE_30BIT) || \
952  ((DATASIZE) == SPI_DATASIZE_29BIT) || \
953  ((DATASIZE) == SPI_DATASIZE_28BIT) || \
954  ((DATASIZE) == SPI_DATASIZE_27BIT) || \
955  ((DATASIZE) == SPI_DATASIZE_26BIT) || \
956  ((DATASIZE) == SPI_DATASIZE_25BIT) || \
957  ((DATASIZE) == SPI_DATASIZE_24BIT) || \
958  ((DATASIZE) == SPI_DATASIZE_23BIT) || \
959  ((DATASIZE) == SPI_DATASIZE_22BIT) || \
960  ((DATASIZE) == SPI_DATASIZE_21BIT) || \
961  ((DATASIZE) == SPI_DATASIZE_20BIT) || \
962  ((DATASIZE) == SPI_DATASIZE_22BIT) || \
963  ((DATASIZE) == SPI_DATASIZE_19BIT) || \
964  ((DATASIZE) == SPI_DATASIZE_18BIT) || \
965  ((DATASIZE) == SPI_DATASIZE_17BIT) || \
966  ((DATASIZE) == SPI_DATASIZE_16BIT) || \
967  ((DATASIZE) == SPI_DATASIZE_15BIT) || \
968  ((DATASIZE) == SPI_DATASIZE_14BIT) || \
969  ((DATASIZE) == SPI_DATASIZE_13BIT) || \
970  ((DATASIZE) == SPI_DATASIZE_12BIT) || \
971  ((DATASIZE) == SPI_DATASIZE_11BIT) || \
972  ((DATASIZE) == SPI_DATASIZE_10BIT) || \
973  ((DATASIZE) == SPI_DATASIZE_9BIT) || \
974  ((DATASIZE) == SPI_DATASIZE_8BIT) || \
975  ((DATASIZE) == SPI_DATASIZE_7BIT) || \
976  ((DATASIZE) == SPI_DATASIZE_6BIT) || \
977  ((DATASIZE) == SPI_DATASIZE_5BIT) || \
978  ((DATASIZE) == SPI_DATASIZE_4BIT))
979 
980 #define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
981  ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
982  ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
983  ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
984  ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
985  ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
986  ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
987  ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
988  ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
989  ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
990  ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
991  ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
992  ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
993  ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
994  ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
995  ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
996 
997 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
998  ((CPOL) == SPI_POLARITY_HIGH))
999 
1000 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
1001  ((CPHA) == SPI_PHASE_2EDGE))
1002 
1003 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
1004  ((NSS) == SPI_NSS_HARD_INPUT) || \
1005  ((NSS) == SPI_NSS_HARD_OUTPUT))
1006 
1007 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
1008  ((NSSP) == SPI_NSS_PULSE_DISABLE))
1009 
1010 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
1011  ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
1012  ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
1013  ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
1014  ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
1015  ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
1016  ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
1017  ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
1018 
1019 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
1020  ((BIT) == SPI_FIRSTBIT_LSB))
1021 
1022 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
1023  ((MODE) == SPI_TIMODE_ENABLE))
1024 
1025 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
1026  ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
1027 
1028 #define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
1029  ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
1030 
1031 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \
1032  ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \
1033  ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \
1034  ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \
1035  ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \
1036  ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \
1037  ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \
1038  ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \
1039  ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \
1040  ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \
1041  ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \
1042  ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \
1043  ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \
1044  ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \
1045  ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \
1046  ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \
1047  ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \
1048  ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \
1049  ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \
1050  ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \
1051  ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \
1052  ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \
1053  ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \
1054  ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \
1055  ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \
1056  ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
1057  ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \
1058  ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \
1059  ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \
1060  ((LENGTH) == SPI_CRC_LENGTH_4BIT))
1061 
1062 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1UL)
1063 
1064 #define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
1065  ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
1066  ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
1067 
1068 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
1069  ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \
1070  ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
1071 
1083 #ifdef __cplusplus
1084 }
1085 #endif
1086 
1087 #endif /* STM32H7xx_HAL_SPI_H */
1088 
1092 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HAL_SPI_AbortCpltCallback
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
HAL_SPI_DMAResume
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
HAL_SPI_STATE_ERROR
@ HAL_SPI_STATE_ERROR
Definition: stm32h7xx_hal_spi.h:139
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f407xx.h:711
__SPI_HandleTypeDef::Init
SPI_InitTypeDef Init
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:109
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
SPI_InitTypeDef::TxCRCInitializationPattern
uint32_t TxCRCInitializationPattern
Definition: stm32h7xx_hal_spi.h:102
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:40
HAL_SPI_Receive_IT
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
HAL_SPI_Transmit_IT
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:139
HAL_SPI_RxCpltCallback
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
SPI_InitTypeDef::RxCRCInitializationPattern
uint32_t RxCRCInitializationPattern
Definition: stm32h7xx_hal_spi.h:105
HAL_SPI_MspDeInit
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
SPI_HandleTypeDef
struct __SPI_HandleTypeDef SPI_HandleTypeDef
SPI handle Structure definition.
HAL_SPI_Transmit
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
SPI_InitTypeDef::MasterReceiverAutoSusp
uint32_t MasterReceiverAutoSusp
Definition: stm32h7xx_hal_spi.h:116
__SPI_HandleTypeDef::TxISR
void(* TxISR)(struct __SPI_HandleTypeDef *hspi)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:125
__SPI_HandleTypeDef
SPI handle Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:105
__SPI_HandleTypeDef::pTxBuffPtr
uint8_t * pTxBuffPtr
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:111
HAL_SPI_DMAStop
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
HAL_SPI_STATE_BUSY_RX
@ HAL_SPI_STATE_BUSY_RX
Definition: stm32h7xx_hal_spi.h:137
stm32h7xx_hal_spi_ex.h
Header file of SPI HAL Extended module.
SPI_InitTypeDef::NSSPolarity
uint32_t NSSPolarity
Definition: stm32h7xx_hal_spi.h:95
HAL_SPI_IRQHandler
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:51
__SPI_HandleTypeDef::RxXferSize
uint16_t RxXferSize
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:119
__SPI_HandleTypeDef::Instance
SPI_TypeDef * Instance
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:107
HAL_SPI_Abort
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
SPI_InitTypeDef
SPI Configuration Structure definition.
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:47
__SPI_HandleTypeDef::hdmatx
DMA_HandleTypeDef * hdmatx
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:127
HAL_SPI_STATE_ABORT
@ HAL_SPI_STATE_ABORT
Definition: stm32h7xx_hal_spi.h:140
HAL_SPI_TransmitReceive_DMA
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
SPI_InitTypeDef::MasterSSIdleness
uint32_t MasterSSIdleness
Definition: stm32h7xx_hal_spi.h:108
__SPI_HandleTypeDef::RxXferCount
__IO uint16_t RxXferCount
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:121
HAL_SPI_TxCpltCallback
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
HAL_SPI_STATE_BUSY
@ HAL_SPI_STATE_BUSY
Definition: stm32h7xx_hal_spi.h:135
HAL_SPI_ErrorCallback
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
HAL_SPI_TxRxCpltCallback
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
__SPI_HandleTypeDef::RxISR
void(* RxISR)(struct __SPI_HandleTypeDef *hspi)
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:123
__SPI_HandleTypeDef::TxXferSize
uint16_t TxXferSize
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:113
HAL_SPI_TxRxHalfCpltCallback
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
HAL_SPI_STATE_RESET
@ HAL_SPI_STATE_RESET
Definition: stm32h7xx_hal_spi.h:133
__SPI_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:135
HAL_SPI_STATE_BUSY_TX_RX
@ HAL_SPI_STATE_BUSY_TX_RX
Definition: stm32h7xx_hal_spi.h:138
__SPI_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:131
SPI_InitTypeDef::MasterInterDataIdleness
uint32_t MasterInterDataIdleness
Definition: stm32h7xx_hal_spi.h:112
__SPI_HandleTypeDef::TxXferCount
__IO uint16_t TxXferCount
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:115
HAL_SPI_Transmit_DMA
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
HAL_SPI_GetState
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
HAL_SPI_GetError
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
__SPI_HandleTypeDef::pRxBuffPtr
uint8_t * pRxBuffPtr
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:117
__SPI_HandleTypeDef::State
__IO HAL_SPI_StateTypeDef State
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:133
HAL_SPI_Receive_DMA
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
HAL_SPI_RxHalfCpltCallback
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
SPI_InitTypeDef::IOSwap
uint32_t IOSwap
Definition: stm32h7xx_hal_spi.h:123
HAL_SPI_STATE_READY
@ HAL_SPI_STATE_READY
Definition: stm32h7xx_hal_spi.h:134
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_SPI_DMAPause
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
HAL_SPI_StateTypeDef
HAL_SPI_StateTypeDef
HAL SPI State structure definition.
Definition: stm32h7xx_hal_spi.h:131
HAL_SPI_Abort_IT
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
HAL_SPI_TxHalfCpltCallback
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
__SPI_HandleTypeDef::hdmarx
DMA_HandleTypeDef * hdmarx
Definition: stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_spi.h:129
HAL_SPI_TransmitReceive_IT
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
HAL_SPI_STATE_BUSY_TX
@ HAL_SPI_STATE_BUSY_TX
Definition: stm32h7xx_hal_spi.h:136
Mode
Definition: porcupine/demo/c/dr_libs/tests/external/miniaudio/extras/stb_vorbis.c:745
HAL_SPI_DeInit
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
__SPI_HandleTypeDef::CRCSize
uint32_t CRCSize
Definition: stm32f7xx_hal_spi.h:134
HAL_SPI_TransmitReceive
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
HAL_SPI_Receive
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
SPI_InitTypeDef::FifoThreshold
uint32_t FifoThreshold
Definition: stm32h7xx_hal_spi.h:99
HAL_SPI_MspInit
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
SPI_InitTypeDef::MasterKeepIOState
uint32_t MasterKeepIOState
Definition: stm32h7xx_hal_spi.h:120
HAL_SPI_Init
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)

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