stm32f411xe.h
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1 
34 #ifndef __STM32F411xE_H
35 #define __STM32F411xE_H
36 
37 #ifdef __cplusplus
38  extern "C" {
39 #endif /* __cplusplus */
40 
48 #define __CM4_REV 0x0001U
49 #define __MPU_PRESENT 1U
50 #define __NVIC_PRIO_BITS 4U
51 #define __Vendor_SysTickConfig 0U
52 #define __FPU_PRESENT 1U
66 typedef enum
67 {
68 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
69  NonMaskableInt_IRQn = -14,
70  MemoryManagement_IRQn = -12,
71  BusFault_IRQn = -11,
72  UsageFault_IRQn = -10,
73  SVCall_IRQn = -5,
74  DebugMonitor_IRQn = -4,
75  PendSV_IRQn = -2,
76  SysTick_IRQn = -1,
77 /****** STM32 specific Interrupt Numbers **********************************************************************/
78  WWDG_IRQn = 0,
79  PVD_IRQn = 1,
80  TAMP_STAMP_IRQn = 2,
81  RTC_WKUP_IRQn = 3,
82  FLASH_IRQn = 4,
83  RCC_IRQn = 5,
84  EXTI0_IRQn = 6,
85  EXTI1_IRQn = 7,
86  EXTI2_IRQn = 8,
87  EXTI3_IRQn = 9,
88  EXTI4_IRQn = 10,
89  DMA1_Stream0_IRQn = 11,
90  DMA1_Stream1_IRQn = 12,
91  DMA1_Stream2_IRQn = 13,
92  DMA1_Stream3_IRQn = 14,
93  DMA1_Stream4_IRQn = 15,
94  DMA1_Stream5_IRQn = 16,
95  DMA1_Stream6_IRQn = 17,
96  ADC_IRQn = 18,
97  EXTI9_5_IRQn = 23,
98  TIM1_BRK_TIM9_IRQn = 24,
99  TIM1_UP_TIM10_IRQn = 25,
100  TIM1_TRG_COM_TIM11_IRQn = 26,
101  TIM1_CC_IRQn = 27,
102  TIM2_IRQn = 28,
103  TIM3_IRQn = 29,
104  TIM4_IRQn = 30,
105  I2C1_EV_IRQn = 31,
106  I2C1_ER_IRQn = 32,
107  I2C2_EV_IRQn = 33,
108  I2C2_ER_IRQn = 34,
109  SPI1_IRQn = 35,
110  SPI2_IRQn = 36,
111  USART1_IRQn = 37,
112  USART2_IRQn = 38,
113  EXTI15_10_IRQn = 40,
114  RTC_Alarm_IRQn = 41,
115  OTG_FS_WKUP_IRQn = 42,
116  DMA1_Stream7_IRQn = 47,
117  SDIO_IRQn = 49,
118  TIM5_IRQn = 50,
119  SPI3_IRQn = 51,
120  DMA2_Stream0_IRQn = 56,
121  DMA2_Stream1_IRQn = 57,
122  DMA2_Stream2_IRQn = 58,
123  DMA2_Stream3_IRQn = 59,
124  DMA2_Stream4_IRQn = 60,
125  OTG_FS_IRQn = 67,
126  DMA2_Stream5_IRQn = 68,
127  DMA2_Stream6_IRQn = 69,
128  DMA2_Stream7_IRQn = 70,
129  USART6_IRQn = 71,
130  I2C3_EV_IRQn = 72,
131  I2C3_ER_IRQn = 73,
132  FPU_IRQn = 81,
133  SPI4_IRQn = 84,
134  SPI5_IRQn = 85
135 } IRQn_Type;
136 
141 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
142 #include "system_stm32f4xx.h"
143 #include <stdint.h>
144 
153 typedef struct
154 {
155  __IO uint32_t SR;
156  __IO uint32_t CR1;
157  __IO uint32_t CR2;
158  __IO uint32_t SMPR1;
159  __IO uint32_t SMPR2;
160  __IO uint32_t JOFR1;
161  __IO uint32_t JOFR2;
162  __IO uint32_t JOFR3;
163  __IO uint32_t JOFR4;
164  __IO uint32_t HTR;
165  __IO uint32_t LTR;
166  __IO uint32_t SQR1;
167  __IO uint32_t SQR2;
168  __IO uint32_t SQR3;
169  __IO uint32_t JSQR;
170  __IO uint32_t JDR1;
171  __IO uint32_t JDR2;
172  __IO uint32_t JDR3;
173  __IO uint32_t JDR4;
174  __IO uint32_t DR;
175 } ADC_TypeDef;
176 
177 typedef struct
178 {
179  __IO uint32_t CSR;
180  __IO uint32_t CCR;
181  __IO uint32_t CDR;
183 } ADC_Common_TypeDef;
184 
189 typedef struct
190 {
191  __IO uint32_t DR;
192  __IO uint8_t IDR;
193  uint8_t RESERVED0;
194  uint16_t RESERVED1;
195  __IO uint32_t CR;
196 } CRC_TypeDef;
197 
202 typedef struct
203 {
204  __IO uint32_t IDCODE;
205  __IO uint32_t CR;
206  __IO uint32_t APB1FZ;
207  __IO uint32_t APB2FZ;
208 }DBGMCU_TypeDef;
209 
210 
215 typedef struct
216 {
217  __IO uint32_t CR;
218  __IO uint32_t NDTR;
219  __IO uint32_t PAR;
220  __IO uint32_t M0AR;
221  __IO uint32_t M1AR;
222  __IO uint32_t FCR;
223 } DMA_Stream_TypeDef;
224 
225 typedef struct
226 {
227  __IO uint32_t LISR;
228  __IO uint32_t HISR;
229  __IO uint32_t LIFCR;
230  __IO uint32_t HIFCR;
231 } DMA_TypeDef;
232 
237 typedef struct
238 {
239  __IO uint32_t IMR;
240  __IO uint32_t EMR;
241  __IO uint32_t RTSR;
242  __IO uint32_t FTSR;
243  __IO uint32_t SWIER;
244  __IO uint32_t PR;
245 } EXTI_TypeDef;
246 
251 typedef struct
252 {
253  __IO uint32_t ACR;
254  __IO uint32_t KEYR;
255  __IO uint32_t OPTKEYR;
256  __IO uint32_t SR;
257  __IO uint32_t CR;
258  __IO uint32_t OPTCR;
259  __IO uint32_t OPTCR1;
260 } FLASH_TypeDef;
261 
266 typedef struct
267 {
268  __IO uint32_t MODER;
269  __IO uint32_t OTYPER;
270  __IO uint32_t OSPEEDR;
271  __IO uint32_t PUPDR;
272  __IO uint32_t IDR;
273  __IO uint32_t ODR;
274  __IO uint32_t BSRR;
275  __IO uint32_t LCKR;
276  __IO uint32_t AFR[2];
277 } GPIO_TypeDef;
278 
283 typedef struct
284 {
285  __IO uint32_t MEMRMP;
286  __IO uint32_t PMC;
287  __IO uint32_t EXTICR[4];
288  uint32_t RESERVED[2];
289  __IO uint32_t CMPCR;
290 } SYSCFG_TypeDef;
291 
296 typedef struct
297 {
298  __IO uint32_t CR1;
299  __IO uint32_t CR2;
300  __IO uint32_t OAR1;
301  __IO uint32_t OAR2;
302  __IO uint32_t DR;
303  __IO uint32_t SR1;
304  __IO uint32_t SR2;
305  __IO uint32_t CCR;
306  __IO uint32_t TRISE;
307  __IO uint32_t FLTR;
308 } I2C_TypeDef;
309 
314 typedef struct
315 {
316  __IO uint32_t KR;
317  __IO uint32_t PR;
318  __IO uint32_t RLR;
319  __IO uint32_t SR;
320 } IWDG_TypeDef;
321 
322 
327 typedef struct
328 {
329  __IO uint32_t CR;
330  __IO uint32_t CSR;
331 } PWR_TypeDef;
332 
337 typedef struct
338 {
339  __IO uint32_t CR;
340  __IO uint32_t PLLCFGR;
341  __IO uint32_t CFGR;
342  __IO uint32_t CIR;
343  __IO uint32_t AHB1RSTR;
344  __IO uint32_t AHB2RSTR;
345  __IO uint32_t AHB3RSTR;
346  uint32_t RESERVED0;
347  __IO uint32_t APB1RSTR;
348  __IO uint32_t APB2RSTR;
349  uint32_t RESERVED1[2];
350  __IO uint32_t AHB1ENR;
351  __IO uint32_t AHB2ENR;
352  __IO uint32_t AHB3ENR;
353  uint32_t RESERVED2;
354  __IO uint32_t APB1ENR;
355  __IO uint32_t APB2ENR;
356  uint32_t RESERVED3[2];
357  __IO uint32_t AHB1LPENR;
358  __IO uint32_t AHB2LPENR;
359  __IO uint32_t AHB3LPENR;
360  uint32_t RESERVED4;
361  __IO uint32_t APB1LPENR;
362  __IO uint32_t APB2LPENR;
363  uint32_t RESERVED5[2];
364  __IO uint32_t BDCR;
365  __IO uint32_t CSR;
366  uint32_t RESERVED6[2];
367  __IO uint32_t SSCGR;
368  __IO uint32_t PLLI2SCFGR;
369  uint32_t RESERVED7[1];
370  __IO uint32_t DCKCFGR;
371 } RCC_TypeDef;
372 
377 typedef struct
378 {
379  __IO uint32_t TR;
380  __IO uint32_t DR;
381  __IO uint32_t CR;
382  __IO uint32_t ISR;
383  __IO uint32_t PRER;
384  __IO uint32_t WUTR;
385  __IO uint32_t CALIBR;
386  __IO uint32_t ALRMAR;
387  __IO uint32_t ALRMBR;
388  __IO uint32_t WPR;
389  __IO uint32_t SSR;
390  __IO uint32_t SHIFTR;
391  __IO uint32_t TSTR;
392  __IO uint32_t TSDR;
393  __IO uint32_t TSSSR;
394  __IO uint32_t CALR;
395  __IO uint32_t TAFCR;
396  __IO uint32_t ALRMASSR;
397  __IO uint32_t ALRMBSSR;
398  uint32_t RESERVED7;
399  __IO uint32_t BKP0R;
400  __IO uint32_t BKP1R;
401  __IO uint32_t BKP2R;
402  __IO uint32_t BKP3R;
403  __IO uint32_t BKP4R;
404  __IO uint32_t BKP5R;
405  __IO uint32_t BKP6R;
406  __IO uint32_t BKP7R;
407  __IO uint32_t BKP8R;
408  __IO uint32_t BKP9R;
409  __IO uint32_t BKP10R;
410  __IO uint32_t BKP11R;
411  __IO uint32_t BKP12R;
412  __IO uint32_t BKP13R;
413  __IO uint32_t BKP14R;
414  __IO uint32_t BKP15R;
415  __IO uint32_t BKP16R;
416  __IO uint32_t BKP17R;
417  __IO uint32_t BKP18R;
418  __IO uint32_t BKP19R;
419 } RTC_TypeDef;
420 
425 typedef struct
426 {
427  __IO uint32_t POWER;
428  __IO uint32_t CLKCR;
429  __IO uint32_t ARG;
430  __IO uint32_t CMD;
431  __IO const uint32_t RESPCMD;
432  __IO const uint32_t RESP1;
433  __IO const uint32_t RESP2;
434  __IO const uint32_t RESP3;
435  __IO const uint32_t RESP4;
436  __IO uint32_t DTIMER;
437  __IO uint32_t DLEN;
438  __IO uint32_t DCTRL;
439  __IO const uint32_t DCOUNT;
440  __IO const uint32_t STA;
441  __IO uint32_t ICR;
442  __IO uint32_t MASK;
443  uint32_t RESERVED0[2];
444  __IO const uint32_t FIFOCNT;
445  uint32_t RESERVED1[13];
446  __IO uint32_t FIFO;
447 } SDIO_TypeDef;
448 
453 typedef struct
454 {
455  __IO uint32_t CR1;
456  __IO uint32_t CR2;
457  __IO uint32_t SR;
458  __IO uint32_t DR;
459  __IO uint32_t CRCPR;
460  __IO uint32_t RXCRCR;
461  __IO uint32_t TXCRCR;
462  __IO uint32_t I2SCFGR;
463  __IO uint32_t I2SPR;
464 } SPI_TypeDef;
465 
466 
471 typedef struct
472 {
473  __IO uint32_t CR1;
474  __IO uint32_t CR2;
475  __IO uint32_t SMCR;
476  __IO uint32_t DIER;
477  __IO uint32_t SR;
478  __IO uint32_t EGR;
479  __IO uint32_t CCMR1;
480  __IO uint32_t CCMR2;
481  __IO uint32_t CCER;
482  __IO uint32_t CNT;
483  __IO uint32_t PSC;
484  __IO uint32_t ARR;
485  __IO uint32_t RCR;
486  __IO uint32_t CCR1;
487  __IO uint32_t CCR2;
488  __IO uint32_t CCR3;
489  __IO uint32_t CCR4;
490  __IO uint32_t BDTR;
491  __IO uint32_t DCR;
492  __IO uint32_t DMAR;
493  __IO uint32_t OR;
494 } TIM_TypeDef;
495 
500 typedef struct
501 {
502  __IO uint32_t SR;
503  __IO uint32_t DR;
504  __IO uint32_t BRR;
505  __IO uint32_t CR1;
506  __IO uint32_t CR2;
507  __IO uint32_t CR3;
508  __IO uint32_t GTPR;
509 } USART_TypeDef;
510 
515 typedef struct
516 {
517  __IO uint32_t CR;
518  __IO uint32_t CFR;
519  __IO uint32_t SR;
520 } WWDG_TypeDef;
524 typedef struct
525 {
526  __IO uint32_t GOTGCTL;
527  __IO uint32_t GOTGINT;
528  __IO uint32_t GAHBCFG;
529  __IO uint32_t GUSBCFG;
530  __IO uint32_t GRSTCTL;
531  __IO uint32_t GINTSTS;
532  __IO uint32_t GINTMSK;
533  __IO uint32_t GRXSTSR;
534  __IO uint32_t GRXSTSP;
535  __IO uint32_t GRXFSIZ;
536  __IO uint32_t DIEPTXF0_HNPTXFSIZ;
537  __IO uint32_t HNPTXSTS;
538  uint32_t Reserved30[2];
539  __IO uint32_t GCCFG;
540  __IO uint32_t CID;
541  uint32_t Reserved40[48];
542  __IO uint32_t HPTXFSIZ;
543  __IO uint32_t DIEPTXF[0x0F];
544 } USB_OTG_GlobalTypeDef;
545 
549 typedef struct
550 {
551  __IO uint32_t DCFG;
552  __IO uint32_t DCTL;
553  __IO uint32_t DSTS;
554  uint32_t Reserved0C;
555  __IO uint32_t DIEPMSK;
556  __IO uint32_t DOEPMSK;
557  __IO uint32_t DAINT;
558  __IO uint32_t DAINTMSK;
559  uint32_t Reserved20;
560  uint32_t Reserved9;
561  __IO uint32_t DVBUSDIS;
562  __IO uint32_t DVBUSPULSE;
563  __IO uint32_t DTHRCTL;
564  __IO uint32_t DIEPEMPMSK;
565  __IO uint32_t DEACHINT;
566  __IO uint32_t DEACHMSK;
567  uint32_t Reserved40;
568  __IO uint32_t DINEP1MSK;
569  uint32_t Reserved44[15];
570  __IO uint32_t DOUTEP1MSK;
571 } USB_OTG_DeviceTypeDef;
572 
576 typedef struct
577 {
578  __IO uint32_t DIEPCTL;
579  uint32_t Reserved04;
580  __IO uint32_t DIEPINT;
581  uint32_t Reserved0C;
582  __IO uint32_t DIEPTSIZ;
583  __IO uint32_t DIEPDMA;
584  __IO uint32_t DTXFSTS;
585  uint32_t Reserved18;
586 } USB_OTG_INEndpointTypeDef;
587 
591 typedef struct
592 {
593  __IO uint32_t DOEPCTL;
594  uint32_t Reserved04;
595  __IO uint32_t DOEPINT;
596  uint32_t Reserved0C;
597  __IO uint32_t DOEPTSIZ;
598  __IO uint32_t DOEPDMA;
599  uint32_t Reserved18[2];
600 } USB_OTG_OUTEndpointTypeDef;
601 
605 typedef struct
606 {
607  __IO uint32_t HCFG;
608  __IO uint32_t HFIR;
609  __IO uint32_t HFNUM;
610  uint32_t Reserved40C;
611  __IO uint32_t HPTXSTS;
612  __IO uint32_t HAINT;
613  __IO uint32_t HAINTMSK;
614 } USB_OTG_HostTypeDef;
615 
619 typedef struct
620 {
621  __IO uint32_t HCCHAR;
622  __IO uint32_t HCSPLT;
623  __IO uint32_t HCINT;
624  __IO uint32_t HCINTMSK;
625  __IO uint32_t HCTSIZ;
626  __IO uint32_t HCDMA;
627  uint32_t Reserved[2];
628 } USB_OTG_HostChannelTypeDef;
629 
637 #define FLASH_BASE 0x08000000UL
638 #define SRAM1_BASE 0x20000000UL
639 #define PERIPH_BASE 0x40000000UL
640 #define SRAM1_BB_BASE 0x22000000UL
641 #define PERIPH_BB_BASE 0x42000000UL
642 #define BKPSRAM_BB_BASE 0x42480000UL
643 #define FLASH_END 0x0807FFFFUL
644 #define FLASH_OTP_BASE 0x1FFF7800UL
645 #define FLASH_OTP_END 0x1FFF7A0FUL
647 /* Legacy defines */
648 #define SRAM_BASE SRAM1_BASE
649 #define SRAM_BB_BASE SRAM1_BB_BASE
650 
652 #define APB1PERIPH_BASE PERIPH_BASE
653 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
654 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
655 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
656 
658 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
659 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
660 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
661 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
662 #define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
663 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
664 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
665 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400UL)
666 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
667 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
668 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000UL)
669 #define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
670 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
671 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
672 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
673 #define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
674 
676 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
677 #define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
678 #define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
679 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
680 #define ADC1_COMMON_BASE (APB2PERIPH_BASE + 0x2300UL)
681 /* Legacy define */
682 #define ADC_BASE ADC1_COMMON_BASE
683 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00UL)
684 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
685 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
686 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
687 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
688 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
689 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
690 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
691 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
692 
694 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
695 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
696 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
697 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
698 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
699 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
700 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
701 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
702 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
703 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
704 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
705 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
706 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
707 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
708 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
709 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
710 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
711 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
712 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
713 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
714 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
715 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
716 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
717 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
718 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
719 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
720 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
721 
722 
724 #define DBGMCU_BASE 0xE0042000UL
725 
726 #define USB_OTG_FS_PERIPH_BASE 0x50000000UL
727 
728 #define USB_OTG_GLOBAL_BASE 0x000UL
729 #define USB_OTG_DEVICE_BASE 0x800UL
730 #define USB_OTG_IN_ENDPOINT_BASE 0x900UL
731 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL
732 #define USB_OTG_EP_REG_SIZE 0x20UL
733 #define USB_OTG_HOST_BASE 0x400UL
734 #define USB_OTG_HOST_PORT_BASE 0x440UL
735 #define USB_OTG_HOST_CHANNEL_BASE 0x500UL
736 #define USB_OTG_HOST_CHANNEL_SIZE 0x20UL
737 #define USB_OTG_PCGCCTL_BASE 0xE00UL
738 #define USB_OTG_FIFO_BASE 0x1000UL
739 #define USB_OTG_FIFO_SIZE 0x1000UL
740 
741 #define UID_BASE 0x1FFF7A10UL
742 #define FLASHSIZE_BASE 0x1FFF7A22UL
743 #define PACKAGE_BASE 0x1FFF7BF0UL
751 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
752 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
753 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
754 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
755 #define RTC ((RTC_TypeDef *) RTC_BASE)
756 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
757 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
758 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
759 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
760 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
761 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
762 #define USART2 ((USART_TypeDef *) USART2_BASE)
763 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
764 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
765 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
766 #define PWR ((PWR_TypeDef *) PWR_BASE)
767 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
768 #define USART1 ((USART_TypeDef *) USART1_BASE)
769 #define USART6 ((USART_TypeDef *) USART6_BASE)
770 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
771 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
772 /* Legacy define */
773 #define ADC ADC1_COMMON
774 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
775 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
776 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
777 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
778 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
779 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
780 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
781 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
782 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
783 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
784 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
785 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
786 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
787 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
788 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
789 #define CRC ((CRC_TypeDef *) CRC_BASE)
790 #define RCC ((RCC_TypeDef *) RCC_BASE)
791 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
792 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
793 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
794 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
795 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
796 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
797 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
798 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
799 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
800 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
801 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
802 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
803 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
804 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
805 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
806 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
807 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
808 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
809 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
810 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
811 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
812 
825 /******************************************************************************/
826 /* Peripheral Registers_Bits_Definition */
827 /******************************************************************************/
828 
829 /******************************************************************************/
830 /* */
831 /* Analog to Digital Converter */
832 /* */
833 /******************************************************************************/
834 
835 /******************** Bit definition for ADC_SR register ********************/
836 #define ADC_SR_AWD_Pos (0U)
837 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
838 #define ADC_SR_AWD ADC_SR_AWD_Msk
839 #define ADC_SR_EOC_Pos (1U)
840 #define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
841 #define ADC_SR_EOC ADC_SR_EOC_Msk
842 #define ADC_SR_JEOC_Pos (2U)
843 #define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
844 #define ADC_SR_JEOC ADC_SR_JEOC_Msk
845 #define ADC_SR_JSTRT_Pos (3U)
846 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
847 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
848 #define ADC_SR_STRT_Pos (4U)
849 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
850 #define ADC_SR_STRT ADC_SR_STRT_Msk
851 #define ADC_SR_OVR_Pos (5U)
852 #define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
853 #define ADC_SR_OVR ADC_SR_OVR_Msk
855 /******************* Bit definition for ADC_CR1 register ********************/
856 #define ADC_CR1_AWDCH_Pos (0U)
857 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
858 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
859 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
860 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
861 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
862 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
863 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
864 #define ADC_CR1_EOCIE_Pos (5U)
865 #define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
866 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
867 #define ADC_CR1_AWDIE_Pos (6U)
868 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
869 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
870 #define ADC_CR1_JEOCIE_Pos (7U)
871 #define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
872 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
873 #define ADC_CR1_SCAN_Pos (8U)
874 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
875 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
876 #define ADC_CR1_AWDSGL_Pos (9U)
877 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
878 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
879 #define ADC_CR1_JAUTO_Pos (10U)
880 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
881 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
882 #define ADC_CR1_DISCEN_Pos (11U)
883 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
884 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
885 #define ADC_CR1_JDISCEN_Pos (12U)
886 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
887 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
888 #define ADC_CR1_DISCNUM_Pos (13U)
889 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
890 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
891 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
892 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
893 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
894 #define ADC_CR1_JAWDEN_Pos (22U)
895 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
896 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
897 #define ADC_CR1_AWDEN_Pos (23U)
898 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
899 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
900 #define ADC_CR1_RES_Pos (24U)
901 #define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
902 #define ADC_CR1_RES ADC_CR1_RES_Msk
903 #define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
904 #define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
905 #define ADC_CR1_OVRIE_Pos (26U)
906 #define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
907 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
909 /******************* Bit definition for ADC_CR2 register ********************/
910 #define ADC_CR2_ADON_Pos (0U)
911 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
912 #define ADC_CR2_ADON ADC_CR2_ADON_Msk
913 #define ADC_CR2_CONT_Pos (1U)
914 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
915 #define ADC_CR2_CONT ADC_CR2_CONT_Msk
916 #define ADC_CR2_DMA_Pos (8U)
917 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
918 #define ADC_CR2_DMA ADC_CR2_DMA_Msk
919 #define ADC_CR2_DDS_Pos (9U)
920 #define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
921 #define ADC_CR2_DDS ADC_CR2_DDS_Msk
922 #define ADC_CR2_EOCS_Pos (10U)
923 #define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
924 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
925 #define ADC_CR2_ALIGN_Pos (11U)
926 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
927 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
928 #define ADC_CR2_JEXTSEL_Pos (16U)
929 #define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
930 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
931 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
932 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
933 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
934 #define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
935 #define ADC_CR2_JEXTEN_Pos (20U)
936 #define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
937 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
938 #define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
939 #define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
940 #define ADC_CR2_JSWSTART_Pos (22U)
941 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
942 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
943 #define ADC_CR2_EXTSEL_Pos (24U)
944 #define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
945 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
946 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
947 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
948 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
949 #define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
950 #define ADC_CR2_EXTEN_Pos (28U)
951 #define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
952 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
953 #define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
954 #define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
955 #define ADC_CR2_SWSTART_Pos (30U)
956 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
957 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
959 /****************** Bit definition for ADC_SMPR1 register *******************/
960 #define ADC_SMPR1_SMP10_Pos (0U)
961 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
962 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
963 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
964 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
965 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
966 #define ADC_SMPR1_SMP11_Pos (3U)
967 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
968 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
969 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
970 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
971 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
972 #define ADC_SMPR1_SMP12_Pos (6U)
973 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
974 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
975 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
976 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
977 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
978 #define ADC_SMPR1_SMP13_Pos (9U)
979 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
980 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
981 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
982 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
983 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
984 #define ADC_SMPR1_SMP14_Pos (12U)
985 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
986 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
987 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
988 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
989 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
990 #define ADC_SMPR1_SMP15_Pos (15U)
991 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
992 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
993 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
994 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
995 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
996 #define ADC_SMPR1_SMP16_Pos (18U)
997 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
998 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
999 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1000 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1001 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1002 #define ADC_SMPR1_SMP17_Pos (21U)
1003 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1004 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1005 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1006 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1007 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1008 #define ADC_SMPR1_SMP18_Pos (24U)
1009 #define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1010 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1011 #define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1012 #define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1013 #define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1015 /****************** Bit definition for ADC_SMPR2 register *******************/
1016 #define ADC_SMPR2_SMP0_Pos (0U)
1017 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1018 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1019 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1020 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1021 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1022 #define ADC_SMPR2_SMP1_Pos (3U)
1023 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1024 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1025 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1026 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1027 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1028 #define ADC_SMPR2_SMP2_Pos (6U)
1029 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1030 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1031 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1032 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1033 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1034 #define ADC_SMPR2_SMP3_Pos (9U)
1035 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1036 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1037 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1038 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1039 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1040 #define ADC_SMPR2_SMP4_Pos (12U)
1041 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1042 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1043 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1044 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1045 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1046 #define ADC_SMPR2_SMP5_Pos (15U)
1047 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1048 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1049 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1050 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1051 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1052 #define ADC_SMPR2_SMP6_Pos (18U)
1053 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1054 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1055 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1056 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1057 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1058 #define ADC_SMPR2_SMP7_Pos (21U)
1059 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1060 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1061 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1062 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1063 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1064 #define ADC_SMPR2_SMP8_Pos (24U)
1065 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1066 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1067 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1068 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1069 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1070 #define ADC_SMPR2_SMP9_Pos (27U)
1071 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1072 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1073 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1074 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1075 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1077 /****************** Bit definition for ADC_JOFR1 register *******************/
1078 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1079 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1080 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1082 /****************** Bit definition for ADC_JOFR2 register *******************/
1083 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1084 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1085 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1087 /****************** Bit definition for ADC_JOFR3 register *******************/
1088 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1089 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1090 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1092 /****************** Bit definition for ADC_JOFR4 register *******************/
1093 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1094 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1095 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1097 /******************* Bit definition for ADC_HTR register ********************/
1098 #define ADC_HTR_HT_Pos (0U)
1099 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1100 #define ADC_HTR_HT ADC_HTR_HT_Msk
1102 /******************* Bit definition for ADC_LTR register ********************/
1103 #define ADC_LTR_LT_Pos (0U)
1104 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1105 #define ADC_LTR_LT ADC_LTR_LT_Msk
1107 /******************* Bit definition for ADC_SQR1 register *******************/
1108 #define ADC_SQR1_SQ13_Pos (0U)
1109 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1110 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1111 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1112 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1113 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1114 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1115 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1116 #define ADC_SQR1_SQ14_Pos (5U)
1117 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1118 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1119 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1120 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1121 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1122 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1123 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1124 #define ADC_SQR1_SQ15_Pos (10U)
1125 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1126 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1127 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1128 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1129 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1130 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1131 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1132 #define ADC_SQR1_SQ16_Pos (15U)
1133 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1134 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1135 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1136 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1137 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1138 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1139 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1140 #define ADC_SQR1_L_Pos (20U)
1141 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1142 #define ADC_SQR1_L ADC_SQR1_L_Msk
1143 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1144 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1145 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1146 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1148 /******************* Bit definition for ADC_SQR2 register *******************/
1149 #define ADC_SQR2_SQ7_Pos (0U)
1150 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1151 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1152 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1153 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1154 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1155 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1156 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1157 #define ADC_SQR2_SQ8_Pos (5U)
1158 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1159 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1160 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1161 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1162 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1163 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1164 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1165 #define ADC_SQR2_SQ9_Pos (10U)
1166 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1167 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1168 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1169 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1170 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1171 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1172 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1173 #define ADC_SQR2_SQ10_Pos (15U)
1174 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1175 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1176 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1177 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1178 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1179 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1180 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1181 #define ADC_SQR2_SQ11_Pos (20U)
1182 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1183 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1184 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1185 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1186 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1187 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1188 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1189 #define ADC_SQR2_SQ12_Pos (25U)
1190 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1191 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1192 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1193 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1194 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1195 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1196 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1198 /******************* Bit definition for ADC_SQR3 register *******************/
1199 #define ADC_SQR3_SQ1_Pos (0U)
1200 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1201 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1202 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1203 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1204 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1205 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1206 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1207 #define ADC_SQR3_SQ2_Pos (5U)
1208 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1209 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1210 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1211 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1212 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1213 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1214 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1215 #define ADC_SQR3_SQ3_Pos (10U)
1216 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1217 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1218 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1219 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1220 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1221 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1222 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1223 #define ADC_SQR3_SQ4_Pos (15U)
1224 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1225 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1226 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1227 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1228 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1229 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1230 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1231 #define ADC_SQR3_SQ5_Pos (20U)
1232 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1233 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1234 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1235 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1236 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1237 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1238 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1239 #define ADC_SQR3_SQ6_Pos (25U)
1240 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1241 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1242 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1243 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1244 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1245 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1246 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1248 /******************* Bit definition for ADC_JSQR register *******************/
1249 #define ADC_JSQR_JSQ1_Pos (0U)
1250 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1251 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1252 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1253 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1254 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1255 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1256 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1257 #define ADC_JSQR_JSQ2_Pos (5U)
1258 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1259 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1260 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1261 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1262 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1263 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1264 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1265 #define ADC_JSQR_JSQ3_Pos (10U)
1266 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1267 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1268 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1269 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1270 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1271 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1272 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1273 #define ADC_JSQR_JSQ4_Pos (15U)
1274 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1275 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1276 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1277 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1278 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1279 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1280 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1281 #define ADC_JSQR_JL_Pos (20U)
1282 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1283 #define ADC_JSQR_JL ADC_JSQR_JL_Msk
1284 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1285 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1287 /******************* Bit definition for ADC_JDR1 register *******************/
1288 #define ADC_JDR1_JDATA_Pos (0U)
1289 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
1290 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
1292 /******************* Bit definition for ADC_JDR2 register *******************/
1293 #define ADC_JDR2_JDATA_Pos (0U)
1294 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
1295 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
1297 /******************* Bit definition for ADC_JDR3 register *******************/
1298 #define ADC_JDR3_JDATA_Pos (0U)
1299 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
1300 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
1302 /******************* Bit definition for ADC_JDR4 register *******************/
1303 #define ADC_JDR4_JDATA_Pos (0U)
1304 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
1305 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
1307 /******************** Bit definition for ADC_DR register ********************/
1308 #define ADC_DR_DATA_Pos (0U)
1309 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1310 #define ADC_DR_DATA ADC_DR_DATA_Msk
1311 #define ADC_DR_ADC2DATA_Pos (16U)
1312 #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1313 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1315 /******************* Bit definition for ADC_CSR register ********************/
1316 #define ADC_CSR_AWD1_Pos (0U)
1317 #define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1318 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1319 #define ADC_CSR_EOC1_Pos (1U)
1320 #define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1321 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1322 #define ADC_CSR_JEOC1_Pos (2U)
1323 #define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1324 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1325 #define ADC_CSR_JSTRT1_Pos (3U)
1326 #define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1327 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1328 #define ADC_CSR_STRT1_Pos (4U)
1329 #define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1330 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1331 #define ADC_CSR_OVR1_Pos (5U)
1332 #define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1333 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1335 /* Legacy defines */
1336 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1337 
1338 /******************* Bit definition for ADC_CCR register ********************/
1339 #define ADC_CCR_MULTI_Pos (0U)
1340 #define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1341 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1342 #define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1343 #define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1344 #define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1345 #define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1346 #define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1347 #define ADC_CCR_DELAY_Pos (8U)
1348 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1349 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1350 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1351 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1352 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1353 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1354 #define ADC_CCR_DDS_Pos (13U)
1355 #define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1356 #define ADC_CCR_DDS ADC_CCR_DDS_Msk
1357 #define ADC_CCR_DMA_Pos (14U)
1358 #define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1359 #define ADC_CCR_DMA ADC_CCR_DMA_Msk
1360 #define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1361 #define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1362 #define ADC_CCR_ADCPRE_Pos (16U)
1363 #define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1364 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1365 #define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1366 #define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1367 #define ADC_CCR_VBATE_Pos (22U)
1368 #define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1369 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1370 #define ADC_CCR_TSVREFE_Pos (23U)
1371 #define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1372 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1374 /******************* Bit definition for ADC_CDR register ********************/
1375 #define ADC_CDR_DATA1_Pos (0U)
1376 #define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1377 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1378 #define ADC_CDR_DATA2_Pos (16U)
1379 #define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1380 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1382 /* Legacy defines */
1383 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1384 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1385 
1386 /******************************************************************************/
1387 /* */
1388 /* CRC calculation unit */
1389 /* */
1390 /******************************************************************************/
1391 /******************* Bit definition for CRC_DR register *********************/
1392 #define CRC_DR_DR_Pos (0U)
1393 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
1394 #define CRC_DR_DR CRC_DR_DR_Msk
1397 /******************* Bit definition for CRC_IDR register ********************/
1398 #define CRC_IDR_IDR_Pos (0U)
1399 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
1400 #define CRC_IDR_IDR CRC_IDR_IDR_Msk
1403 /******************** Bit definition for CRC_CR register ********************/
1404 #define CRC_CR_RESET_Pos (0U)
1405 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
1406 #define CRC_CR_RESET CRC_CR_RESET_Msk
1409 /******************************************************************************/
1410 /* */
1411 /* DMA Controller */
1412 /* */
1413 /******************************************************************************/
1414 /******************** Bits definition for DMA_SxCR register *****************/
1415 #define DMA_SxCR_CHSEL_Pos (25U)
1416 #define DMA_SxCR_CHSEL_Msk (0x7UL << DMA_SxCR_CHSEL_Pos)
1417 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
1418 #define DMA_SxCR_CHSEL_0 0x02000000U
1419 #define DMA_SxCR_CHSEL_1 0x04000000U
1420 #define DMA_SxCR_CHSEL_2 0x08000000U
1421 #define DMA_SxCR_MBURST_Pos (23U)
1422 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
1423 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
1424 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
1425 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
1426 #define DMA_SxCR_PBURST_Pos (21U)
1427 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
1428 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
1429 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
1430 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
1431 #define DMA_SxCR_CT_Pos (19U)
1432 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
1433 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
1434 #define DMA_SxCR_DBM_Pos (18U)
1435 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
1436 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
1437 #define DMA_SxCR_PL_Pos (16U)
1438 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
1439 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
1440 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
1441 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
1442 #define DMA_SxCR_PINCOS_Pos (15U)
1443 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
1444 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
1445 #define DMA_SxCR_MSIZE_Pos (13U)
1446 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
1447 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
1448 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
1449 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
1450 #define DMA_SxCR_PSIZE_Pos (11U)
1451 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
1452 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
1453 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
1454 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
1455 #define DMA_SxCR_MINC_Pos (10U)
1456 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
1457 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
1458 #define DMA_SxCR_PINC_Pos (9U)
1459 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
1460 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
1461 #define DMA_SxCR_CIRC_Pos (8U)
1462 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
1463 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
1464 #define DMA_SxCR_DIR_Pos (6U)
1465 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
1466 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
1467 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
1468 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
1469 #define DMA_SxCR_PFCTRL_Pos (5U)
1470 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
1471 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
1472 #define DMA_SxCR_TCIE_Pos (4U)
1473 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
1474 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
1475 #define DMA_SxCR_HTIE_Pos (3U)
1476 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
1477 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
1478 #define DMA_SxCR_TEIE_Pos (2U)
1479 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
1480 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
1481 #define DMA_SxCR_DMEIE_Pos (1U)
1482 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
1483 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
1484 #define DMA_SxCR_EN_Pos (0U)
1485 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
1486 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
1487 
1488 /* Legacy defines */
1489 #define DMA_SxCR_ACK_Pos (20U)
1490 #define DMA_SxCR_ACK_Msk (0x1UL << DMA_SxCR_ACK_Pos)
1491 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
1492 
1493 /******************** Bits definition for DMA_SxCNDTR register **************/
1494 #define DMA_SxNDT_Pos (0U)
1495 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
1496 #define DMA_SxNDT DMA_SxNDT_Msk
1497 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
1498 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
1499 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
1500 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
1501 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
1502 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
1503 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
1504 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
1505 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
1506 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
1507 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
1508 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
1509 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
1510 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
1511 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
1512 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
1514 /******************** Bits definition for DMA_SxFCR register ****************/
1515 #define DMA_SxFCR_FEIE_Pos (7U)
1516 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
1517 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
1518 #define DMA_SxFCR_FS_Pos (3U)
1519 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
1520 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
1521 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
1522 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
1523 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
1524 #define DMA_SxFCR_DMDIS_Pos (2U)
1525 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
1526 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
1527 #define DMA_SxFCR_FTH_Pos (0U)
1528 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
1529 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
1530 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
1531 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
1533 /******************** Bits definition for DMA_LISR register *****************/
1534 #define DMA_LISR_TCIF3_Pos (27U)
1535 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
1536 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
1537 #define DMA_LISR_HTIF3_Pos (26U)
1538 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
1539 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
1540 #define DMA_LISR_TEIF3_Pos (25U)
1541 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
1542 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
1543 #define DMA_LISR_DMEIF3_Pos (24U)
1544 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
1545 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
1546 #define DMA_LISR_FEIF3_Pos (22U)
1547 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
1548 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
1549 #define DMA_LISR_TCIF2_Pos (21U)
1550 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
1551 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
1552 #define DMA_LISR_HTIF2_Pos (20U)
1553 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
1554 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
1555 #define DMA_LISR_TEIF2_Pos (19U)
1556 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
1557 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
1558 #define DMA_LISR_DMEIF2_Pos (18U)
1559 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
1560 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
1561 #define DMA_LISR_FEIF2_Pos (16U)
1562 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
1563 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
1564 #define DMA_LISR_TCIF1_Pos (11U)
1565 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
1566 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
1567 #define DMA_LISR_HTIF1_Pos (10U)
1568 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
1569 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
1570 #define DMA_LISR_TEIF1_Pos (9U)
1571 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
1572 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
1573 #define DMA_LISR_DMEIF1_Pos (8U)
1574 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
1575 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
1576 #define DMA_LISR_FEIF1_Pos (6U)
1577 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
1578 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
1579 #define DMA_LISR_TCIF0_Pos (5U)
1580 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
1581 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
1582 #define DMA_LISR_HTIF0_Pos (4U)
1583 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
1584 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
1585 #define DMA_LISR_TEIF0_Pos (3U)
1586 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
1587 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
1588 #define DMA_LISR_DMEIF0_Pos (2U)
1589 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
1590 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
1591 #define DMA_LISR_FEIF0_Pos (0U)
1592 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
1593 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
1594 
1595 /******************** Bits definition for DMA_HISR register *****************/
1596 #define DMA_HISR_TCIF7_Pos (27U)
1597 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
1598 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
1599 #define DMA_HISR_HTIF7_Pos (26U)
1600 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
1601 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
1602 #define DMA_HISR_TEIF7_Pos (25U)
1603 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
1604 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
1605 #define DMA_HISR_DMEIF7_Pos (24U)
1606 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
1607 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
1608 #define DMA_HISR_FEIF7_Pos (22U)
1609 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
1610 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
1611 #define DMA_HISR_TCIF6_Pos (21U)
1612 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
1613 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
1614 #define DMA_HISR_HTIF6_Pos (20U)
1615 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
1616 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
1617 #define DMA_HISR_TEIF6_Pos (19U)
1618 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
1619 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
1620 #define DMA_HISR_DMEIF6_Pos (18U)
1621 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
1622 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
1623 #define DMA_HISR_FEIF6_Pos (16U)
1624 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
1625 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
1626 #define DMA_HISR_TCIF5_Pos (11U)
1627 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
1628 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
1629 #define DMA_HISR_HTIF5_Pos (10U)
1630 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
1631 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
1632 #define DMA_HISR_TEIF5_Pos (9U)
1633 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
1634 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
1635 #define DMA_HISR_DMEIF5_Pos (8U)
1636 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
1637 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
1638 #define DMA_HISR_FEIF5_Pos (6U)
1639 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
1640 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
1641 #define DMA_HISR_TCIF4_Pos (5U)
1642 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
1643 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
1644 #define DMA_HISR_HTIF4_Pos (4U)
1645 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
1646 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
1647 #define DMA_HISR_TEIF4_Pos (3U)
1648 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
1649 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
1650 #define DMA_HISR_DMEIF4_Pos (2U)
1651 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
1652 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
1653 #define DMA_HISR_FEIF4_Pos (0U)
1654 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
1655 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
1656 
1657 /******************** Bits definition for DMA_LIFCR register ****************/
1658 #define DMA_LIFCR_CTCIF3_Pos (27U)
1659 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
1660 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
1661 #define DMA_LIFCR_CHTIF3_Pos (26U)
1662 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
1663 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
1664 #define DMA_LIFCR_CTEIF3_Pos (25U)
1665 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
1666 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
1667 #define DMA_LIFCR_CDMEIF3_Pos (24U)
1668 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
1669 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
1670 #define DMA_LIFCR_CFEIF3_Pos (22U)
1671 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
1672 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
1673 #define DMA_LIFCR_CTCIF2_Pos (21U)
1674 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
1675 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
1676 #define DMA_LIFCR_CHTIF2_Pos (20U)
1677 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
1678 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
1679 #define DMA_LIFCR_CTEIF2_Pos (19U)
1680 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
1681 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
1682 #define DMA_LIFCR_CDMEIF2_Pos (18U)
1683 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
1684 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
1685 #define DMA_LIFCR_CFEIF2_Pos (16U)
1686 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
1687 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
1688 #define DMA_LIFCR_CTCIF1_Pos (11U)
1689 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
1690 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
1691 #define DMA_LIFCR_CHTIF1_Pos (10U)
1692 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
1693 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
1694 #define DMA_LIFCR_CTEIF1_Pos (9U)
1695 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
1696 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
1697 #define DMA_LIFCR_CDMEIF1_Pos (8U)
1698 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
1699 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
1700 #define DMA_LIFCR_CFEIF1_Pos (6U)
1701 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
1702 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
1703 #define DMA_LIFCR_CTCIF0_Pos (5U)
1704 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
1705 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
1706 #define DMA_LIFCR_CHTIF0_Pos (4U)
1707 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
1708 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
1709 #define DMA_LIFCR_CTEIF0_Pos (3U)
1710 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
1711 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
1712 #define DMA_LIFCR_CDMEIF0_Pos (2U)
1713 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
1714 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
1715 #define DMA_LIFCR_CFEIF0_Pos (0U)
1716 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
1717 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
1718 
1719 /******************** Bits definition for DMA_HIFCR register ****************/
1720 #define DMA_HIFCR_CTCIF7_Pos (27U)
1721 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
1722 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
1723 #define DMA_HIFCR_CHTIF7_Pos (26U)
1724 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
1725 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
1726 #define DMA_HIFCR_CTEIF7_Pos (25U)
1727 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
1728 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
1729 #define DMA_HIFCR_CDMEIF7_Pos (24U)
1730 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
1731 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
1732 #define DMA_HIFCR_CFEIF7_Pos (22U)
1733 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
1734 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
1735 #define DMA_HIFCR_CTCIF6_Pos (21U)
1736 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
1737 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
1738 #define DMA_HIFCR_CHTIF6_Pos (20U)
1739 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
1740 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
1741 #define DMA_HIFCR_CTEIF6_Pos (19U)
1742 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
1743 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
1744 #define DMA_HIFCR_CDMEIF6_Pos (18U)
1745 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
1746 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
1747 #define DMA_HIFCR_CFEIF6_Pos (16U)
1748 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
1749 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
1750 #define DMA_HIFCR_CTCIF5_Pos (11U)
1751 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
1752 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
1753 #define DMA_HIFCR_CHTIF5_Pos (10U)
1754 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
1755 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
1756 #define DMA_HIFCR_CTEIF5_Pos (9U)
1757 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
1758 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
1759 #define DMA_HIFCR_CDMEIF5_Pos (8U)
1760 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
1761 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
1762 #define DMA_HIFCR_CFEIF5_Pos (6U)
1763 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
1764 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
1765 #define DMA_HIFCR_CTCIF4_Pos (5U)
1766 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
1767 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
1768 #define DMA_HIFCR_CHTIF4_Pos (4U)
1769 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
1770 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
1771 #define DMA_HIFCR_CTEIF4_Pos (3U)
1772 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
1773 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
1774 #define DMA_HIFCR_CDMEIF4_Pos (2U)
1775 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
1776 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
1777 #define DMA_HIFCR_CFEIF4_Pos (0U)
1778 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
1779 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
1780 
1781 /****************** Bit definition for DMA_SxPAR register ********************/
1782 #define DMA_SxPAR_PA_Pos (0U)
1783 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
1784 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
1786 /****************** Bit definition for DMA_SxM0AR register ********************/
1787 #define DMA_SxM0AR_M0A_Pos (0U)
1788 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
1789 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
1791 /****************** Bit definition for DMA_SxM1AR register ********************/
1792 #define DMA_SxM1AR_M1A_Pos (0U)
1793 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
1794 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
1797 /******************************************************************************/
1798 /* */
1799 /* External Interrupt/Event Controller */
1800 /* */
1801 /******************************************************************************/
1802 /******************* Bit definition for EXTI_IMR register *******************/
1803 #define EXTI_IMR_MR0_Pos (0U)
1804 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
1805 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
1806 #define EXTI_IMR_MR1_Pos (1U)
1807 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
1808 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
1809 #define EXTI_IMR_MR2_Pos (2U)
1810 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
1811 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
1812 #define EXTI_IMR_MR3_Pos (3U)
1813 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
1814 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
1815 #define EXTI_IMR_MR4_Pos (4U)
1816 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
1817 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
1818 #define EXTI_IMR_MR5_Pos (5U)
1819 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
1820 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
1821 #define EXTI_IMR_MR6_Pos (6U)
1822 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
1823 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
1824 #define EXTI_IMR_MR7_Pos (7U)
1825 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
1826 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
1827 #define EXTI_IMR_MR8_Pos (8U)
1828 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
1829 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
1830 #define EXTI_IMR_MR9_Pos (9U)
1831 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
1832 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
1833 #define EXTI_IMR_MR10_Pos (10U)
1834 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
1835 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
1836 #define EXTI_IMR_MR11_Pos (11U)
1837 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
1838 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
1839 #define EXTI_IMR_MR12_Pos (12U)
1840 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
1841 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
1842 #define EXTI_IMR_MR13_Pos (13U)
1843 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
1844 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
1845 #define EXTI_IMR_MR14_Pos (14U)
1846 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
1847 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
1848 #define EXTI_IMR_MR15_Pos (15U)
1849 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
1850 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
1851 #define EXTI_IMR_MR16_Pos (16U)
1852 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
1853 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
1854 #define EXTI_IMR_MR17_Pos (17U)
1855 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
1856 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
1857 #define EXTI_IMR_MR18_Pos (18U)
1858 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
1859 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
1860 #define EXTI_IMR_MR19_Pos (19U)
1861 #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
1862 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
1863 #define EXTI_IMR_MR20_Pos (20U)
1864 #define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
1865 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
1866 #define EXTI_IMR_MR21_Pos (21U)
1867 #define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
1868 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
1869 #define EXTI_IMR_MR22_Pos (22U)
1870 #define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
1871 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
1873 /* Reference Defines */
1874 #define EXTI_IMR_IM0 EXTI_IMR_MR0
1875 #define EXTI_IMR_IM1 EXTI_IMR_MR1
1876 #define EXTI_IMR_IM2 EXTI_IMR_MR2
1877 #define EXTI_IMR_IM3 EXTI_IMR_MR3
1878 #define EXTI_IMR_IM4 EXTI_IMR_MR4
1879 #define EXTI_IMR_IM5 EXTI_IMR_MR5
1880 #define EXTI_IMR_IM6 EXTI_IMR_MR6
1881 #define EXTI_IMR_IM7 EXTI_IMR_MR7
1882 #define EXTI_IMR_IM8 EXTI_IMR_MR8
1883 #define EXTI_IMR_IM9 EXTI_IMR_MR9
1884 #define EXTI_IMR_IM10 EXTI_IMR_MR10
1885 #define EXTI_IMR_IM11 EXTI_IMR_MR11
1886 #define EXTI_IMR_IM12 EXTI_IMR_MR12
1887 #define EXTI_IMR_IM13 EXTI_IMR_MR13
1888 #define EXTI_IMR_IM14 EXTI_IMR_MR14
1889 #define EXTI_IMR_IM15 EXTI_IMR_MR15
1890 #define EXTI_IMR_IM16 EXTI_IMR_MR16
1891 #define EXTI_IMR_IM17 EXTI_IMR_MR17
1892 #define EXTI_IMR_IM18 EXTI_IMR_MR18
1893 #define EXTI_IMR_IM19 EXTI_IMR_MR19
1894 #define EXTI_IMR_IM20 EXTI_IMR_MR20
1895 #define EXTI_IMR_IM21 EXTI_IMR_MR21
1896 #define EXTI_IMR_IM22 EXTI_IMR_MR22
1897 #define EXTI_IMR_IM_Pos (0U)
1898 #define EXTI_IMR_IM_Msk (0x7FFFFFUL << EXTI_IMR_IM_Pos)
1899 #define EXTI_IMR_IM EXTI_IMR_IM_Msk
1901 /******************* Bit definition for EXTI_EMR register *******************/
1902 #define EXTI_EMR_MR0_Pos (0U)
1903 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
1904 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
1905 #define EXTI_EMR_MR1_Pos (1U)
1906 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
1907 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
1908 #define EXTI_EMR_MR2_Pos (2U)
1909 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
1910 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
1911 #define EXTI_EMR_MR3_Pos (3U)
1912 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
1913 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
1914 #define EXTI_EMR_MR4_Pos (4U)
1915 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
1916 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
1917 #define EXTI_EMR_MR5_Pos (5U)
1918 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
1919 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
1920 #define EXTI_EMR_MR6_Pos (6U)
1921 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
1922 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
1923 #define EXTI_EMR_MR7_Pos (7U)
1924 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
1925 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
1926 #define EXTI_EMR_MR8_Pos (8U)
1927 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
1928 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
1929 #define EXTI_EMR_MR9_Pos (9U)
1930 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
1931 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
1932 #define EXTI_EMR_MR10_Pos (10U)
1933 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
1934 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
1935 #define EXTI_EMR_MR11_Pos (11U)
1936 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
1937 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
1938 #define EXTI_EMR_MR12_Pos (12U)
1939 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
1940 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
1941 #define EXTI_EMR_MR13_Pos (13U)
1942 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
1943 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
1944 #define EXTI_EMR_MR14_Pos (14U)
1945 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
1946 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
1947 #define EXTI_EMR_MR15_Pos (15U)
1948 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
1949 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
1950 #define EXTI_EMR_MR16_Pos (16U)
1951 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
1952 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
1953 #define EXTI_EMR_MR17_Pos (17U)
1954 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
1955 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
1956 #define EXTI_EMR_MR18_Pos (18U)
1957 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
1958 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
1959 #define EXTI_EMR_MR19_Pos (19U)
1960 #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
1961 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
1962 #define EXTI_EMR_MR20_Pos (20U)
1963 #define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
1964 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
1965 #define EXTI_EMR_MR21_Pos (21U)
1966 #define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
1967 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
1968 #define EXTI_EMR_MR22_Pos (22U)
1969 #define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
1970 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
1972 /* Reference Defines */
1973 #define EXTI_EMR_EM0 EXTI_EMR_MR0
1974 #define EXTI_EMR_EM1 EXTI_EMR_MR1
1975 #define EXTI_EMR_EM2 EXTI_EMR_MR2
1976 #define EXTI_EMR_EM3 EXTI_EMR_MR3
1977 #define EXTI_EMR_EM4 EXTI_EMR_MR4
1978 #define EXTI_EMR_EM5 EXTI_EMR_MR5
1979 #define EXTI_EMR_EM6 EXTI_EMR_MR6
1980 #define EXTI_EMR_EM7 EXTI_EMR_MR7
1981 #define EXTI_EMR_EM8 EXTI_EMR_MR8
1982 #define EXTI_EMR_EM9 EXTI_EMR_MR9
1983 #define EXTI_EMR_EM10 EXTI_EMR_MR10
1984 #define EXTI_EMR_EM11 EXTI_EMR_MR11
1985 #define EXTI_EMR_EM12 EXTI_EMR_MR12
1986 #define EXTI_EMR_EM13 EXTI_EMR_MR13
1987 #define EXTI_EMR_EM14 EXTI_EMR_MR14
1988 #define EXTI_EMR_EM15 EXTI_EMR_MR15
1989 #define EXTI_EMR_EM16 EXTI_EMR_MR16
1990 #define EXTI_EMR_EM17 EXTI_EMR_MR17
1991 #define EXTI_EMR_EM18 EXTI_EMR_MR18
1992 #define EXTI_EMR_EM19 EXTI_EMR_MR19
1993 #define EXTI_EMR_EM20 EXTI_EMR_MR20
1994 #define EXTI_EMR_EM21 EXTI_EMR_MR21
1995 #define EXTI_EMR_EM22 EXTI_EMR_MR22
1996 
1997 /****************** Bit definition for EXTI_RTSR register *******************/
1998 #define EXTI_RTSR_TR0_Pos (0U)
1999 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
2000 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
2001 #define EXTI_RTSR_TR1_Pos (1U)
2002 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
2003 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
2004 #define EXTI_RTSR_TR2_Pos (2U)
2005 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
2006 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
2007 #define EXTI_RTSR_TR3_Pos (3U)
2008 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
2009 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
2010 #define EXTI_RTSR_TR4_Pos (4U)
2011 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
2012 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
2013 #define EXTI_RTSR_TR5_Pos (5U)
2014 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
2015 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
2016 #define EXTI_RTSR_TR6_Pos (6U)
2017 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
2018 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
2019 #define EXTI_RTSR_TR7_Pos (7U)
2020 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
2021 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
2022 #define EXTI_RTSR_TR8_Pos (8U)
2023 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
2024 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
2025 #define EXTI_RTSR_TR9_Pos (9U)
2026 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
2027 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
2028 #define EXTI_RTSR_TR10_Pos (10U)
2029 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
2030 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
2031 #define EXTI_RTSR_TR11_Pos (11U)
2032 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
2033 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
2034 #define EXTI_RTSR_TR12_Pos (12U)
2035 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
2036 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
2037 #define EXTI_RTSR_TR13_Pos (13U)
2038 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
2039 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
2040 #define EXTI_RTSR_TR14_Pos (14U)
2041 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
2042 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
2043 #define EXTI_RTSR_TR15_Pos (15U)
2044 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
2045 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
2046 #define EXTI_RTSR_TR16_Pos (16U)
2047 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
2048 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
2049 #define EXTI_RTSR_TR17_Pos (17U)
2050 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
2051 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
2052 #define EXTI_RTSR_TR18_Pos (18U)
2053 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
2054 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
2055 #define EXTI_RTSR_TR19_Pos (19U)
2056 #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
2057 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
2058 #define EXTI_RTSR_TR20_Pos (20U)
2059 #define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
2060 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
2061 #define EXTI_RTSR_TR21_Pos (21U)
2062 #define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
2063 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
2064 #define EXTI_RTSR_TR22_Pos (22U)
2065 #define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
2066 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
2068 /****************** Bit definition for EXTI_FTSR register *******************/
2069 #define EXTI_FTSR_TR0_Pos (0U)
2070 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
2071 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
2072 #define EXTI_FTSR_TR1_Pos (1U)
2073 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
2074 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
2075 #define EXTI_FTSR_TR2_Pos (2U)
2076 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
2077 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
2078 #define EXTI_FTSR_TR3_Pos (3U)
2079 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
2080 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
2081 #define EXTI_FTSR_TR4_Pos (4U)
2082 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
2083 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
2084 #define EXTI_FTSR_TR5_Pos (5U)
2085 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
2086 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
2087 #define EXTI_FTSR_TR6_Pos (6U)
2088 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
2089 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
2090 #define EXTI_FTSR_TR7_Pos (7U)
2091 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
2092 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
2093 #define EXTI_FTSR_TR8_Pos (8U)
2094 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
2095 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
2096 #define EXTI_FTSR_TR9_Pos (9U)
2097 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
2098 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
2099 #define EXTI_FTSR_TR10_Pos (10U)
2100 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
2101 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
2102 #define EXTI_FTSR_TR11_Pos (11U)
2103 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
2104 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
2105 #define EXTI_FTSR_TR12_Pos (12U)
2106 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
2107 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
2108 #define EXTI_FTSR_TR13_Pos (13U)
2109 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
2110 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
2111 #define EXTI_FTSR_TR14_Pos (14U)
2112 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
2113 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
2114 #define EXTI_FTSR_TR15_Pos (15U)
2115 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
2116 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
2117 #define EXTI_FTSR_TR16_Pos (16U)
2118 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
2119 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
2120 #define EXTI_FTSR_TR17_Pos (17U)
2121 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
2122 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
2123 #define EXTI_FTSR_TR18_Pos (18U)
2124 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
2125 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
2126 #define EXTI_FTSR_TR19_Pos (19U)
2127 #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
2128 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
2129 #define EXTI_FTSR_TR20_Pos (20U)
2130 #define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
2131 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
2132 #define EXTI_FTSR_TR21_Pos (21U)
2133 #define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
2134 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
2135 #define EXTI_FTSR_TR22_Pos (22U)
2136 #define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
2137 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
2139 /****************** Bit definition for EXTI_SWIER register ******************/
2140 #define EXTI_SWIER_SWIER0_Pos (0U)
2141 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
2142 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
2143 #define EXTI_SWIER_SWIER1_Pos (1U)
2144 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
2145 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
2146 #define EXTI_SWIER_SWIER2_Pos (2U)
2147 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
2148 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
2149 #define EXTI_SWIER_SWIER3_Pos (3U)
2150 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
2151 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
2152 #define EXTI_SWIER_SWIER4_Pos (4U)
2153 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
2154 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
2155 #define EXTI_SWIER_SWIER5_Pos (5U)
2156 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
2157 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
2158 #define EXTI_SWIER_SWIER6_Pos (6U)
2159 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
2160 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
2161 #define EXTI_SWIER_SWIER7_Pos (7U)
2162 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
2163 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
2164 #define EXTI_SWIER_SWIER8_Pos (8U)
2165 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
2166 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
2167 #define EXTI_SWIER_SWIER9_Pos (9U)
2168 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
2169 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
2170 #define EXTI_SWIER_SWIER10_Pos (10U)
2171 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
2172 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
2173 #define EXTI_SWIER_SWIER11_Pos (11U)
2174 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
2175 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
2176 #define EXTI_SWIER_SWIER12_Pos (12U)
2177 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
2178 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
2179 #define EXTI_SWIER_SWIER13_Pos (13U)
2180 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
2181 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
2182 #define EXTI_SWIER_SWIER14_Pos (14U)
2183 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
2184 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
2185 #define EXTI_SWIER_SWIER15_Pos (15U)
2186 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
2187 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
2188 #define EXTI_SWIER_SWIER16_Pos (16U)
2189 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
2190 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
2191 #define EXTI_SWIER_SWIER17_Pos (17U)
2192 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
2193 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
2194 #define EXTI_SWIER_SWIER18_Pos (18U)
2195 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
2196 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
2197 #define EXTI_SWIER_SWIER19_Pos (19U)
2198 #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
2199 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
2200 #define EXTI_SWIER_SWIER20_Pos (20U)
2201 #define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
2202 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
2203 #define EXTI_SWIER_SWIER21_Pos (21U)
2204 #define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
2205 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
2206 #define EXTI_SWIER_SWIER22_Pos (22U)
2207 #define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
2208 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
2210 /******************* Bit definition for EXTI_PR register ********************/
2211 #define EXTI_PR_PR0_Pos (0U)
2212 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
2213 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk
2214 #define EXTI_PR_PR1_Pos (1U)
2215 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
2216 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk
2217 #define EXTI_PR_PR2_Pos (2U)
2218 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
2219 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk
2220 #define EXTI_PR_PR3_Pos (3U)
2221 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
2222 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk
2223 #define EXTI_PR_PR4_Pos (4U)
2224 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
2225 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk
2226 #define EXTI_PR_PR5_Pos (5U)
2227 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
2228 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk
2229 #define EXTI_PR_PR6_Pos (6U)
2230 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
2231 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk
2232 #define EXTI_PR_PR7_Pos (7U)
2233 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
2234 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk
2235 #define EXTI_PR_PR8_Pos (8U)
2236 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
2237 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk
2238 #define EXTI_PR_PR9_Pos (9U)
2239 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
2240 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk
2241 #define EXTI_PR_PR10_Pos (10U)
2242 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
2243 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk
2244 #define EXTI_PR_PR11_Pos (11U)
2245 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
2246 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk
2247 #define EXTI_PR_PR12_Pos (12U)
2248 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
2249 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk
2250 #define EXTI_PR_PR13_Pos (13U)
2251 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
2252 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk
2253 #define EXTI_PR_PR14_Pos (14U)
2254 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
2255 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk
2256 #define EXTI_PR_PR15_Pos (15U)
2257 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
2258 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk
2259 #define EXTI_PR_PR16_Pos (16U)
2260 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
2261 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk
2262 #define EXTI_PR_PR17_Pos (17U)
2263 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
2264 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk
2265 #define EXTI_PR_PR18_Pos (18U)
2266 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
2267 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk
2268 #define EXTI_PR_PR19_Pos (19U)
2269 #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
2270 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk
2271 #define EXTI_PR_PR20_Pos (20U)
2272 #define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
2273 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk
2274 #define EXTI_PR_PR21_Pos (21U)
2275 #define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
2276 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk
2277 #define EXTI_PR_PR22_Pos (22U)
2278 #define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
2279 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk
2281 /******************************************************************************/
2282 /* */
2283 /* FLASH */
2284 /* */
2285 /******************************************************************************/
2286 /******************* Bits definition for FLASH_ACR register *****************/
2287 #define FLASH_ACR_LATENCY_Pos (0U)
2288 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
2289 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
2290 #define FLASH_ACR_LATENCY_0WS 0x00000000U
2291 #define FLASH_ACR_LATENCY_1WS 0x00000001U
2292 #define FLASH_ACR_LATENCY_2WS 0x00000002U
2293 #define FLASH_ACR_LATENCY_3WS 0x00000003U
2294 #define FLASH_ACR_LATENCY_4WS 0x00000004U
2295 #define FLASH_ACR_LATENCY_5WS 0x00000005U
2296 #define FLASH_ACR_LATENCY_6WS 0x00000006U
2297 #define FLASH_ACR_LATENCY_7WS 0x00000007U
2298 
2299 #define FLASH_ACR_PRFTEN_Pos (8U)
2300 #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
2301 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
2302 #define FLASH_ACR_ICEN_Pos (9U)
2303 #define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos)
2304 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
2305 #define FLASH_ACR_DCEN_Pos (10U)
2306 #define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos)
2307 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
2308 #define FLASH_ACR_ICRST_Pos (11U)
2309 #define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos)
2310 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
2311 #define FLASH_ACR_DCRST_Pos (12U)
2312 #define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos)
2313 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
2314 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
2315 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos)
2316 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
2317 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
2318 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos)
2319 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
2320 
2321 /******************* Bits definition for FLASH_SR register ******************/
2322 #define FLASH_SR_EOP_Pos (0U)
2323 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
2324 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
2325 #define FLASH_SR_SOP_Pos (1U)
2326 #define FLASH_SR_SOP_Msk (0x1UL << FLASH_SR_SOP_Pos)
2327 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
2328 #define FLASH_SR_WRPERR_Pos (4U)
2329 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
2330 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
2331 #define FLASH_SR_PGAERR_Pos (5U)
2332 #define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
2333 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
2334 #define FLASH_SR_PGPERR_Pos (6U)
2335 #define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
2336 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
2337 #define FLASH_SR_PGSERR_Pos (7U)
2338 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
2339 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
2340 #define FLASH_SR_RDERR_Pos (8U)
2341 #define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
2342 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
2343 #define FLASH_SR_BSY_Pos (16U)
2344 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
2345 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
2346 
2347 /******************* Bits definition for FLASH_CR register ******************/
2348 #define FLASH_CR_PG_Pos (0U)
2349 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
2350 #define FLASH_CR_PG FLASH_CR_PG_Msk
2351 #define FLASH_CR_SER_Pos (1U)
2352 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
2353 #define FLASH_CR_SER FLASH_CR_SER_Msk
2354 #define FLASH_CR_MER_Pos (2U)
2355 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
2356 #define FLASH_CR_MER FLASH_CR_MER_Msk
2357 #define FLASH_CR_SNB_Pos (3U)
2358 #define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos)
2359 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
2360 #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos)
2361 #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos)
2362 #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos)
2363 #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos)
2364 #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos)
2365 #define FLASH_CR_PSIZE_Pos (8U)
2366 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
2367 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
2368 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
2369 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
2370 #define FLASH_CR_STRT_Pos (16U)
2371 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
2372 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
2373 #define FLASH_CR_EOPIE_Pos (24U)
2374 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
2375 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
2376 #define FLASH_CR_LOCK_Pos (31U)
2377 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
2378 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
2379 
2380 /******************* Bits definition for FLASH_OPTCR register ***************/
2381 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
2382 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
2383 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
2384 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
2385 #define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
2386 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
2387 
2388 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
2389 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
2390 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
2391 #define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
2392 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
2393 #define FLASH_OPTCR_WDG_SW_Pos (5U)
2394 #define FLASH_OPTCR_WDG_SW_Msk (0x1UL << FLASH_OPTCR_WDG_SW_Pos)
2395 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
2396 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
2397 #define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
2398 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
2399 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
2400 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
2401 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
2402 #define FLASH_OPTCR_RDP_Pos (8U)
2403 #define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
2404 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
2405 #define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
2406 #define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
2407 #define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
2408 #define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
2409 #define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
2410 #define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
2411 #define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
2412 #define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
2413 #define FLASH_OPTCR_nWRP_Pos (16U)
2414 #define FLASH_OPTCR_nWRP_Msk (0xFFFUL << FLASH_OPTCR_nWRP_Pos)
2415 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
2416 #define FLASH_OPTCR_nWRP_0 0x00010000U
2417 #define FLASH_OPTCR_nWRP_1 0x00020000U
2418 #define FLASH_OPTCR_nWRP_2 0x00040000U
2419 #define FLASH_OPTCR_nWRP_3 0x00080000U
2420 #define FLASH_OPTCR_nWRP_4 0x00100000U
2421 #define FLASH_OPTCR_nWRP_5 0x00200000U
2422 #define FLASH_OPTCR_nWRP_6 0x00400000U
2423 #define FLASH_OPTCR_nWRP_7 0x00800000U
2424 #define FLASH_OPTCR_nWRP_8 0x01000000U
2425 #define FLASH_OPTCR_nWRP_9 0x02000000U
2426 #define FLASH_OPTCR_nWRP_10 0x04000000U
2427 #define FLASH_OPTCR_nWRP_11 0x08000000U
2428 
2429 /****************** Bits definition for FLASH_OPTCR1 register ***************/
2430 #define FLASH_OPTCR1_nWRP_Pos (16U)
2431 #define FLASH_OPTCR1_nWRP_Msk (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)
2432 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
2433 #define FLASH_OPTCR1_nWRP_0 (0x001UL << FLASH_OPTCR1_nWRP_Pos)
2434 #define FLASH_OPTCR1_nWRP_1 (0x002UL << FLASH_OPTCR1_nWRP_Pos)
2435 #define FLASH_OPTCR1_nWRP_2 (0x004UL << FLASH_OPTCR1_nWRP_Pos)
2436 #define FLASH_OPTCR1_nWRP_3 (0x008UL << FLASH_OPTCR1_nWRP_Pos)
2437 #define FLASH_OPTCR1_nWRP_4 (0x010UL << FLASH_OPTCR1_nWRP_Pos)
2438 #define FLASH_OPTCR1_nWRP_5 (0x020UL << FLASH_OPTCR1_nWRP_Pos)
2439 #define FLASH_OPTCR1_nWRP_6 (0x040UL << FLASH_OPTCR1_nWRP_Pos)
2440 #define FLASH_OPTCR1_nWRP_7 (0x080UL << FLASH_OPTCR1_nWRP_Pos)
2441 #define FLASH_OPTCR1_nWRP_8 (0x100UL << FLASH_OPTCR1_nWRP_Pos)
2442 #define FLASH_OPTCR1_nWRP_9 (0x200UL << FLASH_OPTCR1_nWRP_Pos)
2443 #define FLASH_OPTCR1_nWRP_10 (0x400UL << FLASH_OPTCR1_nWRP_Pos)
2444 #define FLASH_OPTCR1_nWRP_11 (0x800UL << FLASH_OPTCR1_nWRP_Pos)
2446 /******************************************************************************/
2447 /* */
2448 /* General Purpose I/O */
2449 /* */
2450 /******************************************************************************/
2451 /****************** Bits definition for GPIO_MODER register *****************/
2452 #define GPIO_MODER_MODER0_Pos (0U)
2453 #define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
2454 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
2455 #define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
2456 #define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
2457 #define GPIO_MODER_MODER1_Pos (2U)
2458 #define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
2459 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
2460 #define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
2461 #define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
2462 #define GPIO_MODER_MODER2_Pos (4U)
2463 #define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
2464 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
2465 #define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
2466 #define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
2467 #define GPIO_MODER_MODER3_Pos (6U)
2468 #define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
2469 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
2470 #define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
2471 #define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
2472 #define GPIO_MODER_MODER4_Pos (8U)
2473 #define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
2474 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
2475 #define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
2476 #define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
2477 #define GPIO_MODER_MODER5_Pos (10U)
2478 #define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
2479 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
2480 #define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
2481 #define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
2482 #define GPIO_MODER_MODER6_Pos (12U)
2483 #define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
2484 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
2485 #define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
2486 #define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
2487 #define GPIO_MODER_MODER7_Pos (14U)
2488 #define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
2489 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
2490 #define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
2491 #define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
2492 #define GPIO_MODER_MODER8_Pos (16U)
2493 #define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
2494 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
2495 #define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
2496 #define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
2497 #define GPIO_MODER_MODER9_Pos (18U)
2498 #define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
2499 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
2500 #define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
2501 #define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
2502 #define GPIO_MODER_MODER10_Pos (20U)
2503 #define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
2504 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
2505 #define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
2506 #define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
2507 #define GPIO_MODER_MODER11_Pos (22U)
2508 #define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
2509 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
2510 #define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
2511 #define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
2512 #define GPIO_MODER_MODER12_Pos (24U)
2513 #define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
2514 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
2515 #define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
2516 #define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
2517 #define GPIO_MODER_MODER13_Pos (26U)
2518 #define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
2519 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
2520 #define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
2521 #define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
2522 #define GPIO_MODER_MODER14_Pos (28U)
2523 #define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
2524 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
2525 #define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
2526 #define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
2527 #define GPIO_MODER_MODER15_Pos (30U)
2528 #define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
2529 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
2530 #define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
2531 #define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
2533 /* Legacy defines */
2534 #define GPIO_MODER_MODE0_Pos GPIO_MODER_MODER0_Pos
2535 #define GPIO_MODER_MODE0_Msk GPIO_MODER_MODER0_Msk
2536 #define GPIO_MODER_MODE0 GPIO_MODER_MODER0
2537 #define GPIO_MODER_MODE0_0 GPIO_MODER_MODER0_0
2538 #define GPIO_MODER_MODE0_1 GPIO_MODER_MODER0_1
2539 #define GPIO_MODER_MODE1_Pos GPIO_MODER_MODER1_Pos
2540 #define GPIO_MODER_MODE1_Msk GPIO_MODER_MODER1_Msk
2541 #define GPIO_MODER_MODE1 GPIO_MODER_MODER1
2542 #define GPIO_MODER_MODE1_0 GPIO_MODER_MODER1_0
2543 #define GPIO_MODER_MODE1_1 GPIO_MODER_MODER1_1
2544 #define GPIO_MODER_MODE2_Pos GPIO_MODER_MODER2_PoS
2545 #define GPIO_MODER_MODE2_Msk GPIO_MODER_MODER2_Msk
2546 #define GPIO_MODER_MODE2 GPIO_MODER_MODER2
2547 #define GPIO_MODER_MODE2_0 GPIO_MODER_MODER2_0
2548 #define GPIO_MODER_MODE2_1 GPIO_MODER_MODER2_1
2549 #define GPIO_MODER_MODE3_Pos GPIO_MODER_MODER3_Pos
2550 #define GPIO_MODER_MODE3_Msk GPIO_MODER_MODER3_Msk
2551 #define GPIO_MODER_MODE3 GPIO_MODER_MODER3
2552 #define GPIO_MODER_MODE3_0 GPIO_MODER_MODER3_0
2553 #define GPIO_MODER_MODE3_1 GPIO_MODER_MODER3_1
2554 #define GPIO_MODER_MODE4_Pos GPIO_MODER_MODER4_Pos
2555 #define GPIO_MODER_MODE4_Msk GPIO_MODER_MODER4_Msk
2556 #define GPIO_MODER_MODE4 GPIO_MODER_MODER4
2557 #define GPIO_MODER_MODE4_0 GPIO_MODER_MODER4_0
2558 #define GPIO_MODER_MODE4_1 GPIO_MODER_MODER4_1
2559 #define GPIO_MODER_MODE5_Pos GPIO_MODER_MODER5_Pos
2560 #define GPIO_MODER_MODE5_Msk GPIO_MODER_MODER5_Msk
2561 #define GPIO_MODER_MODE5 GPIO_MODER_MODER5
2562 #define GPIO_MODER_MODE5_0 GPIO_MODER_MODER5_0
2563 #define GPIO_MODER_MODE5_1 GPIO_MODER_MODER5_1
2564 #define GPIO_MODER_MODE6_Pos GPIO_MODER_MODER6_Pos
2565 #define GPIO_MODER_MODE6_Msk GPIO_MODER_MODER6_Msk
2566 #define GPIO_MODER_MODE6 GPIO_MODER_MODER6
2567 #define GPIO_MODER_MODE6_0 GPIO_MODER_MODER6_0
2568 #define GPIO_MODER_MODE6_1 GPIO_MODER_MODER6_1
2569 #define GPIO_MODER_MODE7_Pos GPIO_MODER_MODER7_Pos
2570 #define GPIO_MODER_MODE7_Msk GPIO_MODER_MODER7_Msk
2571 #define GPIO_MODER_MODE7 GPIO_MODER_MODER7
2572 #define GPIO_MODER_MODE7_0 GPIO_MODER_MODER7_0
2573 #define GPIO_MODER_MODE7_1 GPIO_MODER_MODER7_1
2574 #define GPIO_MODER_MODE8_Pos GPIO_MODER_MODER8_Pos
2575 #define GPIO_MODER_MODE8_Msk GPIO_MODER_MODER2_Msk
2576 #define GPIO_MODER_MODE8 GPIO_MODER_MODER8
2577 #define GPIO_MODER_MODE8_0 GPIO_MODER_MODER8_0
2578 #define GPIO_MODER_MODE8_1 GPIO_MODER_MODER8_1
2579 #define GPIO_MODER_MODE9_Pos GPIO_MODER_MODER9_Pos
2580 #define GPIO_MODER_MODE9_Msk GPIO_MODER_MODER9_Msk
2581 #define GPIO_MODER_MODE9 GPIO_MODER_MODER9
2582 #define GPIO_MODER_MODE9_0 GPIO_MODER_MODER9_0
2583 #define GPIO_MODER_MODE9_1 GPIO_MODER_MODER9_1
2584 #define GPIO_MODER_MODE10_Pos GPIO_MODER_MODER10_Pos
2585 #define GPIO_MODER_MODE10_Msk GPIO_MODER_MODER10_Msk
2586 #define GPIO_MODER_MODE10 GPIO_MODER_MODER10
2587 #define GPIO_MODER_MODE10_0 GPIO_MODER_MODER10_0
2588 #define GPIO_MODER_MODE10_1 GPIO_MODER_MODER10_1
2589 #define GPIO_MODER_MODE11_Pos GPIO_MODER_MODER11_Pos
2590 #define GPIO_MODER_MODE11_Msk GPIO_MODER_MODER11_Msk
2591 #define GPIO_MODER_MODE11 GPIO_MODER_MODER11
2592 #define GPIO_MODER_MODE11_0 GPIO_MODER_MODER11_0
2593 #define GPIO_MODER_MODE11_1 GPIO_MODER_MODER11_1
2594 #define GPIO_MODER_MODE12_Pos GPIO_MODER_MODER12_Pos
2595 #define GPIO_MODER_MODE12_Msk GPIO_MODER_MODER12_Msk
2596 #define GPIO_MODER_MODE12 GPIO_MODER_MODER12
2597 #define GPIO_MODER_MODE12_0 GPIO_MODER_MODER12_0
2598 #define GPIO_MODER_MODE12_1 GPIO_MODER_MODER12_1
2599 #define GPIO_MODER_MODE13_Pos GPIO_MODER_MODER13_Pos
2600 #define GPIO_MODER_MODE13_Msk GPIO_MODER_MODER13_Msk
2601 #define GPIO_MODER_MODE13 GPIO_MODER_MODER13
2602 #define GPIO_MODER_MODE13_0 GPIO_MODER_MODER13_0
2603 #define GPIO_MODER_MODE13_1 GPIO_MODER_MODER13_1
2604 #define GPIO_MODER_MODE14_Pos GPIO_MODER_MODER14_Pos
2605 #define GPIO_MODER_MODE14_Msk GPIO_MODER_MODER14_Msk
2606 #define GPIO_MODER_MODE14 GPIO_MODER_MODER14
2607 #define GPIO_MODER_MODE14_0 GPIO_MODER_MODER14_0
2608 #define GPIO_MODER_MODE14_1 GPIO_MODER_MODER14_1
2609 #define GPIO_MODER_MODE15_Pos GPIO_MODER_MODER15_Pos
2610 #define GPIO_MODER_MODE15_Msk GPIO_MODER_MODER15_Msk
2611 #define GPIO_MODER_MODE15 GPIO_MODER_MODER15
2612 #define GPIO_MODER_MODE15_0 GPIO_MODER_MODER15_0
2613 #define GPIO_MODER_MODE15_1 GPIO_MODER_MODER15_1
2614 
2615 /****************** Bits definition for GPIO_OTYPER register ****************/
2616 #define GPIO_OTYPER_OT0_Pos (0U)
2617 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
2618 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
2619 #define GPIO_OTYPER_OT1_Pos (1U)
2620 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
2621 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
2622 #define GPIO_OTYPER_OT2_Pos (2U)
2623 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
2624 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
2625 #define GPIO_OTYPER_OT3_Pos (3U)
2626 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
2627 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
2628 #define GPIO_OTYPER_OT4_Pos (4U)
2629 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
2630 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
2631 #define GPIO_OTYPER_OT5_Pos (5U)
2632 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
2633 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
2634 #define GPIO_OTYPER_OT6_Pos (6U)
2635 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
2636 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
2637 #define GPIO_OTYPER_OT7_Pos (7U)
2638 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
2639 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
2640 #define GPIO_OTYPER_OT8_Pos (8U)
2641 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
2642 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
2643 #define GPIO_OTYPER_OT9_Pos (9U)
2644 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
2645 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
2646 #define GPIO_OTYPER_OT10_Pos (10U)
2647 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
2648 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
2649 #define GPIO_OTYPER_OT11_Pos (11U)
2650 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
2651 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
2652 #define GPIO_OTYPER_OT12_Pos (12U)
2653 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
2654 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
2655 #define GPIO_OTYPER_OT13_Pos (13U)
2656 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
2657 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
2658 #define GPIO_OTYPER_OT14_Pos (14U)
2659 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
2660 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
2661 #define GPIO_OTYPER_OT15_Pos (15U)
2662 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
2663 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
2664 
2665 /* Legacy defines */
2666 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
2667 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
2668 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
2669 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
2670 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
2671 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
2672 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
2673 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
2674 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
2675 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
2676 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
2677 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
2678 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
2679 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
2680 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
2681 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
2682 
2683 /****************** Bits definition for GPIO_OSPEEDR register ***************/
2684 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
2685 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
2686 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
2687 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
2688 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
2689 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
2690 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
2691 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
2692 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
2693 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
2694 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
2695 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
2696 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
2697 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
2698 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
2699 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
2700 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
2701 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
2702 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
2703 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
2704 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
2705 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
2706 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
2707 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
2708 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
2709 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
2710 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
2711 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
2712 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
2713 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
2714 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
2715 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
2716 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
2717 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
2718 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
2719 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
2720 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
2721 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
2722 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
2723 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
2724 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
2725 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
2726 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
2727 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
2728 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
2729 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
2730 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
2731 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
2732 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
2733 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
2734 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
2735 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
2736 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
2737 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
2738 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
2739 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
2740 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
2741 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
2742 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
2743 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
2744 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
2745 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
2746 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
2747 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
2748 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
2749 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
2750 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
2751 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
2752 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
2753 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
2754 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
2755 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
2756 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
2757 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
2758 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
2759 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
2760 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
2761 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
2762 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
2763 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
2765 /* Legacy defines */
2766 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
2767 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
2768 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
2769 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
2770 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
2771 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
2772 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
2773 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
2774 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
2775 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
2776 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
2777 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
2778 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
2779 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
2780 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
2781 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
2782 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
2783 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
2784 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
2785 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
2786 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
2787 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
2788 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
2789 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
2790 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
2791 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
2792 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
2793 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
2794 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
2795 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
2796 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
2797 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
2798 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
2799 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
2800 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
2801 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
2802 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
2803 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
2804 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
2805 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
2806 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
2807 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
2808 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
2809 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
2810 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
2811 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
2812 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
2813 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
2814 
2815 /****************** Bits definition for GPIO_PUPDR register *****************/
2816 #define GPIO_PUPDR_PUPD0_Pos (0U)
2817 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
2818 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
2819 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
2820 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
2821 #define GPIO_PUPDR_PUPD1_Pos (2U)
2822 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
2823 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
2824 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
2825 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
2826 #define GPIO_PUPDR_PUPD2_Pos (4U)
2827 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
2828 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
2829 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
2830 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
2831 #define GPIO_PUPDR_PUPD3_Pos (6U)
2832 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
2833 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
2834 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
2835 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
2836 #define GPIO_PUPDR_PUPD4_Pos (8U)
2837 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
2838 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
2839 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
2840 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
2841 #define GPIO_PUPDR_PUPD5_Pos (10U)
2842 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
2843 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
2844 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
2845 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
2846 #define GPIO_PUPDR_PUPD6_Pos (12U)
2847 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
2848 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
2849 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
2850 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
2851 #define GPIO_PUPDR_PUPD7_Pos (14U)
2852 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
2853 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
2854 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
2855 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
2856 #define GPIO_PUPDR_PUPD8_Pos (16U)
2857 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
2858 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
2859 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
2860 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
2861 #define GPIO_PUPDR_PUPD9_Pos (18U)
2862 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
2863 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
2864 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
2865 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
2866 #define GPIO_PUPDR_PUPD10_Pos (20U)
2867 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
2868 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
2869 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
2870 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
2871 #define GPIO_PUPDR_PUPD11_Pos (22U)
2872 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
2873 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
2874 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
2875 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
2876 #define GPIO_PUPDR_PUPD12_Pos (24U)
2877 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
2878 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
2879 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
2880 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
2881 #define GPIO_PUPDR_PUPD13_Pos (26U)
2882 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
2883 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
2884 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
2885 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
2886 #define GPIO_PUPDR_PUPD14_Pos (28U)
2887 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
2888 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
2889 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
2890 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
2891 #define GPIO_PUPDR_PUPD15_Pos (30U)
2892 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
2893 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
2894 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
2895 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
2897 /* Legacy defines */
2898 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
2899 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
2900 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
2901 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
2902 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
2903 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
2904 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
2905 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
2906 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
2907 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
2908 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
2909 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
2910 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
2911 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
2912 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
2913 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
2914 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
2915 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
2916 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
2917 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
2918 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
2919 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
2920 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
2921 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
2922 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
2923 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
2924 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
2925 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
2926 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
2927 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
2928 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
2929 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
2930 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
2931 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
2932 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
2933 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
2934 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
2935 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
2936 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
2937 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
2938 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
2939 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
2940 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
2941 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
2942 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
2943 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
2944 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
2945 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
2946 
2947 /****************** Bits definition for GPIO_IDR register *******************/
2948 #define GPIO_IDR_ID0_Pos (0U)
2949 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
2950 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
2951 #define GPIO_IDR_ID1_Pos (1U)
2952 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
2953 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
2954 #define GPIO_IDR_ID2_Pos (2U)
2955 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
2956 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
2957 #define GPIO_IDR_ID3_Pos (3U)
2958 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
2959 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
2960 #define GPIO_IDR_ID4_Pos (4U)
2961 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
2962 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
2963 #define GPIO_IDR_ID5_Pos (5U)
2964 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
2965 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
2966 #define GPIO_IDR_ID6_Pos (6U)
2967 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
2968 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
2969 #define GPIO_IDR_ID7_Pos (7U)
2970 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
2971 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
2972 #define GPIO_IDR_ID8_Pos (8U)
2973 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
2974 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
2975 #define GPIO_IDR_ID9_Pos (9U)
2976 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
2977 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
2978 #define GPIO_IDR_ID10_Pos (10U)
2979 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
2980 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
2981 #define GPIO_IDR_ID11_Pos (11U)
2982 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
2983 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
2984 #define GPIO_IDR_ID12_Pos (12U)
2985 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
2986 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
2987 #define GPIO_IDR_ID13_Pos (13U)
2988 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
2989 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
2990 #define GPIO_IDR_ID14_Pos (14U)
2991 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
2992 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
2993 #define GPIO_IDR_ID15_Pos (15U)
2994 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
2995 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
2996 
2997 /* Legacy defines */
2998 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
2999 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
3000 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
3001 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
3002 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
3003 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
3004 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
3005 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
3006 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
3007 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
3008 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
3009 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
3010 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
3011 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
3012 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
3013 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
3014 
3015 /****************** Bits definition for GPIO_ODR register *******************/
3016 #define GPIO_ODR_OD0_Pos (0U)
3017 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
3018 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
3019 #define GPIO_ODR_OD1_Pos (1U)
3020 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
3021 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
3022 #define GPIO_ODR_OD2_Pos (2U)
3023 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
3024 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
3025 #define GPIO_ODR_OD3_Pos (3U)
3026 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
3027 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
3028 #define GPIO_ODR_OD4_Pos (4U)
3029 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
3030 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
3031 #define GPIO_ODR_OD5_Pos (5U)
3032 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
3033 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
3034 #define GPIO_ODR_OD6_Pos (6U)
3035 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
3036 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
3037 #define GPIO_ODR_OD7_Pos (7U)
3038 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
3039 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
3040 #define GPIO_ODR_OD8_Pos (8U)
3041 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
3042 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
3043 #define GPIO_ODR_OD9_Pos (9U)
3044 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
3045 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
3046 #define GPIO_ODR_OD10_Pos (10U)
3047 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
3048 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
3049 #define GPIO_ODR_OD11_Pos (11U)
3050 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
3051 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
3052 #define GPIO_ODR_OD12_Pos (12U)
3053 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
3054 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
3055 #define GPIO_ODR_OD13_Pos (13U)
3056 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
3057 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
3058 #define GPIO_ODR_OD14_Pos (14U)
3059 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
3060 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
3061 #define GPIO_ODR_OD15_Pos (15U)
3062 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
3063 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
3064 /* Legacy defines */
3065 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
3066 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
3067 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
3068 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
3069 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
3070 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
3071 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
3072 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
3073 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
3074 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
3075 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
3076 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
3077 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
3078 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
3079 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
3080 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
3081 
3082 /****************** Bits definition for GPIO_BSRR register ******************/
3083 #define GPIO_BSRR_BS0_Pos (0U)
3084 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
3085 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
3086 #define GPIO_BSRR_BS1_Pos (1U)
3087 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
3088 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
3089 #define GPIO_BSRR_BS2_Pos (2U)
3090 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
3091 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
3092 #define GPIO_BSRR_BS3_Pos (3U)
3093 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
3094 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
3095 #define GPIO_BSRR_BS4_Pos (4U)
3096 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
3097 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
3098 #define GPIO_BSRR_BS5_Pos (5U)
3099 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
3100 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
3101 #define GPIO_BSRR_BS6_Pos (6U)
3102 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
3103 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
3104 #define GPIO_BSRR_BS7_Pos (7U)
3105 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
3106 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
3107 #define GPIO_BSRR_BS8_Pos (8U)
3108 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
3109 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
3110 #define GPIO_BSRR_BS9_Pos (9U)
3111 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
3112 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
3113 #define GPIO_BSRR_BS10_Pos (10U)
3114 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
3115 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
3116 #define GPIO_BSRR_BS11_Pos (11U)
3117 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
3118 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
3119 #define GPIO_BSRR_BS12_Pos (12U)
3120 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
3121 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
3122 #define GPIO_BSRR_BS13_Pos (13U)
3123 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
3124 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
3125 #define GPIO_BSRR_BS14_Pos (14U)
3126 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
3127 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
3128 #define GPIO_BSRR_BS15_Pos (15U)
3129 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
3130 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
3131 #define GPIO_BSRR_BR0_Pos (16U)
3132 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
3133 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
3134 #define GPIO_BSRR_BR1_Pos (17U)
3135 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
3136 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
3137 #define GPIO_BSRR_BR2_Pos (18U)
3138 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
3139 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
3140 #define GPIO_BSRR_BR3_Pos (19U)
3141 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
3142 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
3143 #define GPIO_BSRR_BR4_Pos (20U)
3144 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
3145 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
3146 #define GPIO_BSRR_BR5_Pos (21U)
3147 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
3148 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
3149 #define GPIO_BSRR_BR6_Pos (22U)
3150 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
3151 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
3152 #define GPIO_BSRR_BR7_Pos (23U)
3153 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
3154 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
3155 #define GPIO_BSRR_BR8_Pos (24U)
3156 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
3157 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
3158 #define GPIO_BSRR_BR9_Pos (25U)
3159 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
3160 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
3161 #define GPIO_BSRR_BR10_Pos (26U)
3162 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
3163 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
3164 #define GPIO_BSRR_BR11_Pos (27U)
3165 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
3166 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
3167 #define GPIO_BSRR_BR12_Pos (28U)
3168 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
3169 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
3170 #define GPIO_BSRR_BR13_Pos (29U)
3171 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
3172 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
3173 #define GPIO_BSRR_BR14_Pos (30U)
3174 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
3175 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
3176 #define GPIO_BSRR_BR15_Pos (31U)
3177 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
3178 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
3179 
3180 /* Legacy defines */
3181 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
3182 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
3183 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
3184 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
3185 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
3186 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
3187 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
3188 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
3189 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
3190 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
3191 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
3192 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
3193 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
3194 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
3195 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
3196 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
3197 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
3198 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
3199 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
3200 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
3201 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
3202 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
3203 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
3204 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
3205 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
3206 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
3207 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
3208 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
3209 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
3210 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
3211 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
3212 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
3213 #define GPIO_BRR_BR0 GPIO_BSRR_BR0
3214 #define GPIO_BRR_BR0_Pos GPIO_BSRR_BR0_Pos
3215 #define GPIO_BRR_BR0_Msk GPIO_BSRR_BR0_Msk
3216 #define GPIO_BRR_BR1 GPIO_BSRR_BR1
3217 #define GPIO_BRR_BR1_Pos GPIO_BSRR_BR1_Pos
3218 #define GPIO_BRR_BR1_Msk GPIO_BSRR_BR1_Msk
3219 #define GPIO_BRR_BR2 GPIO_BSRR_BR2
3220 #define GPIO_BRR_BR2_Pos GPIO_BSRR_BR2_Pos
3221 #define GPIO_BRR_BR2_Msk GPIO_BSRR_BR2_Msk
3222 #define GPIO_BRR_BR3 GPIO_BSRR_BR3
3223 #define GPIO_BRR_BR3_Pos GPIO_BSRR_BR3_Pos
3224 #define GPIO_BRR_BR3_Msk GPIO_BSRR_BR3_Msk
3225 #define GPIO_BRR_BR4 GPIO_BSRR_BR4
3226 #define GPIO_BRR_BR4_Pos GPIO_BSRR_BR4_Pos
3227 #define GPIO_BRR_BR4_Msk GPIO_BSRR_BR4_Msk
3228 #define GPIO_BRR_BR5 GPIO_BSRR_BR5
3229 #define GPIO_BRR_BR5_Pos GPIO_BSRR_BR5_Pos
3230 #define GPIO_BRR_BR5_Msk GPIO_BSRR_BR5_Msk
3231 #define GPIO_BRR_BR6 GPIO_BSRR_BR6
3232 #define GPIO_BRR_BR6_Pos GPIO_BSRR_BR6_Pos
3233 #define GPIO_BRR_BR6_Msk GPIO_BSRR_BR6_Msk
3234 #define GPIO_BRR_BR7 GPIO_BSRR_BR7
3235 #define GPIO_BRR_BR7_Pos GPIO_BSRR_BR7_Pos
3236 #define GPIO_BRR_BR7_Msk GPIO_BSRR_BR7_Msk
3237 #define GPIO_BRR_BR8 GPIO_BSRR_BR8
3238 #define GPIO_BRR_BR8_Pos GPIO_BSRR_BR8_Pos
3239 #define GPIO_BRR_BR8_Msk GPIO_BSRR_BR8_Msk
3240 #define GPIO_BRR_BR9 GPIO_BSRR_BR9
3241 #define GPIO_BRR_BR9_Pos GPIO_BSRR_BR9_Pos
3242 #define GPIO_BRR_BR9_Msk GPIO_BSRR_BR9_Msk
3243 #define GPIO_BRR_BR10 GPIO_BSRR_BR10
3244 #define GPIO_BRR_BR10_Pos GPIO_BSRR_BR10_Pos
3245 #define GPIO_BRR_BR10_Msk GPIO_BSRR_BR10_Msk
3246 #define GPIO_BRR_BR11 GPIO_BSRR_BR11
3247 #define GPIO_BRR_BR11_Pos GPIO_BSRR_BR11_Pos
3248 #define GPIO_BRR_BR11_Msk GPIO_BSRR_BR11_Msk
3249 #define GPIO_BRR_BR12 GPIO_BSRR_BR12
3250 #define GPIO_BRR_BR12_Pos GPIO_BSRR_BR12_Pos
3251 #define GPIO_BRR_BR12_Msk GPIO_BSRR_BR12_Msk
3252 #define GPIO_BRR_BR13 GPIO_BSRR_BR13
3253 #define GPIO_BRR_BR13_Pos GPIO_BSRR_BR13_Pos
3254 #define GPIO_BRR_BR13_Msk GPIO_BSRR_BR13_Msk
3255 #define GPIO_BRR_BR14 GPIO_BSRR_BR14
3256 #define GPIO_BRR_BR14_Pos GPIO_BSRR_BR14_Pos
3257 #define GPIO_BRR_BR14_Msk GPIO_BSRR_BR14_Msk
3258 #define GPIO_BRR_BR15 GPIO_BSRR_BR15
3259 #define GPIO_BRR_BR15_Pos GPIO_BSRR_BR15_Pos
3260 #define GPIO_BRR_BR15_Msk GPIO_BSRR_BR15_Msk
3261 /****************** Bit definition for GPIO_LCKR register *********************/
3262 #define GPIO_LCKR_LCK0_Pos (0U)
3263 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
3264 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
3265 #define GPIO_LCKR_LCK1_Pos (1U)
3266 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
3267 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
3268 #define GPIO_LCKR_LCK2_Pos (2U)
3269 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
3270 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
3271 #define GPIO_LCKR_LCK3_Pos (3U)
3272 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
3273 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
3274 #define GPIO_LCKR_LCK4_Pos (4U)
3275 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
3276 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
3277 #define GPIO_LCKR_LCK5_Pos (5U)
3278 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
3279 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
3280 #define GPIO_LCKR_LCK6_Pos (6U)
3281 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
3282 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
3283 #define GPIO_LCKR_LCK7_Pos (7U)
3284 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
3285 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
3286 #define GPIO_LCKR_LCK8_Pos (8U)
3287 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
3288 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
3289 #define GPIO_LCKR_LCK9_Pos (9U)
3290 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
3291 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
3292 #define GPIO_LCKR_LCK10_Pos (10U)
3293 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
3294 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
3295 #define GPIO_LCKR_LCK11_Pos (11U)
3296 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
3297 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
3298 #define GPIO_LCKR_LCK12_Pos (12U)
3299 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
3300 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
3301 #define GPIO_LCKR_LCK13_Pos (13U)
3302 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
3303 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
3304 #define GPIO_LCKR_LCK14_Pos (14U)
3305 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
3306 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
3307 #define GPIO_LCKR_LCK15_Pos (15U)
3308 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
3309 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
3310 #define GPIO_LCKR_LCKK_Pos (16U)
3311 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
3312 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
3313 /****************** Bit definition for GPIO_AFRL register *********************/
3314 #define GPIO_AFRL_AFSEL0_Pos (0U)
3315 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
3316 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
3317 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
3318 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
3319 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
3320 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
3321 #define GPIO_AFRL_AFSEL1_Pos (4U)
3322 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
3323 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
3324 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
3325 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
3326 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
3327 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
3328 #define GPIO_AFRL_AFSEL2_Pos (8U)
3329 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
3330 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
3331 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
3332 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
3333 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
3334 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
3335 #define GPIO_AFRL_AFSEL3_Pos (12U)
3336 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
3337 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
3338 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
3339 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
3340 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
3341 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
3342 #define GPIO_AFRL_AFSEL4_Pos (16U)
3343 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
3344 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
3345 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
3346 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
3347 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
3348 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
3349 #define GPIO_AFRL_AFSEL5_Pos (20U)
3350 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
3351 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
3352 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
3353 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
3354 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
3355 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
3356 #define GPIO_AFRL_AFSEL6_Pos (24U)
3357 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
3358 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
3359 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
3360 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
3361 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
3362 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
3363 #define GPIO_AFRL_AFSEL7_Pos (28U)
3364 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
3365 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
3366 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
3367 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
3368 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
3369 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
3371 /* Legacy defines */
3372 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
3373 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
3374 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
3375 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
3376 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
3377 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
3378 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
3379 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
3380 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
3381 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
3382 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
3383 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
3384 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
3385 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
3386 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
3387 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
3388 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
3389 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
3390 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
3391 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
3392 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
3393 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
3394 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
3395 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
3396 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
3397 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
3398 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
3399 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
3400 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
3401 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
3402 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
3403 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
3404 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
3405 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
3406 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
3407 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
3408 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
3409 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
3410 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
3411 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
3412 
3413 /****************** Bit definition for GPIO_AFRH register *********************/
3414 #define GPIO_AFRH_AFSEL8_Pos (0U)
3415 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
3416 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
3417 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
3418 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
3419 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
3420 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
3421 #define GPIO_AFRH_AFSEL9_Pos (4U)
3422 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
3423 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
3424 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
3425 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
3426 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
3427 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
3428 #define GPIO_AFRH_AFSEL10_Pos (8U)
3429 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
3430 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
3431 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
3432 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
3433 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
3434 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
3435 #define GPIO_AFRH_AFSEL11_Pos (12U)
3436 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
3437 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
3438 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
3439 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
3440 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
3441 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
3442 #define GPIO_AFRH_AFSEL12_Pos (16U)
3443 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
3444 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
3445 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
3446 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
3447 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
3448 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
3449 #define GPIO_AFRH_AFSEL13_Pos (20U)
3450 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
3451 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
3452 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
3453 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
3454 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
3455 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
3456 #define GPIO_AFRH_AFSEL14_Pos (24U)
3457 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
3458 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
3459 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
3460 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
3461 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
3462 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
3463 #define GPIO_AFRH_AFSEL15_Pos (28U)
3464 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
3465 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
3466 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
3467 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
3468 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
3469 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
3471 /* Legacy defines */
3472 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
3473 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
3474 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
3475 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
3476 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
3477 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
3478 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
3479 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
3480 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
3481 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
3482 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
3483 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
3484 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
3485 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
3486 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
3487 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
3488 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
3489 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
3490 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
3491 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
3492 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
3493 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
3494 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
3495 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
3496 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
3497 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
3498 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
3499 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
3500 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
3501 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
3502 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
3503 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
3504 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
3505 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
3506 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
3507 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
3508 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
3509 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
3510 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
3511 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
3512 
3513 
3514 /******************************************************************************/
3515 /* */
3516 /* Inter-integrated Circuit Interface */
3517 /* */
3518 /******************************************************************************/
3519 /******************* Bit definition for I2C_CR1 register ********************/
3520 #define I2C_CR1_PE_Pos (0U)
3521 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
3522 #define I2C_CR1_PE I2C_CR1_PE_Msk
3523 #define I2C_CR1_SMBUS_Pos (1U)
3524 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
3525 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
3526 #define I2C_CR1_SMBTYPE_Pos (3U)
3527 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
3528 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
3529 #define I2C_CR1_ENARP_Pos (4U)
3530 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
3531 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
3532 #define I2C_CR1_ENPEC_Pos (5U)
3533 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
3534 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
3535 #define I2C_CR1_ENGC_Pos (6U)
3536 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
3537 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
3538 #define I2C_CR1_NOSTRETCH_Pos (7U)
3539 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
3540 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
3541 #define I2C_CR1_START_Pos (8U)
3542 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
3543 #define I2C_CR1_START I2C_CR1_START_Msk
3544 #define I2C_CR1_STOP_Pos (9U)
3545 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
3546 #define I2C_CR1_STOP I2C_CR1_STOP_Msk
3547 #define I2C_CR1_ACK_Pos (10U)
3548 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
3549 #define I2C_CR1_ACK I2C_CR1_ACK_Msk
3550 #define I2C_CR1_POS_Pos (11U)
3551 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
3552 #define I2C_CR1_POS I2C_CR1_POS_Msk
3553 #define I2C_CR1_PEC_Pos (12U)
3554 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
3555 #define I2C_CR1_PEC I2C_CR1_PEC_Msk
3556 #define I2C_CR1_ALERT_Pos (13U)
3557 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
3558 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
3559 #define I2C_CR1_SWRST_Pos (15U)
3560 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
3561 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
3563 /******************* Bit definition for I2C_CR2 register ********************/
3564 #define I2C_CR2_FREQ_Pos (0U)
3565 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
3566 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
3567 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
3568 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
3569 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
3570 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
3571 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
3572 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
3574 #define I2C_CR2_ITERREN_Pos (8U)
3575 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
3576 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
3577 #define I2C_CR2_ITEVTEN_Pos (9U)
3578 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
3579 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
3580 #define I2C_CR2_ITBUFEN_Pos (10U)
3581 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
3582 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
3583 #define I2C_CR2_DMAEN_Pos (11U)
3584 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
3585 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
3586 #define I2C_CR2_LAST_Pos (12U)
3587 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
3588 #define I2C_CR2_LAST I2C_CR2_LAST_Msk
3590 /******************* Bit definition for I2C_OAR1 register *******************/
3591 #define I2C_OAR1_ADD1_7 0x000000FEU
3592 #define I2C_OAR1_ADD8_9 0x00000300U
3594 #define I2C_OAR1_ADD0_Pos (0U)
3595 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
3596 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
3597 #define I2C_OAR1_ADD1_Pos (1U)
3598 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
3599 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
3600 #define I2C_OAR1_ADD2_Pos (2U)
3601 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
3602 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
3603 #define I2C_OAR1_ADD3_Pos (3U)
3604 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
3605 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
3606 #define I2C_OAR1_ADD4_Pos (4U)
3607 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
3608 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
3609 #define I2C_OAR1_ADD5_Pos (5U)
3610 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
3611 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
3612 #define I2C_OAR1_ADD6_Pos (6U)
3613 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
3614 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
3615 #define I2C_OAR1_ADD7_Pos (7U)
3616 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
3617 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
3618 #define I2C_OAR1_ADD8_Pos (8U)
3619 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
3620 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
3621 #define I2C_OAR1_ADD9_Pos (9U)
3622 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
3623 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
3625 #define I2C_OAR1_ADDMODE_Pos (15U)
3626 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
3627 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
3629 /******************* Bit definition for I2C_OAR2 register *******************/
3630 #define I2C_OAR2_ENDUAL_Pos (0U)
3631 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
3632 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
3633 #define I2C_OAR2_ADD2_Pos (1U)
3634 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
3635 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
3637 /******************** Bit definition for I2C_DR register ********************/
3638 #define I2C_DR_DR_Pos (0U)
3639 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
3640 #define I2C_DR_DR I2C_DR_DR_Msk
3642 /******************* Bit definition for I2C_SR1 register ********************/
3643 #define I2C_SR1_SB_Pos (0U)
3644 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
3645 #define I2C_SR1_SB I2C_SR1_SB_Msk
3646 #define I2C_SR1_ADDR_Pos (1U)
3647 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
3648 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
3649 #define I2C_SR1_BTF_Pos (2U)
3650 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
3651 #define I2C_SR1_BTF I2C_SR1_BTF_Msk
3652 #define I2C_SR1_ADD10_Pos (3U)
3653 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
3654 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
3655 #define I2C_SR1_STOPF_Pos (4U)
3656 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
3657 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
3658 #define I2C_SR1_RXNE_Pos (6U)
3659 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
3660 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
3661 #define I2C_SR1_TXE_Pos (7U)
3662 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
3663 #define I2C_SR1_TXE I2C_SR1_TXE_Msk
3664 #define I2C_SR1_BERR_Pos (8U)
3665 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
3666 #define I2C_SR1_BERR I2C_SR1_BERR_Msk
3667 #define I2C_SR1_ARLO_Pos (9U)
3668 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
3669 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
3670 #define I2C_SR1_AF_Pos (10U)
3671 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
3672 #define I2C_SR1_AF I2C_SR1_AF_Msk
3673 #define I2C_SR1_OVR_Pos (11U)
3674 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
3675 #define I2C_SR1_OVR I2C_SR1_OVR_Msk
3676 #define I2C_SR1_PECERR_Pos (12U)
3677 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
3678 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
3679 #define I2C_SR1_TIMEOUT_Pos (14U)
3680 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
3681 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
3682 #define I2C_SR1_SMBALERT_Pos (15U)
3683 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
3684 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
3686 /******************* Bit definition for I2C_SR2 register ********************/
3687 #define I2C_SR2_MSL_Pos (0U)
3688 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
3689 #define I2C_SR2_MSL I2C_SR2_MSL_Msk
3690 #define I2C_SR2_BUSY_Pos (1U)
3691 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
3692 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
3693 #define I2C_SR2_TRA_Pos (2U)
3694 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
3695 #define I2C_SR2_TRA I2C_SR2_TRA_Msk
3696 #define I2C_SR2_GENCALL_Pos (4U)
3697 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
3698 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
3699 #define I2C_SR2_SMBDEFAULT_Pos (5U)
3700 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
3701 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
3702 #define I2C_SR2_SMBHOST_Pos (6U)
3703 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
3704 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
3705 #define I2C_SR2_DUALF_Pos (7U)
3706 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
3707 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
3708 #define I2C_SR2_PEC_Pos (8U)
3709 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
3710 #define I2C_SR2_PEC I2C_SR2_PEC_Msk
3712 /******************* Bit definition for I2C_CCR register ********************/
3713 #define I2C_CCR_CCR_Pos (0U)
3714 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
3715 #define I2C_CCR_CCR I2C_CCR_CCR_Msk
3716 #define I2C_CCR_DUTY_Pos (14U)
3717 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
3718 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
3719 #define I2C_CCR_FS_Pos (15U)
3720 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
3721 #define I2C_CCR_FS I2C_CCR_FS_Msk
3723 /****************** Bit definition for I2C_TRISE register *******************/
3724 #define I2C_TRISE_TRISE_Pos (0U)
3725 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
3726 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
3728 /****************** Bit definition for I2C_FLTR register *******************/
3729 #define I2C_FLTR_DNF_Pos (0U)
3730 #define I2C_FLTR_DNF_Msk (0xFUL << I2C_FLTR_DNF_Pos)
3731 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk
3732 #define I2C_FLTR_ANOFF_Pos (4U)
3733 #define I2C_FLTR_ANOFF_Msk (0x1UL << I2C_FLTR_ANOFF_Pos)
3734 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk
3736 /******************************************************************************/
3737 /* */
3738 /* Independent WATCHDOG */
3739 /* */
3740 /******************************************************************************/
3741 /******************* Bit definition for IWDG_KR register ********************/
3742 #define IWDG_KR_KEY_Pos (0U)
3743 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
3744 #define IWDG_KR_KEY IWDG_KR_KEY_Msk
3746 /******************* Bit definition for IWDG_PR register ********************/
3747 #define IWDG_PR_PR_Pos (0U)
3748 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
3749 #define IWDG_PR_PR IWDG_PR_PR_Msk
3750 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
3751 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
3752 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
3754 /******************* Bit definition for IWDG_RLR register *******************/
3755 #define IWDG_RLR_RL_Pos (0U)
3756 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
3757 #define IWDG_RLR_RL IWDG_RLR_RL_Msk
3759 /******************* Bit definition for IWDG_SR register ********************/
3760 #define IWDG_SR_PVU_Pos (0U)
3761 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
3762 #define IWDG_SR_PVU IWDG_SR_PVU_Msk
3763 #define IWDG_SR_RVU_Pos (1U)
3764 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
3765 #define IWDG_SR_RVU IWDG_SR_RVU_Msk
3769 /******************************************************************************/
3770 /* */
3771 /* Power Control */
3772 /* */
3773 /******************************************************************************/
3774 /******************** Bit definition for PWR_CR register ********************/
3775 #define PWR_CR_LPDS_Pos (0U)
3776 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
3777 #define PWR_CR_LPDS PWR_CR_LPDS_Msk
3778 #define PWR_CR_PDDS_Pos (1U)
3779 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
3780 #define PWR_CR_PDDS PWR_CR_PDDS_Msk
3781 #define PWR_CR_CWUF_Pos (2U)
3782 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
3783 #define PWR_CR_CWUF PWR_CR_CWUF_Msk
3784 #define PWR_CR_CSBF_Pos (3U)
3785 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
3786 #define PWR_CR_CSBF PWR_CR_CSBF_Msk
3787 #define PWR_CR_PVDE_Pos (4U)
3788 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
3789 #define PWR_CR_PVDE PWR_CR_PVDE_Msk
3791 #define PWR_CR_PLS_Pos (5U)
3792 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
3793 #define PWR_CR_PLS PWR_CR_PLS_Msk
3794 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
3795 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
3796 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
3799 #define PWR_CR_PLS_LEV0 0x00000000U
3800 #define PWR_CR_PLS_LEV1 0x00000020U
3801 #define PWR_CR_PLS_LEV2 0x00000040U
3802 #define PWR_CR_PLS_LEV3 0x00000060U
3803 #define PWR_CR_PLS_LEV4 0x00000080U
3804 #define PWR_CR_PLS_LEV5 0x000000A0U
3805 #define PWR_CR_PLS_LEV6 0x000000C0U
3806 #define PWR_CR_PLS_LEV7 0x000000E0U
3807 #define PWR_CR_DBP_Pos (8U)
3808 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
3809 #define PWR_CR_DBP PWR_CR_DBP_Msk
3810 #define PWR_CR_FPDS_Pos (9U)
3811 #define PWR_CR_FPDS_Msk (0x1UL << PWR_CR_FPDS_Pos)
3812 #define PWR_CR_FPDS PWR_CR_FPDS_Msk
3813 #define PWR_CR_LPLVDS_Pos (10U)
3814 #define PWR_CR_LPLVDS_Msk (0x1UL << PWR_CR_LPLVDS_Pos)
3815 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk
3816 #define PWR_CR_MRLVDS_Pos (11U)
3817 #define PWR_CR_MRLVDS_Msk (0x1UL << PWR_CR_MRLVDS_Pos)
3818 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk
3819 #define PWR_CR_ADCDC1_Pos (13U)
3820 #define PWR_CR_ADCDC1_Msk (0x1UL << PWR_CR_ADCDC1_Pos)
3821 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk
3822 #define PWR_CR_VOS_Pos (14U)
3823 #define PWR_CR_VOS_Msk (0x3UL << PWR_CR_VOS_Pos)
3824 #define PWR_CR_VOS PWR_CR_VOS_Msk
3825 #define PWR_CR_VOS_0 0x00004000U
3826 #define PWR_CR_VOS_1 0x00008000U
3827 #define PWR_CR_FMSSR_Pos (20U)
3828 #define PWR_CR_FMSSR_Msk (0x1UL << PWR_CR_FMSSR_Pos)
3829 #define PWR_CR_FMSSR PWR_CR_FMSSR_Msk
3830 #define PWR_CR_FISSR_Pos (21U)
3831 #define PWR_CR_FISSR_Msk (0x1UL << PWR_CR_FISSR_Pos)
3832 #define PWR_CR_FISSR PWR_CR_FISSR_Msk
3834 /* Legacy define */
3835 #define PWR_CR_PMODE PWR_CR_VOS
3836 
3837 /******************* Bit definition for PWR_CSR register ********************/
3838 #define PWR_CSR_WUF_Pos (0U)
3839 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
3840 #define PWR_CSR_WUF PWR_CSR_WUF_Msk
3841 #define PWR_CSR_SBF_Pos (1U)
3842 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
3843 #define PWR_CSR_SBF PWR_CSR_SBF_Msk
3844 #define PWR_CSR_PVDO_Pos (2U)
3845 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
3846 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
3847 #define PWR_CSR_BRR_Pos (3U)
3848 #define PWR_CSR_BRR_Msk (0x1UL << PWR_CSR_BRR_Pos)
3849 #define PWR_CSR_BRR PWR_CSR_BRR_Msk
3850 #define PWR_CSR_EWUP_Pos (8U)
3851 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
3852 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
3853 #define PWR_CSR_BRE_Pos (9U)
3854 #define PWR_CSR_BRE_Msk (0x1UL << PWR_CSR_BRE_Pos)
3855 #define PWR_CSR_BRE PWR_CSR_BRE_Msk
3856 #define PWR_CSR_VOSRDY_Pos (14U)
3857 #define PWR_CSR_VOSRDY_Msk (0x1UL << PWR_CSR_VOSRDY_Pos)
3858 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk
3860 /* Legacy define */
3861 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
3862 
3863 /******************************************************************************/
3864 /* */
3865 /* Reset and Clock Control */
3866 /* */
3867 /******************************************************************************/
3868 /******************** Bit definition for RCC_CR register ********************/
3869 #define RCC_CR_HSION_Pos (0U)
3870 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
3871 #define RCC_CR_HSION RCC_CR_HSION_Msk
3872 #define RCC_CR_HSIRDY_Pos (1U)
3873 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
3874 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
3875 
3876 #define RCC_CR_HSITRIM_Pos (3U)
3877 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
3878 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
3879 #define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
3880 #define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
3881 #define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
3882 #define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
3883 #define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
3885 #define RCC_CR_HSICAL_Pos (8U)
3886 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
3887 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
3888 #define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
3889 #define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
3890 #define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
3891 #define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
3892 #define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
3893 #define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
3894 #define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
3895 #define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
3897 #define RCC_CR_HSEON_Pos (16U)
3898 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
3899 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
3900 #define RCC_CR_HSERDY_Pos (17U)
3901 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
3902 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
3903 #define RCC_CR_HSEBYP_Pos (18U)
3904 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
3905 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
3906 #define RCC_CR_CSSON_Pos (19U)
3907 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
3908 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
3909 #define RCC_CR_PLLON_Pos (24U)
3910 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
3911 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
3912 #define RCC_CR_PLLRDY_Pos (25U)
3913 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
3914 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
3915 /*
3916  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
3917  */
3918 #define RCC_PLLI2S_SUPPORT
3920 #define RCC_CR_PLLI2SON_Pos (26U)
3921 #define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
3922 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
3923 #define RCC_CR_PLLI2SRDY_Pos (27U)
3924 #define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
3925 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
3926 
3927 /******************** Bit definition for RCC_PLLCFGR register ***************/
3928 #define RCC_PLLCFGR_PLLM_Pos (0U)
3929 #define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
3930 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
3931 #define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
3932 #define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
3933 #define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
3934 #define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
3935 #define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
3936 #define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
3938 #define RCC_PLLCFGR_PLLN_Pos (6U)
3939 #define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
3940 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
3941 #define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
3942 #define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
3943 #define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
3944 #define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
3945 #define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
3946 #define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
3947 #define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
3948 #define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
3949 #define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
3951 #define RCC_PLLCFGR_PLLP_Pos (16U)
3952 #define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
3953 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
3954 #define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
3955 #define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
3957 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
3958 #define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
3959 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
3960 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
3961 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
3962 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
3963 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
3964 
3965 #define RCC_PLLCFGR_PLLQ_Pos (24U)
3966 #define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
3967 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
3968 #define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
3969 #define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
3970 #define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
3971 #define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
3974 /******************** Bit definition for RCC_CFGR register ******************/
3975 
3976 #define RCC_CFGR_SW_Pos (0U)
3977 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
3978 #define RCC_CFGR_SW RCC_CFGR_SW_Msk
3979 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
3980 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
3982 #define RCC_CFGR_SW_HSI 0x00000000U
3983 #define RCC_CFGR_SW_HSE 0x00000001U
3984 #define RCC_CFGR_SW_PLL 0x00000002U
3987 #define RCC_CFGR_SWS_Pos (2U)
3988 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
3989 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
3990 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
3991 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
3993 #define RCC_CFGR_SWS_HSI 0x00000000U
3994 #define RCC_CFGR_SWS_HSE 0x00000004U
3995 #define RCC_CFGR_SWS_PLL 0x00000008U
3998 #define RCC_CFGR_HPRE_Pos (4U)
3999 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
4000 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
4001 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
4002 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
4003 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
4004 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
4006 #define RCC_CFGR_HPRE_DIV1 0x00000000U
4007 #define RCC_CFGR_HPRE_DIV2 0x00000080U
4008 #define RCC_CFGR_HPRE_DIV4 0x00000090U
4009 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
4010 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
4011 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
4012 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
4013 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
4014 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
4017 #define RCC_CFGR_PPRE1_Pos (10U)
4018 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
4019 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
4020 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
4021 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
4022 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
4024 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
4025 #define RCC_CFGR_PPRE1_DIV2 0x00001000U
4026 #define RCC_CFGR_PPRE1_DIV4 0x00001400U
4027 #define RCC_CFGR_PPRE1_DIV8 0x00001800U
4028 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U
4031 #define RCC_CFGR_PPRE2_Pos (13U)
4032 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
4033 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
4034 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
4035 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
4036 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
4038 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
4039 #define RCC_CFGR_PPRE2_DIV2 0x00008000U
4040 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U
4041 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U
4042 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U
4045 #define RCC_CFGR_RTCPRE_Pos (16U)
4046 #define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
4047 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
4048 #define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
4049 #define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
4050 #define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
4051 #define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
4052 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
4055 #define RCC_CFGR_MCO1_Pos (21U)
4056 #define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
4057 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
4058 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
4059 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
4061 #define RCC_CFGR_I2SSRC_Pos (23U)
4062 #define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
4063 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
4064 
4065 #define RCC_CFGR_MCO1PRE_Pos (24U)
4066 #define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
4067 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
4068 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
4069 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
4070 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
4072 #define RCC_CFGR_MCO2PRE_Pos (27U)
4073 #define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
4074 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
4075 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
4076 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
4077 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
4079 #define RCC_CFGR_MCO2_Pos (30U)
4080 #define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
4081 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
4082 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
4083 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
4085 /******************** Bit definition for RCC_CIR register *******************/
4086 #define RCC_CIR_LSIRDYF_Pos (0U)
4087 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
4088 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
4089 #define RCC_CIR_LSERDYF_Pos (1U)
4090 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
4091 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
4092 #define RCC_CIR_HSIRDYF_Pos (2U)
4093 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
4094 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
4095 #define RCC_CIR_HSERDYF_Pos (3U)
4096 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
4097 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
4098 #define RCC_CIR_PLLRDYF_Pos (4U)
4099 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
4100 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
4101 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
4102 #define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
4103 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
4104 
4105 #define RCC_CIR_CSSF_Pos (7U)
4106 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
4107 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
4108 #define RCC_CIR_LSIRDYIE_Pos (8U)
4109 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
4110 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
4111 #define RCC_CIR_LSERDYIE_Pos (9U)
4112 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
4113 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
4114 #define RCC_CIR_HSIRDYIE_Pos (10U)
4115 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
4116 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
4117 #define RCC_CIR_HSERDYIE_Pos (11U)
4118 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
4119 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
4120 #define RCC_CIR_PLLRDYIE_Pos (12U)
4121 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
4122 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
4123 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
4124 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
4125 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
4126 
4127 #define RCC_CIR_LSIRDYC_Pos (16U)
4128 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
4129 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
4130 #define RCC_CIR_LSERDYC_Pos (17U)
4131 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
4132 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
4133 #define RCC_CIR_HSIRDYC_Pos (18U)
4134 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
4135 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
4136 #define RCC_CIR_HSERDYC_Pos (19U)
4137 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
4138 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
4139 #define RCC_CIR_PLLRDYC_Pos (20U)
4140 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
4141 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
4142 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
4143 #define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
4144 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
4145 
4146 #define RCC_CIR_CSSC_Pos (23U)
4147 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
4148 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
4149 
4150 /******************** Bit definition for RCC_AHB1RSTR register **************/
4151 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
4152 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
4153 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
4154 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
4155 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
4156 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
4157 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
4158 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
4159 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
4160 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
4161 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
4162 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
4163 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
4164 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
4165 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
4166 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
4167 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
4168 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
4169 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
4170 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
4171 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
4172 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
4173 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
4174 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
4175 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
4176 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
4177 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
4178 
4179 /******************** Bit definition for RCC_AHB2RSTR register **************/
4180 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
4181 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
4182 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
4183 /******************** Bit definition for RCC_AHB3RSTR register **************/
4184 
4185 
4186 /******************** Bit definition for RCC_APB1RSTR register **************/
4187 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
4188 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
4189 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
4190 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
4191 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
4192 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
4193 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
4194 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
4195 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
4196 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
4197 #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
4198 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
4199 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
4200 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
4201 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
4202 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
4203 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
4204 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
4205 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
4206 #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
4207 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
4208 #define RCC_APB1RSTR_USART2RST_Pos (17U)
4209 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
4210 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
4211 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
4212 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
4213 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
4214 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
4215 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
4216 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
4217 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
4218 #define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
4219 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
4220 #define RCC_APB1RSTR_PWRRST_Pos (28U)
4221 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
4222 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
4223 
4224 /******************** Bit definition for RCC_APB2RSTR register **************/
4225 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
4226 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
4227 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
4228 #define RCC_APB2RSTR_USART1RST_Pos (4U)
4229 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
4230 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
4231 #define RCC_APB2RSTR_USART6RST_Pos (5U)
4232 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
4233 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
4234 #define RCC_APB2RSTR_ADCRST_Pos (8U)
4235 #define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
4236 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
4237 #define RCC_APB2RSTR_SDIORST_Pos (11U)
4238 #define RCC_APB2RSTR_SDIORST_Msk (0x1UL << RCC_APB2RSTR_SDIORST_Pos)
4239 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
4240 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
4241 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
4242 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
4243 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
4244 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
4245 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
4246 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
4247 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
4248 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
4249 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
4250 #define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
4251 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
4252 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
4253 #define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
4254 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
4255 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
4256 #define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
4257 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
4258 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
4259 #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
4260 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
4261 
4262 /* Old SPI1RST bit definition, maintained for legacy purpose */
4263 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
4264 
4265 /******************** Bit definition for RCC_AHB1ENR register ***************/
4266 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
4267 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
4268 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
4269 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
4270 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
4271 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
4272 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
4273 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
4274 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
4275 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
4276 #define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
4277 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
4278 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
4279 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
4280 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
4281 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
4282 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
4283 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
4284 #define RCC_AHB1ENR_CRCEN_Pos (12U)
4285 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
4286 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
4287 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
4288 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
4289 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
4290 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
4291 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
4292 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
4293 /******************** Bit definition for RCC_AHB2ENR register ***************/
4294 /*
4295  * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
4296  */
4297 #define RCC_AHB2_SUPPORT
4299 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
4300 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
4301 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
4302 
4303 /******************** Bit definition for RCC_APB1ENR register ***************/
4304 #define RCC_APB1ENR_TIM2EN_Pos (0U)
4305 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
4306 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
4307 #define RCC_APB1ENR_TIM3EN_Pos (1U)
4308 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
4309 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
4310 #define RCC_APB1ENR_TIM4EN_Pos (2U)
4311 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
4312 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
4313 #define RCC_APB1ENR_TIM5EN_Pos (3U)
4314 #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
4315 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
4316 #define RCC_APB1ENR_WWDGEN_Pos (11U)
4317 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
4318 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
4319 #define RCC_APB1ENR_SPI2EN_Pos (14U)
4320 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
4321 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
4322 #define RCC_APB1ENR_SPI3EN_Pos (15U)
4323 #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
4324 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
4325 #define RCC_APB1ENR_USART2EN_Pos (17U)
4326 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
4327 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
4328 #define RCC_APB1ENR_I2C1EN_Pos (21U)
4329 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
4330 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
4331 #define RCC_APB1ENR_I2C2EN_Pos (22U)
4332 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
4333 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
4334 #define RCC_APB1ENR_I2C3EN_Pos (23U)
4335 #define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
4336 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
4337 #define RCC_APB1ENR_PWREN_Pos (28U)
4338 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
4339 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
4340 
4341 /******************** Bit definition for RCC_APB2ENR register ***************/
4342 #define RCC_APB2ENR_TIM1EN_Pos (0U)
4343 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
4344 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
4345 #define RCC_APB2ENR_USART1EN_Pos (4U)
4346 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
4347 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
4348 #define RCC_APB2ENR_USART6EN_Pos (5U)
4349 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
4350 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
4351 #define RCC_APB2ENR_ADC1EN_Pos (8U)
4352 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
4353 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
4354 #define RCC_APB2ENR_SDIOEN_Pos (11U)
4355 #define RCC_APB2ENR_SDIOEN_Msk (0x1UL << RCC_APB2ENR_SDIOEN_Pos)
4356 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
4357 #define RCC_APB2ENR_SPI1EN_Pos (12U)
4358 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
4359 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
4360 #define RCC_APB2ENR_SPI4EN_Pos (13U)
4361 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
4362 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
4363 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
4364 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
4365 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
4366 #define RCC_APB2ENR_TIM9EN_Pos (16U)
4367 #define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
4368 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
4369 #define RCC_APB2ENR_TIM10EN_Pos (17U)
4370 #define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
4371 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
4372 #define RCC_APB2ENR_TIM11EN_Pos (18U)
4373 #define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
4374 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
4375 #define RCC_APB2ENR_SPI5EN_Pos (20U)
4376 #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
4377 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
4378 
4379 /******************** Bit definition for RCC_AHB1LPENR register *************/
4380 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
4381 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
4382 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
4383 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
4384 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
4385 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
4386 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
4387 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
4388 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
4389 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
4390 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
4391 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
4392 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
4393 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
4394 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
4395 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
4396 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
4397 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
4398 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
4399 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
4400 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
4401 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
4402 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
4403 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
4404 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
4405 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
4406 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
4407 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
4408 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
4409 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
4410 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
4411 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
4412 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
4413 
4414 
4415 /******************** Bit definition for RCC_AHB2LPENR register *************/
4416 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
4417 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
4418 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
4419 
4420 /******************** Bit definition for RCC_AHB3LPENR register *************/
4421 
4422 /******************** Bit definition for RCC_APB1LPENR register *************/
4423 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
4424 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
4425 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
4426 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
4427 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
4428 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
4429 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
4430 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
4431 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
4432 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
4433 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
4434 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
4435 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
4436 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
4437 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
4438 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
4439 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
4440 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
4441 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
4442 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
4443 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
4444 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
4445 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
4446 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
4447 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
4448 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
4449 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
4450 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
4451 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
4452 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
4453 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
4454 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
4455 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
4456 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
4457 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
4458 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
4459 
4460 /******************** Bit definition for RCC_APB2LPENR register *************/
4461 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
4462 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
4463 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
4464 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
4465 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
4466 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
4467 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
4468 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
4469 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
4470 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
4471 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
4472 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
4473 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
4474 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos)
4475 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
4476 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
4477 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
4478 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
4479 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
4480 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
4481 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
4482 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
4483 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
4484 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
4485 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
4486 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
4487 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
4488 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
4489 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
4490 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
4491 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
4492 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
4493 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
4494 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
4495 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
4496 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
4497 
4498 /******************** Bit definition for RCC_BDCR register ******************/
4499 #define RCC_BDCR_LSEON_Pos (0U)
4500 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
4501 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
4502 #define RCC_BDCR_LSERDY_Pos (1U)
4503 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
4504 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
4505 #define RCC_BDCR_LSEBYP_Pos (2U)
4506 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
4507 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
4508 #define RCC_BDCR_LSEMOD_Pos (3U)
4509 #define RCC_BDCR_LSEMOD_Msk (0x1UL << RCC_BDCR_LSEMOD_Pos)
4510 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
4511 
4512 #define RCC_BDCR_RTCSEL_Pos (8U)
4513 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
4514 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
4515 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
4516 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
4518 #define RCC_BDCR_RTCEN_Pos (15U)
4519 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
4520 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
4521 #define RCC_BDCR_BDRST_Pos (16U)
4522 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
4523 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
4524 
4525 /******************** Bit definition for RCC_CSR register *******************/
4526 #define RCC_CSR_LSION_Pos (0U)
4527 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
4528 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
4529 #define RCC_CSR_LSIRDY_Pos (1U)
4530 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
4531 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
4532 #define RCC_CSR_RMVF_Pos (24U)
4533 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
4534 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
4535 #define RCC_CSR_BORRSTF_Pos (25U)
4536 #define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
4537 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
4538 #define RCC_CSR_PINRSTF_Pos (26U)
4539 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
4540 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
4541 #define RCC_CSR_PORRSTF_Pos (27U)
4542 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
4543 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
4544 #define RCC_CSR_SFTRSTF_Pos (28U)
4545 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
4546 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
4547 #define RCC_CSR_IWDGRSTF_Pos (29U)
4548 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
4549 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
4550 #define RCC_CSR_WWDGRSTF_Pos (30U)
4551 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
4552 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
4553 #define RCC_CSR_LPWRRSTF_Pos (31U)
4554 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
4555 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
4556 /* Legacy defines */
4557 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
4558 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
4559 
4560 /******************** Bit definition for RCC_SSCGR register *****************/
4561 #define RCC_SSCGR_MODPER_Pos (0U)
4562 #define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
4563 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
4564 #define RCC_SSCGR_INCSTEP_Pos (13U)
4565 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
4566 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
4567 #define RCC_SSCGR_SPREADSEL_Pos (30U)
4568 #define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
4569 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
4570 #define RCC_SSCGR_SSCGEN_Pos (31U)
4571 #define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
4572 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
4573 
4574 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
4575 #define RCC_PLLI2SCFGR_PLLI2SM_Pos (0U)
4576 #define RCC_PLLI2SCFGR_PLLI2SM_Msk (0x3FUL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
4577 #define RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM_Msk
4578 #define RCC_PLLI2SCFGR_PLLI2SM_0 (0x01UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
4579 #define RCC_PLLI2SCFGR_PLLI2SM_1 (0x02UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
4580 #define RCC_PLLI2SCFGR_PLLI2SM_2 (0x04UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
4581 #define RCC_PLLI2SCFGR_PLLI2SM_3 (0x08UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
4582 #define RCC_PLLI2SCFGR_PLLI2SM_4 (0x10UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
4583 #define RCC_PLLI2SCFGR_PLLI2SM_5 (0x20UL << RCC_PLLI2SCFGR_PLLI2SM_Pos)
4585 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
4586 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4587 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
4588 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4589 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4590 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4591 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4592 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4593 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4594 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4595 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4596 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
4598 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
4599 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
4600 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
4601 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
4602 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
4603 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
4605 /******************** Bit definition for RCC_DCKCFGR register ***************/
4606 
4607 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
4608 #define RCC_DCKCFGR_TIMPRE_Msk (0x1UL << RCC_DCKCFGR_TIMPRE_Pos)
4609 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
4610 
4611 
4612 /******************************************************************************/
4613 /* */
4614 /* Real-Time Clock (RTC) */
4615 /* */
4616 /******************************************************************************/
4617 /******************** Bits definition for RTC_TR register *******************/
4618 #define RTC_TR_PM_Pos (22U)
4619 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
4620 #define RTC_TR_PM RTC_TR_PM_Msk
4621 #define RTC_TR_HT_Pos (20U)
4622 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
4623 #define RTC_TR_HT RTC_TR_HT_Msk
4624 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
4625 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
4626 #define RTC_TR_HU_Pos (16U)
4627 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
4628 #define RTC_TR_HU RTC_TR_HU_Msk
4629 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
4630 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
4631 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
4632 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
4633 #define RTC_TR_MNT_Pos (12U)
4634 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
4635 #define RTC_TR_MNT RTC_TR_MNT_Msk
4636 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
4637 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
4638 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
4639 #define RTC_TR_MNU_Pos (8U)
4640 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
4641 #define RTC_TR_MNU RTC_TR_MNU_Msk
4642 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
4643 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
4644 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
4645 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
4646 #define RTC_TR_ST_Pos (4U)
4647 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
4648 #define RTC_TR_ST RTC_TR_ST_Msk
4649 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
4650 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
4651 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
4652 #define RTC_TR_SU_Pos (0U)
4653 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
4654 #define RTC_TR_SU RTC_TR_SU_Msk
4655 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
4656 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
4657 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
4658 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
4660 /******************** Bits definition for RTC_DR register *******************/
4661 #define RTC_DR_YT_Pos (20U)
4662 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
4663 #define RTC_DR_YT RTC_DR_YT_Msk
4664 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
4665 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
4666 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
4667 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
4668 #define RTC_DR_YU_Pos (16U)
4669 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
4670 #define RTC_DR_YU RTC_DR_YU_Msk
4671 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
4672 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
4673 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
4674 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
4675 #define RTC_DR_WDU_Pos (13U)
4676 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
4677 #define RTC_DR_WDU RTC_DR_WDU_Msk
4678 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
4679 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
4680 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
4681 #define RTC_DR_MT_Pos (12U)
4682 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
4683 #define RTC_DR_MT RTC_DR_MT_Msk
4684 #define RTC_DR_MU_Pos (8U)
4685 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
4686 #define RTC_DR_MU RTC_DR_MU_Msk
4687 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
4688 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
4689 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
4690 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
4691 #define RTC_DR_DT_Pos (4U)
4692 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
4693 #define RTC_DR_DT RTC_DR_DT_Msk
4694 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
4695 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
4696 #define RTC_DR_DU_Pos (0U)
4697 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
4698 #define RTC_DR_DU RTC_DR_DU_Msk
4699 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
4700 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
4701 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
4702 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
4704 /******************** Bits definition for RTC_CR register *******************/
4705 #define RTC_CR_COE_Pos (23U)
4706 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
4707 #define RTC_CR_COE RTC_CR_COE_Msk
4708 #define RTC_CR_OSEL_Pos (21U)
4709 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
4710 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
4711 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
4712 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
4713 #define RTC_CR_POL_Pos (20U)
4714 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
4715 #define RTC_CR_POL RTC_CR_POL_Msk
4716 #define RTC_CR_COSEL_Pos (19U)
4717 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
4718 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
4719 #define RTC_CR_BKP_Pos (18U)
4720 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
4721 #define RTC_CR_BKP RTC_CR_BKP_Msk
4722 #define RTC_CR_SUB1H_Pos (17U)
4723 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
4724 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
4725 #define RTC_CR_ADD1H_Pos (16U)
4726 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
4727 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
4728 #define RTC_CR_TSIE_Pos (15U)
4729 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
4730 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
4731 #define RTC_CR_WUTIE_Pos (14U)
4732 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
4733 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
4734 #define RTC_CR_ALRBIE_Pos (13U)
4735 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
4736 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
4737 #define RTC_CR_ALRAIE_Pos (12U)
4738 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
4739 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
4740 #define RTC_CR_TSE_Pos (11U)
4741 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
4742 #define RTC_CR_TSE RTC_CR_TSE_Msk
4743 #define RTC_CR_WUTE_Pos (10U)
4744 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
4745 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
4746 #define RTC_CR_ALRBE_Pos (9U)
4747 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
4748 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
4749 #define RTC_CR_ALRAE_Pos (8U)
4750 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
4751 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
4752 #define RTC_CR_DCE_Pos (7U)
4753 #define RTC_CR_DCE_Msk (0x1UL << RTC_CR_DCE_Pos)
4754 #define RTC_CR_DCE RTC_CR_DCE_Msk
4755 #define RTC_CR_FMT_Pos (6U)
4756 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
4757 #define RTC_CR_FMT RTC_CR_FMT_Msk
4758 #define RTC_CR_BYPSHAD_Pos (5U)
4759 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
4760 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
4761 #define RTC_CR_REFCKON_Pos (4U)
4762 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
4763 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
4764 #define RTC_CR_TSEDGE_Pos (3U)
4765 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
4766 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
4767 #define RTC_CR_WUCKSEL_Pos (0U)
4768 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
4769 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
4770 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
4771 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
4772 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
4774 /* Legacy defines */
4775 #define RTC_CR_BCK RTC_CR_BKP
4776 
4777 /******************** Bits definition for RTC_ISR register ******************/
4778 #define RTC_ISR_RECALPF_Pos (16U)
4779 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
4780 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
4781 #define RTC_ISR_TAMP1F_Pos (13U)
4782 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
4783 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
4784 #define RTC_ISR_TAMP2F_Pos (14U)
4785 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
4786 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
4787 #define RTC_ISR_TSOVF_Pos (12U)
4788 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
4789 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
4790 #define RTC_ISR_TSF_Pos (11U)
4791 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
4792 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
4793 #define RTC_ISR_WUTF_Pos (10U)
4794 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
4795 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
4796 #define RTC_ISR_ALRBF_Pos (9U)
4797 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
4798 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
4799 #define RTC_ISR_ALRAF_Pos (8U)
4800 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
4801 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
4802 #define RTC_ISR_INIT_Pos (7U)
4803 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
4804 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
4805 #define RTC_ISR_INITF_Pos (6U)
4806 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
4807 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
4808 #define RTC_ISR_RSF_Pos (5U)
4809 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
4810 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
4811 #define RTC_ISR_INITS_Pos (4U)
4812 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
4813 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
4814 #define RTC_ISR_SHPF_Pos (3U)
4815 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
4816 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
4817 #define RTC_ISR_WUTWF_Pos (2U)
4818 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
4819 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
4820 #define RTC_ISR_ALRBWF_Pos (1U)
4821 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
4822 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
4823 #define RTC_ISR_ALRAWF_Pos (0U)
4824 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
4825 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
4826 
4827 /******************** Bits definition for RTC_PRER register *****************/
4828 #define RTC_PRER_PREDIV_A_Pos (16U)
4829 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
4830 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
4831 #define RTC_PRER_PREDIV_S_Pos (0U)
4832 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
4833 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
4834 
4835 /******************** Bits definition for RTC_WUTR register *****************/
4836 #define RTC_WUTR_WUT_Pos (0U)
4837 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
4838 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
4839 
4840 /******************** Bits definition for RTC_CALIBR register ***************/
4841 #define RTC_CALIBR_DCS_Pos (7U)
4842 #define RTC_CALIBR_DCS_Msk (0x1UL << RTC_CALIBR_DCS_Pos)
4843 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
4844 #define RTC_CALIBR_DC_Pos (0U)
4845 #define RTC_CALIBR_DC_Msk (0x1FUL << RTC_CALIBR_DC_Pos)
4846 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
4847 
4848 /******************** Bits definition for RTC_ALRMAR register ***************/
4849 #define RTC_ALRMAR_MSK4_Pos (31U)
4850 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
4851 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
4852 #define RTC_ALRMAR_WDSEL_Pos (30U)
4853 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
4854 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
4855 #define RTC_ALRMAR_DT_Pos (28U)
4856 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
4857 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
4858 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
4859 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
4860 #define RTC_ALRMAR_DU_Pos (24U)
4861 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
4862 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
4863 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
4864 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
4865 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
4866 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
4867 #define RTC_ALRMAR_MSK3_Pos (23U)
4868 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
4869 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
4870 #define RTC_ALRMAR_PM_Pos (22U)
4871 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
4872 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
4873 #define RTC_ALRMAR_HT_Pos (20U)
4874 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
4875 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
4876 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
4877 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
4878 #define RTC_ALRMAR_HU_Pos (16U)
4879 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
4880 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
4881 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
4882 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
4883 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
4884 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
4885 #define RTC_ALRMAR_MSK2_Pos (15U)
4886 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
4887 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
4888 #define RTC_ALRMAR_MNT_Pos (12U)
4889 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
4890 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
4891 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
4892 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
4893 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
4894 #define RTC_ALRMAR_MNU_Pos (8U)
4895 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
4896 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
4897 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
4898 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
4899 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
4900 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
4901 #define RTC_ALRMAR_MSK1_Pos (7U)
4902 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
4903 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
4904 #define RTC_ALRMAR_ST_Pos (4U)
4905 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
4906 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
4907 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
4908 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
4909 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
4910 #define RTC_ALRMAR_SU_Pos (0U)
4911 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
4912 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
4913 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
4914 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
4915 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
4916 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
4918 /******************** Bits definition for RTC_ALRMBR register ***************/
4919 #define RTC_ALRMBR_MSK4_Pos (31U)
4920 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
4921 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
4922 #define RTC_ALRMBR_WDSEL_Pos (30U)
4923 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
4924 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
4925 #define RTC_ALRMBR_DT_Pos (28U)
4926 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
4927 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
4928 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
4929 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
4930 #define RTC_ALRMBR_DU_Pos (24U)
4931 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
4932 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
4933 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
4934 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
4935 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
4936 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
4937 #define RTC_ALRMBR_MSK3_Pos (23U)
4938 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
4939 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
4940 #define RTC_ALRMBR_PM_Pos (22U)
4941 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
4942 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
4943 #define RTC_ALRMBR_HT_Pos (20U)
4944 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
4945 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
4946 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
4947 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
4948 #define RTC_ALRMBR_HU_Pos (16U)
4949 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
4950 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
4951 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
4952 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
4953 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
4954 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
4955 #define RTC_ALRMBR_MSK2_Pos (15U)
4956 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
4957 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
4958 #define RTC_ALRMBR_MNT_Pos (12U)
4959 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
4960 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
4961 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
4962 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
4963 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
4964 #define RTC_ALRMBR_MNU_Pos (8U)
4965 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
4966 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
4967 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
4968 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
4969 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
4970 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
4971 #define RTC_ALRMBR_MSK1_Pos (7U)
4972 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
4973 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
4974 #define RTC_ALRMBR_ST_Pos (4U)
4975 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
4976 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
4977 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
4978 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
4979 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
4980 #define RTC_ALRMBR_SU_Pos (0U)
4981 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
4982 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
4983 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
4984 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
4985 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
4986 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
4988 /******************** Bits definition for RTC_WPR register ******************/
4989 #define RTC_WPR_KEY_Pos (0U)
4990 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
4991 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
4992 
4993 /******************** Bits definition for RTC_SSR register ******************/
4994 #define RTC_SSR_SS_Pos (0U)
4995 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
4996 #define RTC_SSR_SS RTC_SSR_SS_Msk
4997 
4998 /******************** Bits definition for RTC_SHIFTR register ***************/
4999 #define RTC_SHIFTR_SUBFS_Pos (0U)
5000 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
5001 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
5002 #define RTC_SHIFTR_ADD1S_Pos (31U)
5003 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
5004 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
5005 
5006 /******************** Bits definition for RTC_TSTR register *****************/
5007 #define RTC_TSTR_PM_Pos (22U)
5008 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
5009 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
5010 #define RTC_TSTR_HT_Pos (20U)
5011 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
5012 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
5013 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
5014 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
5015 #define RTC_TSTR_HU_Pos (16U)
5016 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
5017 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
5018 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
5019 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
5020 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
5021 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
5022 #define RTC_TSTR_MNT_Pos (12U)
5023 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
5024 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
5025 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
5026 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
5027 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
5028 #define RTC_TSTR_MNU_Pos (8U)
5029 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
5030 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
5031 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
5032 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
5033 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
5034 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
5035 #define RTC_TSTR_ST_Pos (4U)
5036 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
5037 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
5038 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
5039 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
5040 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
5041 #define RTC_TSTR_SU_Pos (0U)
5042 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
5043 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
5044 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
5045 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
5046 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
5047 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
5049 /******************** Bits definition for RTC_TSDR register *****************/
5050 #define RTC_TSDR_WDU_Pos (13U)
5051 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
5052 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
5053 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
5054 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
5055 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
5056 #define RTC_TSDR_MT_Pos (12U)
5057 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
5058 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
5059 #define RTC_TSDR_MU_Pos (8U)
5060 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
5061 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
5062 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
5063 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
5064 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
5065 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
5066 #define RTC_TSDR_DT_Pos (4U)
5067 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
5068 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
5069 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
5070 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
5071 #define RTC_TSDR_DU_Pos (0U)
5072 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
5073 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
5074 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
5075 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
5076 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
5077 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
5079 /******************** Bits definition for RTC_TSSSR register ****************/
5080 #define RTC_TSSSR_SS_Pos (0U)
5081 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
5082 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
5083 
5084 /******************** Bits definition for RTC_CAL register *****************/
5085 #define RTC_CALR_CALP_Pos (15U)
5086 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
5087 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
5088 #define RTC_CALR_CALW8_Pos (14U)
5089 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
5090 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
5091 #define RTC_CALR_CALW16_Pos (13U)
5092 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
5093 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
5094 #define RTC_CALR_CALM_Pos (0U)
5095 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
5096 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
5097 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
5098 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
5099 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
5100 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
5101 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
5102 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
5103 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
5104 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
5105 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
5107 /******************** Bits definition for RTC_TAFCR register ****************/
5108 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
5109 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)
5110 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
5111 #define RTC_TAFCR_TSINSEL_Pos (17U)
5112 #define RTC_TAFCR_TSINSEL_Msk (0x1UL << RTC_TAFCR_TSINSEL_Pos)
5113 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
5114 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
5115 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)
5116 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
5117 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
5118 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)
5119 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
5120 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
5121 #define RTC_TAFCR_TAMPPRCH_Msk (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)
5122 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
5123 #define RTC_TAFCR_TAMPPRCH_0 (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)
5124 #define RTC_TAFCR_TAMPPRCH_1 (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)
5125 #define RTC_TAFCR_TAMPFLT_Pos (11U)
5126 #define RTC_TAFCR_TAMPFLT_Msk (0x3UL << RTC_TAFCR_TAMPFLT_Pos)
5127 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
5128 #define RTC_TAFCR_TAMPFLT_0 (0x1UL << RTC_TAFCR_TAMPFLT_Pos)
5129 #define RTC_TAFCR_TAMPFLT_1 (0x2UL << RTC_TAFCR_TAMPFLT_Pos)
5130 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
5131 #define RTC_TAFCR_TAMPFREQ_Msk (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)
5132 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
5133 #define RTC_TAFCR_TAMPFREQ_0 (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)
5134 #define RTC_TAFCR_TAMPFREQ_1 (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)
5135 #define RTC_TAFCR_TAMPFREQ_2 (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)
5136 #define RTC_TAFCR_TAMPTS_Pos (7U)
5137 #define RTC_TAFCR_TAMPTS_Msk (0x1UL << RTC_TAFCR_TAMPTS_Pos)
5138 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
5139 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
5140 #define RTC_TAFCR_TAMP2TRG_Msk (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)
5141 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
5142 #define RTC_TAFCR_TAMP2E_Pos (3U)
5143 #define RTC_TAFCR_TAMP2E_Msk (0x1UL << RTC_TAFCR_TAMP2E_Pos)
5144 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
5145 #define RTC_TAFCR_TAMPIE_Pos (2U)
5146 #define RTC_TAFCR_TAMPIE_Msk (0x1UL << RTC_TAFCR_TAMPIE_Pos)
5147 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
5148 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
5149 #define RTC_TAFCR_TAMP1TRG_Msk (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)
5150 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
5151 #define RTC_TAFCR_TAMP1E_Pos (0U)
5152 #define RTC_TAFCR_TAMP1E_Msk (0x1UL << RTC_TAFCR_TAMP1E_Pos)
5153 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
5154 
5155 /* Legacy defines */
5156 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
5157 
5158 /******************** Bits definition for RTC_ALRMASSR register *************/
5159 #define RTC_ALRMASSR_MASKSS_Pos (24U)
5160 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
5161 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
5162 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
5163 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
5164 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
5165 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
5166 #define RTC_ALRMASSR_SS_Pos (0U)
5167 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
5168 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
5169 
5170 /******************** Bits definition for RTC_ALRMBSSR register *************/
5171 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
5172 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
5173 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
5174 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
5175 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
5176 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
5177 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
5178 #define RTC_ALRMBSSR_SS_Pos (0U)
5179 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
5180 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
5181 
5182 /******************** Bits definition for RTC_BKP0R register ****************/
5183 #define RTC_BKP0R_Pos (0U)
5184 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
5185 #define RTC_BKP0R RTC_BKP0R_Msk
5186 
5187 /******************** Bits definition for RTC_BKP1R register ****************/
5188 #define RTC_BKP1R_Pos (0U)
5189 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
5190 #define RTC_BKP1R RTC_BKP1R_Msk
5191 
5192 /******************** Bits definition for RTC_BKP2R register ****************/
5193 #define RTC_BKP2R_Pos (0U)
5194 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
5195 #define RTC_BKP2R RTC_BKP2R_Msk
5196 
5197 /******************** Bits definition for RTC_BKP3R register ****************/
5198 #define RTC_BKP3R_Pos (0U)
5199 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
5200 #define RTC_BKP3R RTC_BKP3R_Msk
5201 
5202 /******************** Bits definition for RTC_BKP4R register ****************/
5203 #define RTC_BKP4R_Pos (0U)
5204 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
5205 #define RTC_BKP4R RTC_BKP4R_Msk
5206 
5207 /******************** Bits definition for RTC_BKP5R register ****************/
5208 #define RTC_BKP5R_Pos (0U)
5209 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
5210 #define RTC_BKP5R RTC_BKP5R_Msk
5211 
5212 /******************** Bits definition for RTC_BKP6R register ****************/
5213 #define RTC_BKP6R_Pos (0U)
5214 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
5215 #define RTC_BKP6R RTC_BKP6R_Msk
5216 
5217 /******************** Bits definition for RTC_BKP7R register ****************/
5218 #define RTC_BKP7R_Pos (0U)
5219 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
5220 #define RTC_BKP7R RTC_BKP7R_Msk
5221 
5222 /******************** Bits definition for RTC_BKP8R register ****************/
5223 #define RTC_BKP8R_Pos (0U)
5224 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
5225 #define RTC_BKP8R RTC_BKP8R_Msk
5226 
5227 /******************** Bits definition for RTC_BKP9R register ****************/
5228 #define RTC_BKP9R_Pos (0U)
5229 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
5230 #define RTC_BKP9R RTC_BKP9R_Msk
5231 
5232 /******************** Bits definition for RTC_BKP10R register ***************/
5233 #define RTC_BKP10R_Pos (0U)
5234 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
5235 #define RTC_BKP10R RTC_BKP10R_Msk
5236 
5237 /******************** Bits definition for RTC_BKP11R register ***************/
5238 #define RTC_BKP11R_Pos (0U)
5239 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
5240 #define RTC_BKP11R RTC_BKP11R_Msk
5241 
5242 /******************** Bits definition for RTC_BKP12R register ***************/
5243 #define RTC_BKP12R_Pos (0U)
5244 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
5245 #define RTC_BKP12R RTC_BKP12R_Msk
5246 
5247 /******************** Bits definition for RTC_BKP13R register ***************/
5248 #define RTC_BKP13R_Pos (0U)
5249 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
5250 #define RTC_BKP13R RTC_BKP13R_Msk
5251 
5252 /******************** Bits definition for RTC_BKP14R register ***************/
5253 #define RTC_BKP14R_Pos (0U)
5254 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
5255 #define RTC_BKP14R RTC_BKP14R_Msk
5256 
5257 /******************** Bits definition for RTC_BKP15R register ***************/
5258 #define RTC_BKP15R_Pos (0U)
5259 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
5260 #define RTC_BKP15R RTC_BKP15R_Msk
5261 
5262 /******************** Bits definition for RTC_BKP16R register ***************/
5263 #define RTC_BKP16R_Pos (0U)
5264 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
5265 #define RTC_BKP16R RTC_BKP16R_Msk
5266 
5267 /******************** Bits definition for RTC_BKP17R register ***************/
5268 #define RTC_BKP17R_Pos (0U)
5269 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
5270 #define RTC_BKP17R RTC_BKP17R_Msk
5271 
5272 /******************** Bits definition for RTC_BKP18R register ***************/
5273 #define RTC_BKP18R_Pos (0U)
5274 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
5275 #define RTC_BKP18R RTC_BKP18R_Msk
5276 
5277 /******************** Bits definition for RTC_BKP19R register ***************/
5278 #define RTC_BKP19R_Pos (0U)
5279 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
5280 #define RTC_BKP19R RTC_BKP19R_Msk
5281 
5282 /******************** Number of backup registers ******************************/
5283 #define RTC_BKP_NUMBER 0x000000014U
5284 
5285 
5286 /******************************************************************************/
5287 /* */
5288 /* SD host Interface */
5289 /* */
5290 /******************************************************************************/
5291 /****************** Bit definition for SDIO_POWER register ******************/
5292 #define SDIO_POWER_PWRCTRL_Pos (0U)
5293 #define SDIO_POWER_PWRCTRL_Msk (0x3UL << SDIO_POWER_PWRCTRL_Pos)
5294 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk
5295 #define SDIO_POWER_PWRCTRL_0 (0x1UL << SDIO_POWER_PWRCTRL_Pos)
5296 #define SDIO_POWER_PWRCTRL_1 (0x2UL << SDIO_POWER_PWRCTRL_Pos)
5298 /****************** Bit definition for SDIO_CLKCR register ******************/
5299 #define SDIO_CLKCR_CLKDIV_Pos (0U)
5300 #define SDIO_CLKCR_CLKDIV_Msk (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)
5301 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk
5302 #define SDIO_CLKCR_CLKEN_Pos (8U)
5303 #define SDIO_CLKCR_CLKEN_Msk (0x1UL << SDIO_CLKCR_CLKEN_Pos)
5304 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk
5305 #define SDIO_CLKCR_PWRSAV_Pos (9U)
5306 #define SDIO_CLKCR_PWRSAV_Msk (0x1UL << SDIO_CLKCR_PWRSAV_Pos)
5307 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk
5308 #define SDIO_CLKCR_BYPASS_Pos (10U)
5309 #define SDIO_CLKCR_BYPASS_Msk (0x1UL << SDIO_CLKCR_BYPASS_Pos)
5310 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk
5312 #define SDIO_CLKCR_WIDBUS_Pos (11U)
5313 #define SDIO_CLKCR_WIDBUS_Msk (0x3UL << SDIO_CLKCR_WIDBUS_Pos)
5314 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk
5315 #define SDIO_CLKCR_WIDBUS_0 (0x1UL << SDIO_CLKCR_WIDBUS_Pos)
5316 #define SDIO_CLKCR_WIDBUS_1 (0x2UL << SDIO_CLKCR_WIDBUS_Pos)
5318 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
5319 #define SDIO_CLKCR_NEGEDGE_Msk (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)
5320 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk
5321 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
5322 #define SDIO_CLKCR_HWFC_EN_Msk (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)
5323 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk
5325 /******************* Bit definition for SDIO_ARG register *******************/
5326 #define SDIO_ARG_CMDARG_Pos (0U)
5327 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)
5328 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk
5330 /******************* Bit definition for SDIO_CMD register *******************/
5331 #define SDIO_CMD_CMDINDEX_Pos (0U)
5332 #define SDIO_CMD_CMDINDEX_Msk (0x3FUL << SDIO_CMD_CMDINDEX_Pos)
5333 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk
5335 #define SDIO_CMD_WAITRESP_Pos (6U)
5336 #define SDIO_CMD_WAITRESP_Msk (0x3UL << SDIO_CMD_WAITRESP_Pos)
5337 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk
5338 #define SDIO_CMD_WAITRESP_0 (0x1UL << SDIO_CMD_WAITRESP_Pos)
5339 #define SDIO_CMD_WAITRESP_1 (0x2UL << SDIO_CMD_WAITRESP_Pos)
5341 #define SDIO_CMD_WAITINT_Pos (8U)
5342 #define SDIO_CMD_WAITINT_Msk (0x1UL << SDIO_CMD_WAITINT_Pos)
5343 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk
5344 #define SDIO_CMD_WAITPEND_Pos (9U)
5345 #define SDIO_CMD_WAITPEND_Msk (0x1UL << SDIO_CMD_WAITPEND_Pos)
5346 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk
5347 #define SDIO_CMD_CPSMEN_Pos (10U)
5348 #define SDIO_CMD_CPSMEN_Msk (0x1UL << SDIO_CMD_CPSMEN_Pos)
5349 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk
5350 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
5351 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)
5352 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk
5353 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
5354 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)
5355 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk
5356 #define SDIO_CMD_NIEN_Pos (13U)
5357 #define SDIO_CMD_NIEN_Msk (0x1UL << SDIO_CMD_NIEN_Pos)
5358 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk
5359 #define SDIO_CMD_CEATACMD_Pos (14U)
5360 #define SDIO_CMD_CEATACMD_Msk (0x1UL << SDIO_CMD_CEATACMD_Pos)
5361 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk
5363 /***************** Bit definition for SDIO_RESPCMD register *****************/
5364 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
5365 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)
5366 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk
5368 /****************** Bit definition for SDIO_RESP0 register ******************/
5369 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
5370 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos)
5371 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk
5373 /****************** Bit definition for SDIO_RESP1 register ******************/
5374 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
5375 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos)
5376 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk
5378 /****************** Bit definition for SDIO_RESP2 register ******************/
5379 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
5380 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos)
5381 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk
5383 /****************** Bit definition for SDIO_RESP3 register ******************/
5384 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
5385 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos)
5386 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk
5388 /****************** Bit definition for SDIO_RESP4 register ******************/
5389 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
5390 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos)
5391 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk
5393 /****************** Bit definition for SDIO_DTIMER register *****************/
5394 #define SDIO_DTIMER_DATATIME_Pos (0U)
5395 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos)
5396 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk
5398 /****************** Bit definition for SDIO_DLEN register *******************/
5399 #define SDIO_DLEN_DATALENGTH_Pos (0U)
5400 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos)
5401 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk
5403 /****************** Bit definition for SDIO_DCTRL register ******************/
5404 #define SDIO_DCTRL_DTEN_Pos (0U)
5405 #define SDIO_DCTRL_DTEN_Msk (0x1UL << SDIO_DCTRL_DTEN_Pos)
5406 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk
5407 #define SDIO_DCTRL_DTDIR_Pos (1U)
5408 #define SDIO_DCTRL_DTDIR_Msk (0x1UL << SDIO_DCTRL_DTDIR_Pos)
5409 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk
5410 #define SDIO_DCTRL_DTMODE_Pos (2U)
5411 #define SDIO_DCTRL_DTMODE_Msk (0x1UL << SDIO_DCTRL_DTMODE_Pos)
5412 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk
5413 #define SDIO_DCTRL_DMAEN_Pos (3U)
5414 #define SDIO_DCTRL_DMAEN_Msk (0x1UL << SDIO_DCTRL_DMAEN_Pos)
5415 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk
5417 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
5418 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)
5419 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk
5420 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
5421 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
5422 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
5423 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)
5425 #define SDIO_DCTRL_RWSTART_Pos (8U)
5426 #define SDIO_DCTRL_RWSTART_Msk (0x1UL << SDIO_DCTRL_RWSTART_Pos)
5427 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk
5428 #define SDIO_DCTRL_RWSTOP_Pos (9U)
5429 #define SDIO_DCTRL_RWSTOP_Msk (0x1UL << SDIO_DCTRL_RWSTOP_Pos)
5430 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk
5431 #define SDIO_DCTRL_RWMOD_Pos (10U)
5432 #define SDIO_DCTRL_RWMOD_Msk (0x1UL << SDIO_DCTRL_RWMOD_Pos)
5433 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk
5434 #define SDIO_DCTRL_SDIOEN_Pos (11U)
5435 #define SDIO_DCTRL_SDIOEN_Msk (0x1UL << SDIO_DCTRL_SDIOEN_Pos)
5436 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk
5438 /****************** Bit definition for SDIO_DCOUNT register *****************/
5439 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
5440 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos)
5441 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk
5443 /****************** Bit definition for SDIO_STA register ********************/
5444 #define SDIO_STA_CCRCFAIL_Pos (0U)
5445 #define SDIO_STA_CCRCFAIL_Msk (0x1UL << SDIO_STA_CCRCFAIL_Pos)
5446 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk
5447 #define SDIO_STA_DCRCFAIL_Pos (1U)
5448 #define SDIO_STA_DCRCFAIL_Msk (0x1UL << SDIO_STA_DCRCFAIL_Pos)
5449 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk
5450 #define SDIO_STA_CTIMEOUT_Pos (2U)
5451 #define SDIO_STA_CTIMEOUT_Msk (0x1UL << SDIO_STA_CTIMEOUT_Pos)
5452 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk
5453 #define SDIO_STA_DTIMEOUT_Pos (3U)
5454 #define SDIO_STA_DTIMEOUT_Msk (0x1UL << SDIO_STA_DTIMEOUT_Pos)
5455 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk
5456 #define SDIO_STA_TXUNDERR_Pos (4U)
5457 #define SDIO_STA_TXUNDERR_Msk (0x1UL << SDIO_STA_TXUNDERR_Pos)
5458 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk
5459 #define SDIO_STA_RXOVERR_Pos (5U)
5460 #define SDIO_STA_RXOVERR_Msk (0x1UL << SDIO_STA_RXOVERR_Pos)
5461 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk
5462 #define SDIO_STA_CMDREND_Pos (6U)
5463 #define SDIO_STA_CMDREND_Msk (0x1UL << SDIO_STA_CMDREND_Pos)
5464 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk
5465 #define SDIO_STA_CMDSENT_Pos (7U)
5466 #define SDIO_STA_CMDSENT_Msk (0x1UL << SDIO_STA_CMDSENT_Pos)
5467 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk
5468 #define SDIO_STA_DATAEND_Pos (8U)
5469 #define SDIO_STA_DATAEND_Msk (0x1UL << SDIO_STA_DATAEND_Pos)
5470 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk
5471 #define SDIO_STA_STBITERR_Pos (9U)
5472 #define SDIO_STA_STBITERR_Msk (0x1UL << SDIO_STA_STBITERR_Pos)
5473 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk
5474 #define SDIO_STA_DBCKEND_Pos (10U)
5475 #define SDIO_STA_DBCKEND_Msk (0x1UL << SDIO_STA_DBCKEND_Pos)
5476 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk
5477 #define SDIO_STA_CMDACT_Pos (11U)
5478 #define SDIO_STA_CMDACT_Msk (0x1UL << SDIO_STA_CMDACT_Pos)
5479 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk
5480 #define SDIO_STA_TXACT_Pos (12U)
5481 #define SDIO_STA_TXACT_Msk (0x1UL << SDIO_STA_TXACT_Pos)
5482 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk
5483 #define SDIO_STA_RXACT_Pos (13U)
5484 #define SDIO_STA_RXACT_Msk (0x1UL << SDIO_STA_RXACT_Pos)
5485 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk
5486 #define SDIO_STA_TXFIFOHE_Pos (14U)
5487 #define SDIO_STA_TXFIFOHE_Msk (0x1UL << SDIO_STA_TXFIFOHE_Pos)
5488 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk
5489 #define SDIO_STA_RXFIFOHF_Pos (15U)
5490 #define SDIO_STA_RXFIFOHF_Msk (0x1UL << SDIO_STA_RXFIFOHF_Pos)
5491 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk
5492 #define SDIO_STA_TXFIFOF_Pos (16U)
5493 #define SDIO_STA_TXFIFOF_Msk (0x1UL << SDIO_STA_TXFIFOF_Pos)
5494 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk
5495 #define SDIO_STA_RXFIFOF_Pos (17U)
5496 #define SDIO_STA_RXFIFOF_Msk (0x1UL << SDIO_STA_RXFIFOF_Pos)
5497 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk
5498 #define SDIO_STA_TXFIFOE_Pos (18U)
5499 #define SDIO_STA_TXFIFOE_Msk (0x1UL << SDIO_STA_TXFIFOE_Pos)
5500 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk
5501 #define SDIO_STA_RXFIFOE_Pos (19U)
5502 #define SDIO_STA_RXFIFOE_Msk (0x1UL << SDIO_STA_RXFIFOE_Pos)
5503 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk
5504 #define SDIO_STA_TXDAVL_Pos (20U)
5505 #define SDIO_STA_TXDAVL_Msk (0x1UL << SDIO_STA_TXDAVL_Pos)
5506 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk
5507 #define SDIO_STA_RXDAVL_Pos (21U)
5508 #define SDIO_STA_RXDAVL_Msk (0x1UL << SDIO_STA_RXDAVL_Pos)
5509 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk
5510 #define SDIO_STA_SDIOIT_Pos (22U)
5511 #define SDIO_STA_SDIOIT_Msk (0x1UL << SDIO_STA_SDIOIT_Pos)
5512 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk
5513 #define SDIO_STA_CEATAEND_Pos (23U)
5514 #define SDIO_STA_CEATAEND_Msk (0x1UL << SDIO_STA_CEATAEND_Pos)
5515 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk
5517 /******************* Bit definition for SDIO_ICR register *******************/
5518 #define SDIO_ICR_CCRCFAILC_Pos (0U)
5519 #define SDIO_ICR_CCRCFAILC_Msk (0x1UL << SDIO_ICR_CCRCFAILC_Pos)
5520 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk
5521 #define SDIO_ICR_DCRCFAILC_Pos (1U)
5522 #define SDIO_ICR_DCRCFAILC_Msk (0x1UL << SDIO_ICR_DCRCFAILC_Pos)
5523 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk
5524 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
5525 #define SDIO_ICR_CTIMEOUTC_Msk (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)
5526 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk
5527 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
5528 #define SDIO_ICR_DTIMEOUTC_Msk (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)
5529 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk
5530 #define SDIO_ICR_TXUNDERRC_Pos (4U)
5531 #define SDIO_ICR_TXUNDERRC_Msk (0x1UL << SDIO_ICR_TXUNDERRC_Pos)
5532 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk
5533 #define SDIO_ICR_RXOVERRC_Pos (5U)
5534 #define SDIO_ICR_RXOVERRC_Msk (0x1UL << SDIO_ICR_RXOVERRC_Pos)
5535 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk
5536 #define SDIO_ICR_CMDRENDC_Pos (6U)
5537 #define SDIO_ICR_CMDRENDC_Msk (0x1UL << SDIO_ICR_CMDRENDC_Pos)
5538 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk
5539 #define SDIO_ICR_CMDSENTC_Pos (7U)
5540 #define SDIO_ICR_CMDSENTC_Msk (0x1UL << SDIO_ICR_CMDSENTC_Pos)
5541 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk
5542 #define SDIO_ICR_DATAENDC_Pos (8U)
5543 #define SDIO_ICR_DATAENDC_Msk (0x1UL << SDIO_ICR_DATAENDC_Pos)
5544 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk
5545 #define SDIO_ICR_STBITERRC_Pos (9U)
5546 #define SDIO_ICR_STBITERRC_Msk (0x1UL << SDIO_ICR_STBITERRC_Pos)
5547 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk
5548 #define SDIO_ICR_DBCKENDC_Pos (10U)
5549 #define SDIO_ICR_DBCKENDC_Msk (0x1UL << SDIO_ICR_DBCKENDC_Pos)
5550 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk
5551 #define SDIO_ICR_SDIOITC_Pos (22U)
5552 #define SDIO_ICR_SDIOITC_Msk (0x1UL << SDIO_ICR_SDIOITC_Pos)
5553 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk
5554 #define SDIO_ICR_CEATAENDC_Pos (23U)
5555 #define SDIO_ICR_CEATAENDC_Msk (0x1UL << SDIO_ICR_CEATAENDC_Pos)
5556 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk
5558 /****************** Bit definition for SDIO_MASK register *******************/
5559 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
5560 #define SDIO_MASK_CCRCFAILIE_Msk (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)
5561 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk
5562 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
5563 #define SDIO_MASK_DCRCFAILIE_Msk (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)
5564 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk
5565 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
5566 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)
5567 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk
5568 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
5569 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)
5570 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk
5571 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
5572 #define SDIO_MASK_TXUNDERRIE_Msk (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)
5573 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk
5574 #define SDIO_MASK_RXOVERRIE_Pos (5U)
5575 #define SDIO_MASK_RXOVERRIE_Msk (0x1UL << SDIO_MASK_RXOVERRIE_Pos)
5576 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk
5577 #define SDIO_MASK_CMDRENDIE_Pos (6U)
5578 #define SDIO_MASK_CMDRENDIE_Msk (0x1UL << SDIO_MASK_CMDRENDIE_Pos)
5579 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk
5580 #define SDIO_MASK_CMDSENTIE_Pos (7U)
5581 #define SDIO_MASK_CMDSENTIE_Msk (0x1UL << SDIO_MASK_CMDSENTIE_Pos)
5582 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk
5583 #define SDIO_MASK_DATAENDIE_Pos (8U)
5584 #define SDIO_MASK_DATAENDIE_Msk (0x1UL << SDIO_MASK_DATAENDIE_Pos)
5585 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk
5586 #define SDIO_MASK_STBITERRIE_Pos (9U)
5587 #define SDIO_MASK_STBITERRIE_Msk (0x1UL << SDIO_MASK_STBITERRIE_Pos)
5588 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk
5589 #define SDIO_MASK_DBCKENDIE_Pos (10U)
5590 #define SDIO_MASK_DBCKENDIE_Msk (0x1UL << SDIO_MASK_DBCKENDIE_Pos)
5591 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk
5592 #define SDIO_MASK_CMDACTIE_Pos (11U)
5593 #define SDIO_MASK_CMDACTIE_Msk (0x1UL << SDIO_MASK_CMDACTIE_Pos)
5594 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk
5595 #define SDIO_MASK_TXACTIE_Pos (12U)
5596 #define SDIO_MASK_TXACTIE_Msk (0x1UL << SDIO_MASK_TXACTIE_Pos)
5597 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk
5598 #define SDIO_MASK_RXACTIE_Pos (13U)
5599 #define SDIO_MASK_RXACTIE_Msk (0x1UL << SDIO_MASK_RXACTIE_Pos)
5600 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk
5601 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
5602 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)
5603 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk
5604 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
5605 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)
5606 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk
5607 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
5608 #define SDIO_MASK_TXFIFOFIE_Msk (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)
5609 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk
5610 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
5611 #define SDIO_MASK_RXFIFOFIE_Msk (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)
5612 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk
5613 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
5614 #define SDIO_MASK_TXFIFOEIE_Msk (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)
5615 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk
5616 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
5617 #define SDIO_MASK_RXFIFOEIE_Msk (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)
5618 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk
5619 #define SDIO_MASK_TXDAVLIE_Pos (20U)
5620 #define SDIO_MASK_TXDAVLIE_Msk (0x1UL << SDIO_MASK_TXDAVLIE_Pos)
5621 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk
5622 #define SDIO_MASK_RXDAVLIE_Pos (21U)
5623 #define SDIO_MASK_RXDAVLIE_Msk (0x1UL << SDIO_MASK_RXDAVLIE_Pos)
5624 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk
5625 #define SDIO_MASK_SDIOITIE_Pos (22U)
5626 #define SDIO_MASK_SDIOITIE_Msk (0x1UL << SDIO_MASK_SDIOITIE_Pos)
5627 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk
5628 #define SDIO_MASK_CEATAENDIE_Pos (23U)
5629 #define SDIO_MASK_CEATAENDIE_Msk (0x1UL << SDIO_MASK_CEATAENDIE_Pos)
5630 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk
5632 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5633 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
5634 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos)
5635 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk
5637 /****************** Bit definition for SDIO_FIFO register *******************/
5638 #define SDIO_FIFO_FIFODATA_Pos (0U)
5639 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos)
5640 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk
5642 /******************************************************************************/
5643 /* */
5644 /* Serial Peripheral Interface */
5645 /* */
5646 /******************************************************************************/
5647 #define SPI_I2S_FULLDUPLEX_SUPPORT
5649 /******************* Bit definition for SPI_CR1 register ********************/
5650 #define SPI_CR1_CPHA_Pos (0U)
5651 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
5652 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
5653 #define SPI_CR1_CPOL_Pos (1U)
5654 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
5655 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
5656 #define SPI_CR1_MSTR_Pos (2U)
5657 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
5658 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
5660 #define SPI_CR1_BR_Pos (3U)
5661 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
5662 #define SPI_CR1_BR SPI_CR1_BR_Msk
5663 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
5664 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
5665 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
5667 #define SPI_CR1_SPE_Pos (6U)
5668 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
5669 #define SPI_CR1_SPE SPI_CR1_SPE_Msk
5670 #define SPI_CR1_LSBFIRST_Pos (7U)
5671 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
5672 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
5673 #define SPI_CR1_SSI_Pos (8U)
5674 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
5675 #define SPI_CR1_SSI SPI_CR1_SSI_Msk
5676 #define SPI_CR1_SSM_Pos (9U)
5677 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
5678 #define SPI_CR1_SSM SPI_CR1_SSM_Msk
5679 #define SPI_CR1_RXONLY_Pos (10U)
5680 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
5681 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
5682 #define SPI_CR1_DFF_Pos (11U)
5683 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
5684 #define SPI_CR1_DFF SPI_CR1_DFF_Msk
5685 #define SPI_CR1_CRCNEXT_Pos (12U)
5686 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
5687 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
5688 #define SPI_CR1_CRCEN_Pos (13U)
5689 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
5690 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
5691 #define SPI_CR1_BIDIOE_Pos (14U)
5692 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
5693 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
5694 #define SPI_CR1_BIDIMODE_Pos (15U)
5695 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
5696 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
5698 /******************* Bit definition for SPI_CR2 register ********************/
5699 #define SPI_CR2_RXDMAEN_Pos (0U)
5700 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
5701 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
5702 #define SPI_CR2_TXDMAEN_Pos (1U)
5703 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
5704 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
5705 #define SPI_CR2_SSOE_Pos (2U)
5706 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
5707 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
5708 #define SPI_CR2_FRF_Pos (4U)
5709 #define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
5710 #define SPI_CR2_FRF SPI_CR2_FRF_Msk
5711 #define SPI_CR2_ERRIE_Pos (5U)
5712 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
5713 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
5714 #define SPI_CR2_RXNEIE_Pos (6U)
5715 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
5716 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
5717 #define SPI_CR2_TXEIE_Pos (7U)
5718 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
5719 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
5721 /******************** Bit definition for SPI_SR register ********************/
5722 #define SPI_SR_RXNE_Pos (0U)
5723 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
5724 #define SPI_SR_RXNE SPI_SR_RXNE_Msk
5725 #define SPI_SR_TXE_Pos (1U)
5726 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
5727 #define SPI_SR_TXE SPI_SR_TXE_Msk
5728 #define SPI_SR_CHSIDE_Pos (2U)
5729 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
5730 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
5731 #define SPI_SR_UDR_Pos (3U)
5732 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
5733 #define SPI_SR_UDR SPI_SR_UDR_Msk
5734 #define SPI_SR_CRCERR_Pos (4U)
5735 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
5736 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
5737 #define SPI_SR_MODF_Pos (5U)
5738 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
5739 #define SPI_SR_MODF SPI_SR_MODF_Msk
5740 #define SPI_SR_OVR_Pos (6U)
5741 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
5742 #define SPI_SR_OVR SPI_SR_OVR_Msk
5743 #define SPI_SR_BSY_Pos (7U)
5744 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
5745 #define SPI_SR_BSY SPI_SR_BSY_Msk
5746 #define SPI_SR_FRE_Pos (8U)
5747 #define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
5748 #define SPI_SR_FRE SPI_SR_FRE_Msk
5750 /******************** Bit definition for SPI_DR register ********************/
5751 #define SPI_DR_DR_Pos (0U)
5752 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
5753 #define SPI_DR_DR SPI_DR_DR_Msk
5755 /******************* Bit definition for SPI_CRCPR register ******************/
5756 #define SPI_CRCPR_CRCPOLY_Pos (0U)
5757 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
5758 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
5760 /****************** Bit definition for SPI_RXCRCR register ******************/
5761 #define SPI_RXCRCR_RXCRC_Pos (0U)
5762 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
5763 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
5765 /****************** Bit definition for SPI_TXCRCR register ******************/
5766 #define SPI_TXCRCR_TXCRC_Pos (0U)
5767 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
5768 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
5770 /****************** Bit definition for SPI_I2SCFGR register *****************/
5771 #define SPI_I2SCFGR_CHLEN_Pos (0U)
5772 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
5773 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
5775 #define SPI_I2SCFGR_DATLEN_Pos (1U)
5776 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
5777 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
5778 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
5779 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
5781 #define SPI_I2SCFGR_CKPOL_Pos (3U)
5782 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
5783 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
5785 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
5786 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
5787 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
5788 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
5789 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
5791 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
5792 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
5793 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
5795 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
5796 #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
5797 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
5798 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
5799 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
5801 #define SPI_I2SCFGR_I2SE_Pos (10U)
5802 #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
5803 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
5804 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
5805 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
5806 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
5808 /****************** Bit definition for SPI_I2SPR register *******************/
5809 #define SPI_I2SPR_I2SDIV_Pos (0U)
5810 #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
5811 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
5812 #define SPI_I2SPR_ODD_Pos (8U)
5813 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
5814 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
5815 #define SPI_I2SPR_MCKOE_Pos (9U)
5816 #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
5817 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
5819 /******************************************************************************/
5820 /* */
5821 /* SYSCFG */
5822 /* */
5823 /******************************************************************************/
5824 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
5825 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
5826 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
5827 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk
5828 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
5829 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)
5830 /****************** Bit definition for SYSCFG_PMC register ******************/
5831 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
5832 #define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
5833 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
5835 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
5836 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
5837 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
5838 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
5839 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
5840 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
5841 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
5842 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
5843 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
5844 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
5845 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
5846 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
5847 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
5851 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
5852 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
5853 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
5854 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
5855 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
5856 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
5861 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
5862 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
5863 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
5864 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
5865 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
5866 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
5871 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
5872 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
5873 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
5874 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
5875 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
5876 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
5881 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
5882 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
5883 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
5884 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
5885 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
5886 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
5888 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
5889 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
5890 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
5891 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
5892 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
5893 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
5894 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
5895 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
5896 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
5897 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
5898 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
5899 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
5900 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
5905 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
5906 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
5907 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
5908 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
5909 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
5910 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
5915 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
5916 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
5917 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
5918 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
5919 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
5920 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
5925 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
5926 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
5927 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
5928 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
5929 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
5930 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
5935 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
5936 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
5937 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
5938 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
5939 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
5940 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
5942 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
5943 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
5944 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
5945 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
5946 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
5947 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
5948 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
5949 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
5950 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
5951 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
5952 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
5953 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
5954 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
5959 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
5960 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
5961 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
5962 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
5963 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
5964 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
5969 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
5970 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
5971 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
5972 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
5973 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
5974 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
5979 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
5980 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
5981 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
5982 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
5983 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
5984 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
5989 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
5990 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
5991 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
5992 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
5993 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
5994 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
5996 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
5997 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
5998 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
5999 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
6000 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
6001 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
6002 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
6003 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
6004 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
6005 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
6006 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
6007 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
6008 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
6013 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
6014 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
6015 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
6016 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
6017 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
6018 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
6023 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
6024 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
6025 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
6026 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
6027 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
6028 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
6033 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
6034 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
6035 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
6036 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
6037 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
6038 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
6043 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
6044 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
6045 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
6046 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
6047 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
6048 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
6050 /****************** Bit definition for SYSCFG_CMPCR register ****************/
6051 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
6052 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
6053 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
6054 #define SYSCFG_CMPCR_READY_Pos (8U)
6055 #define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
6056 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
6058 /******************************************************************************/
6059 /* */
6060 /* TIM */
6061 /* */
6062 /******************************************************************************/
6063 /******************* Bit definition for TIM_CR1 register ********************/
6064 #define TIM_CR1_CEN_Pos (0U)
6065 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
6066 #define TIM_CR1_CEN TIM_CR1_CEN_Msk
6067 #define TIM_CR1_UDIS_Pos (1U)
6068 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
6069 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
6070 #define TIM_CR1_URS_Pos (2U)
6071 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
6072 #define TIM_CR1_URS TIM_CR1_URS_Msk
6073 #define TIM_CR1_OPM_Pos (3U)
6074 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
6075 #define TIM_CR1_OPM TIM_CR1_OPM_Msk
6076 #define TIM_CR1_DIR_Pos (4U)
6077 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
6078 #define TIM_CR1_DIR TIM_CR1_DIR_Msk
6080 #define TIM_CR1_CMS_Pos (5U)
6081 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
6082 #define TIM_CR1_CMS TIM_CR1_CMS_Msk
6083 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
6084 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
6086 #define TIM_CR1_ARPE_Pos (7U)
6087 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
6088 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
6090 #define TIM_CR1_CKD_Pos (8U)
6091 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
6092 #define TIM_CR1_CKD TIM_CR1_CKD_Msk
6093 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
6094 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
6096 /******************* Bit definition for TIM_CR2 register ********************/
6097 #define TIM_CR2_CCPC_Pos (0U)
6098 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
6099 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
6100 #define TIM_CR2_CCUS_Pos (2U)
6101 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
6102 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
6103 #define TIM_CR2_CCDS_Pos (3U)
6104 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
6105 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
6107 #define TIM_CR2_MMS_Pos (4U)
6108 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
6109 #define TIM_CR2_MMS TIM_CR2_MMS_Msk
6110 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
6111 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
6112 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
6114 #define TIM_CR2_TI1S_Pos (7U)
6115 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
6116 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
6117 #define TIM_CR2_OIS1_Pos (8U)
6118 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
6119 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
6120 #define TIM_CR2_OIS1N_Pos (9U)
6121 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
6122 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
6123 #define TIM_CR2_OIS2_Pos (10U)
6124 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
6125 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
6126 #define TIM_CR2_OIS2N_Pos (11U)
6127 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
6128 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
6129 #define TIM_CR2_OIS3_Pos (12U)
6130 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
6131 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
6132 #define TIM_CR2_OIS3N_Pos (13U)
6133 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
6134 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
6135 #define TIM_CR2_OIS4_Pos (14U)
6136 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
6137 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
6139 /******************* Bit definition for TIM_SMCR register *******************/
6140 #define TIM_SMCR_SMS_Pos (0U)
6141 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
6142 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
6143 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
6144 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
6145 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
6147 #define TIM_SMCR_TS_Pos (4U)
6148 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
6149 #define TIM_SMCR_TS TIM_SMCR_TS_Msk
6150 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
6151 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
6152 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
6154 #define TIM_SMCR_MSM_Pos (7U)
6155 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
6156 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
6158 #define TIM_SMCR_ETF_Pos (8U)
6159 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
6160 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
6161 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
6162 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
6163 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
6164 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
6166 #define TIM_SMCR_ETPS_Pos (12U)
6167 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
6168 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
6169 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
6170 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
6172 #define TIM_SMCR_ECE_Pos (14U)
6173 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
6174 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
6175 #define TIM_SMCR_ETP_Pos (15U)
6176 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
6177 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
6179 /******************* Bit definition for TIM_DIER register *******************/
6180 #define TIM_DIER_UIE_Pos (0U)
6181 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
6182 #define TIM_DIER_UIE TIM_DIER_UIE_Msk
6183 #define TIM_DIER_CC1IE_Pos (1U)
6184 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
6185 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
6186 #define TIM_DIER_CC2IE_Pos (2U)
6187 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
6188 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
6189 #define TIM_DIER_CC3IE_Pos (3U)
6190 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
6191 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
6192 #define TIM_DIER_CC4IE_Pos (4U)
6193 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
6194 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
6195 #define TIM_DIER_COMIE_Pos (5U)
6196 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
6197 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
6198 #define TIM_DIER_TIE_Pos (6U)
6199 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
6200 #define TIM_DIER_TIE TIM_DIER_TIE_Msk
6201 #define TIM_DIER_BIE_Pos (7U)
6202 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
6203 #define TIM_DIER_BIE TIM_DIER_BIE_Msk
6204 #define TIM_DIER_UDE_Pos (8U)
6205 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
6206 #define TIM_DIER_UDE TIM_DIER_UDE_Msk
6207 #define TIM_DIER_CC1DE_Pos (9U)
6208 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
6209 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
6210 #define TIM_DIER_CC2DE_Pos (10U)
6211 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
6212 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
6213 #define TIM_DIER_CC3DE_Pos (11U)
6214 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
6215 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
6216 #define TIM_DIER_CC4DE_Pos (12U)
6217 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
6218 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
6219 #define TIM_DIER_COMDE_Pos (13U)
6220 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
6221 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
6222 #define TIM_DIER_TDE_Pos (14U)
6223 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
6224 #define TIM_DIER_TDE TIM_DIER_TDE_Msk
6226 /******************** Bit definition for TIM_SR register ********************/
6227 #define TIM_SR_UIF_Pos (0U)
6228 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
6229 #define TIM_SR_UIF TIM_SR_UIF_Msk
6230 #define TIM_SR_CC1IF_Pos (1U)
6231 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
6232 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
6233 #define TIM_SR_CC2IF_Pos (2U)
6234 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
6235 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
6236 #define TIM_SR_CC3IF_Pos (3U)
6237 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
6238 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
6239 #define TIM_SR_CC4IF_Pos (4U)
6240 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
6241 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
6242 #define TIM_SR_COMIF_Pos (5U)
6243 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
6244 #define TIM_SR_COMIF TIM_SR_COMIF_Msk
6245 #define TIM_SR_TIF_Pos (6U)
6246 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
6247 #define TIM_SR_TIF TIM_SR_TIF_Msk
6248 #define TIM_SR_BIF_Pos (7U)
6249 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
6250 #define TIM_SR_BIF TIM_SR_BIF_Msk
6251 #define TIM_SR_CC1OF_Pos (9U)
6252 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
6253 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
6254 #define TIM_SR_CC2OF_Pos (10U)
6255 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
6256 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
6257 #define TIM_SR_CC3OF_Pos (11U)
6258 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
6259 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
6260 #define TIM_SR_CC4OF_Pos (12U)
6261 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
6262 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
6264 /******************* Bit definition for TIM_EGR register ********************/
6265 #define TIM_EGR_UG_Pos (0U)
6266 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
6267 #define TIM_EGR_UG TIM_EGR_UG_Msk
6268 #define TIM_EGR_CC1G_Pos (1U)
6269 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
6270 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
6271 #define TIM_EGR_CC2G_Pos (2U)
6272 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
6273 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
6274 #define TIM_EGR_CC3G_Pos (3U)
6275 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
6276 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
6277 #define TIM_EGR_CC4G_Pos (4U)
6278 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
6279 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
6280 #define TIM_EGR_COMG_Pos (5U)
6281 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
6282 #define TIM_EGR_COMG TIM_EGR_COMG_Msk
6283 #define TIM_EGR_TG_Pos (6U)
6284 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
6285 #define TIM_EGR_TG TIM_EGR_TG_Msk
6286 #define TIM_EGR_BG_Pos (7U)
6287 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
6288 #define TIM_EGR_BG TIM_EGR_BG_Msk
6290 /****************** Bit definition for TIM_CCMR1 register *******************/
6291 #define TIM_CCMR1_CC1S_Pos (0U)
6292 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
6293 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
6294 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
6295 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
6297 #define TIM_CCMR1_OC1FE_Pos (2U)
6298 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
6299 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
6300 #define TIM_CCMR1_OC1PE_Pos (3U)
6301 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
6302 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
6304 #define TIM_CCMR1_OC1M_Pos (4U)
6305 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
6306 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
6307 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
6308 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
6309 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
6311 #define TIM_CCMR1_OC1CE_Pos (7U)
6312 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
6313 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
6315 #define TIM_CCMR1_CC2S_Pos (8U)
6316 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
6317 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
6318 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
6319 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
6321 #define TIM_CCMR1_OC2FE_Pos (10U)
6322 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
6323 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
6324 #define TIM_CCMR1_OC2PE_Pos (11U)
6325 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
6326 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
6328 #define TIM_CCMR1_OC2M_Pos (12U)
6329 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
6330 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
6331 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
6332 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
6333 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
6335 #define TIM_CCMR1_OC2CE_Pos (15U)
6336 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
6337 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
6339 /*----------------------------------------------------------------------------*/
6340 
6341 #define TIM_CCMR1_IC1PSC_Pos (2U)
6342 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
6343 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
6344 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
6345 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
6347 #define TIM_CCMR1_IC1F_Pos (4U)
6348 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
6349 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
6350 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
6351 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
6352 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
6353 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
6355 #define TIM_CCMR1_IC2PSC_Pos (10U)
6356 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
6357 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
6358 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
6359 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
6361 #define TIM_CCMR1_IC2F_Pos (12U)
6362 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
6363 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
6364 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
6365 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
6366 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
6367 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
6369 /****************** Bit definition for TIM_CCMR2 register *******************/
6370 #define TIM_CCMR2_CC3S_Pos (0U)
6371 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
6372 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
6373 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
6374 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
6376 #define TIM_CCMR2_OC3FE_Pos (2U)
6377 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
6378 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
6379 #define TIM_CCMR2_OC3PE_Pos (3U)
6380 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
6381 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
6383 #define TIM_CCMR2_OC3M_Pos (4U)
6384 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
6385 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
6386 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
6387 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
6388 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
6390 #define TIM_CCMR2_OC3CE_Pos (7U)
6391 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
6392 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
6394 #define TIM_CCMR2_CC4S_Pos (8U)
6395 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
6396 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
6397 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
6398 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
6400 #define TIM_CCMR2_OC4FE_Pos (10U)
6401 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
6402 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
6403 #define TIM_CCMR2_OC4PE_Pos (11U)
6404 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
6405 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
6407 #define TIM_CCMR2_OC4M_Pos (12U)
6408 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
6409 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
6410 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
6411 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
6412 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
6414 #define TIM_CCMR2_OC4CE_Pos (15U)
6415 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
6416 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
6418 /*----------------------------------------------------------------------------*/
6419 
6420 #define TIM_CCMR2_IC3PSC_Pos (2U)
6421 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
6422 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
6423 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
6424 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
6426 #define TIM_CCMR2_IC3F_Pos (4U)
6427 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
6428 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
6429 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
6430 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
6431 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
6432 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
6434 #define TIM_CCMR2_IC4PSC_Pos (10U)
6435 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
6436 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
6437 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
6438 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
6440 #define TIM_CCMR2_IC4F_Pos (12U)
6441 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
6442 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
6443 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
6444 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
6445 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
6446 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
6448 /******************* Bit definition for TIM_CCER register *******************/
6449 #define TIM_CCER_CC1E_Pos (0U)
6450 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
6451 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
6452 #define TIM_CCER_CC1P_Pos (1U)
6453 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
6454 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
6455 #define TIM_CCER_CC1NE_Pos (2U)
6456 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
6457 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
6458 #define TIM_CCER_CC1NP_Pos (3U)
6459 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
6460 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
6461 #define TIM_CCER_CC2E_Pos (4U)
6462 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
6463 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
6464 #define TIM_CCER_CC2P_Pos (5U)
6465 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
6466 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
6467 #define TIM_CCER_CC2NE_Pos (6U)
6468 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
6469 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
6470 #define TIM_CCER_CC2NP_Pos (7U)
6471 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
6472 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
6473 #define TIM_CCER_CC3E_Pos (8U)
6474 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
6475 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
6476 #define TIM_CCER_CC3P_Pos (9U)
6477 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
6478 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
6479 #define TIM_CCER_CC3NE_Pos (10U)
6480 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
6481 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
6482 #define TIM_CCER_CC3NP_Pos (11U)
6483 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
6484 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
6485 #define TIM_CCER_CC4E_Pos (12U)
6486 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
6487 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
6488 #define TIM_CCER_CC4P_Pos (13U)
6489 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
6490 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
6491 #define TIM_CCER_CC4NP_Pos (15U)
6492 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
6493 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
6495 /******************* Bit definition for TIM_CNT register ********************/
6496 #define TIM_CNT_CNT_Pos (0U)
6497 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
6498 #define TIM_CNT_CNT TIM_CNT_CNT_Msk
6500 /******************* Bit definition for TIM_PSC register ********************/
6501 #define TIM_PSC_PSC_Pos (0U)
6502 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
6503 #define TIM_PSC_PSC TIM_PSC_PSC_Msk
6505 /******************* Bit definition for TIM_ARR register ********************/
6506 #define TIM_ARR_ARR_Pos (0U)
6507 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
6508 #define TIM_ARR_ARR TIM_ARR_ARR_Msk
6510 /******************* Bit definition for TIM_RCR register ********************/
6511 #define TIM_RCR_REP_Pos (0U)
6512 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
6513 #define TIM_RCR_REP TIM_RCR_REP_Msk
6515 /******************* Bit definition for TIM_CCR1 register *******************/
6516 #define TIM_CCR1_CCR1_Pos (0U)
6517 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
6518 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
6520 /******************* Bit definition for TIM_CCR2 register *******************/
6521 #define TIM_CCR2_CCR2_Pos (0U)
6522 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
6523 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
6525 /******************* Bit definition for TIM_CCR3 register *******************/
6526 #define TIM_CCR3_CCR3_Pos (0U)
6527 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
6528 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
6530 /******************* Bit definition for TIM_CCR4 register *******************/
6531 #define TIM_CCR4_CCR4_Pos (0U)
6532 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
6533 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
6535 /******************* Bit definition for TIM_BDTR register *******************/
6536 #define TIM_BDTR_DTG_Pos (0U)
6537 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
6538 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
6539 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
6540 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
6541 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
6542 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
6543 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
6544 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
6545 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
6546 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
6548 #define TIM_BDTR_LOCK_Pos (8U)
6549 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
6550 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
6551 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
6552 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
6554 #define TIM_BDTR_OSSI_Pos (10U)
6555 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
6556 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
6557 #define TIM_BDTR_OSSR_Pos (11U)
6558 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
6559 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
6560 #define TIM_BDTR_BKE_Pos (12U)
6561 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
6562 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
6563 #define TIM_BDTR_BKP_Pos (13U)
6564 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
6565 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
6566 #define TIM_BDTR_AOE_Pos (14U)
6567 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
6568 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
6569 #define TIM_BDTR_MOE_Pos (15U)
6570 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
6571 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
6573 /******************* Bit definition for TIM_DCR register ********************/
6574 #define TIM_DCR_DBA_Pos (0U)
6575 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
6576 #define TIM_DCR_DBA TIM_DCR_DBA_Msk
6577 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
6578 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
6579 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
6580 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
6581 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
6583 #define TIM_DCR_DBL_Pos (8U)
6584 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
6585 #define TIM_DCR_DBL TIM_DCR_DBL_Msk
6586 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
6587 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
6588 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
6589 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
6590 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
6592 /******************* Bit definition for TIM_DMAR register *******************/
6593 #define TIM_DMAR_DMAB_Pos (0U)
6594 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
6595 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
6597 /******************* Bit definition for TIM_OR register *********************/
6598 #define TIM_OR_TI1_RMP_Pos (0U)
6599 #define TIM_OR_TI1_RMP_Msk (0x3UL << TIM_OR_TI1_RMP_Pos)
6600 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk
6601 #define TIM_OR_TI1_RMP_0 (0x1UL << TIM_OR_TI1_RMP_Pos)
6602 #define TIM_OR_TI1_RMP_1 (0x2UL << TIM_OR_TI1_RMP_Pos)
6604 #define TIM_OR_TI4_RMP_Pos (6U)
6605 #define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
6606 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
6607 #define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
6608 #define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
6609 #define TIM_OR_ITR1_RMP_Pos (10U)
6610 #define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
6611 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
6612 #define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
6613 #define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
6616 /******************************************************************************/
6617 /* */
6618 /* Universal Synchronous Asynchronous Receiver Transmitter */
6619 /* */
6620 /******************************************************************************/
6621 /******************* Bit definition for USART_SR register *******************/
6622 #define USART_SR_PE_Pos (0U)
6623 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
6624 #define USART_SR_PE USART_SR_PE_Msk
6625 #define USART_SR_FE_Pos (1U)
6626 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
6627 #define USART_SR_FE USART_SR_FE_Msk
6628 #define USART_SR_NE_Pos (2U)
6629 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
6630 #define USART_SR_NE USART_SR_NE_Msk
6631 #define USART_SR_ORE_Pos (3U)
6632 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
6633 #define USART_SR_ORE USART_SR_ORE_Msk
6634 #define USART_SR_IDLE_Pos (4U)
6635 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
6636 #define USART_SR_IDLE USART_SR_IDLE_Msk
6637 #define USART_SR_RXNE_Pos (5U)
6638 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
6639 #define USART_SR_RXNE USART_SR_RXNE_Msk
6640 #define USART_SR_TC_Pos (6U)
6641 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
6642 #define USART_SR_TC USART_SR_TC_Msk
6643 #define USART_SR_TXE_Pos (7U)
6644 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
6645 #define USART_SR_TXE USART_SR_TXE_Msk
6646 #define USART_SR_LBD_Pos (8U)
6647 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
6648 #define USART_SR_LBD USART_SR_LBD_Msk
6649 #define USART_SR_CTS_Pos (9U)
6650 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
6651 #define USART_SR_CTS USART_SR_CTS_Msk
6653 /******************* Bit definition for USART_DR register *******************/
6654 #define USART_DR_DR_Pos (0U)
6655 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
6656 #define USART_DR_DR USART_DR_DR_Msk
6658 /****************** Bit definition for USART_BRR register *******************/
6659 #define USART_BRR_DIV_Fraction_Pos (0U)
6660 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
6661 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
6662 #define USART_BRR_DIV_Mantissa_Pos (4U)
6663 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
6664 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
6666 /****************** Bit definition for USART_CR1 register *******************/
6667 #define USART_CR1_SBK_Pos (0U)
6668 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
6669 #define USART_CR1_SBK USART_CR1_SBK_Msk
6670 #define USART_CR1_RWU_Pos (1U)
6671 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
6672 #define USART_CR1_RWU USART_CR1_RWU_Msk
6673 #define USART_CR1_RE_Pos (2U)
6674 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
6675 #define USART_CR1_RE USART_CR1_RE_Msk
6676 #define USART_CR1_TE_Pos (3U)
6677 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
6678 #define USART_CR1_TE USART_CR1_TE_Msk
6679 #define USART_CR1_IDLEIE_Pos (4U)
6680 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
6681 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
6682 #define USART_CR1_RXNEIE_Pos (5U)
6683 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
6684 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
6685 #define USART_CR1_TCIE_Pos (6U)
6686 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
6687 #define USART_CR1_TCIE USART_CR1_TCIE_Msk
6688 #define USART_CR1_TXEIE_Pos (7U)
6689 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
6690 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
6691 #define USART_CR1_PEIE_Pos (8U)
6692 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
6693 #define USART_CR1_PEIE USART_CR1_PEIE_Msk
6694 #define USART_CR1_PS_Pos (9U)
6695 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
6696 #define USART_CR1_PS USART_CR1_PS_Msk
6697 #define USART_CR1_PCE_Pos (10U)
6698 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
6699 #define USART_CR1_PCE USART_CR1_PCE_Msk
6700 #define USART_CR1_WAKE_Pos (11U)
6701 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
6702 #define USART_CR1_WAKE USART_CR1_WAKE_Msk
6703 #define USART_CR1_M_Pos (12U)
6704 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
6705 #define USART_CR1_M USART_CR1_M_Msk
6706 #define USART_CR1_UE_Pos (13U)
6707 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
6708 #define USART_CR1_UE USART_CR1_UE_Msk
6709 #define USART_CR1_OVER8_Pos (15U)
6710 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
6711 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk
6713 /****************** Bit definition for USART_CR2 register *******************/
6714 #define USART_CR2_ADD_Pos (0U)
6715 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
6716 #define USART_CR2_ADD USART_CR2_ADD_Msk
6717 #define USART_CR2_LBDL_Pos (5U)
6718 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
6719 #define USART_CR2_LBDL USART_CR2_LBDL_Msk
6720 #define USART_CR2_LBDIE_Pos (6U)
6721 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
6722 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
6723 #define USART_CR2_LBCL_Pos (8U)
6724 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
6725 #define USART_CR2_LBCL USART_CR2_LBCL_Msk
6726 #define USART_CR2_CPHA_Pos (9U)
6727 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
6728 #define USART_CR2_CPHA USART_CR2_CPHA_Msk
6729 #define USART_CR2_CPOL_Pos (10U)
6730 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
6731 #define USART_CR2_CPOL USART_CR2_CPOL_Msk
6732 #define USART_CR2_CLKEN_Pos (11U)
6733 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
6734 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
6736 #define USART_CR2_STOP_Pos (12U)
6737 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
6738 #define USART_CR2_STOP USART_CR2_STOP_Msk
6739 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
6740 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
6742 #define USART_CR2_LINEN_Pos (14U)
6743 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
6744 #define USART_CR2_LINEN USART_CR2_LINEN_Msk
6746 /****************** Bit definition for USART_CR3 register *******************/
6747 #define USART_CR3_EIE_Pos (0U)
6748 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
6749 #define USART_CR3_EIE USART_CR3_EIE_Msk
6750 #define USART_CR3_IREN_Pos (1U)
6751 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
6752 #define USART_CR3_IREN USART_CR3_IREN_Msk
6753 #define USART_CR3_IRLP_Pos (2U)
6754 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
6755 #define USART_CR3_IRLP USART_CR3_IRLP_Msk
6756 #define USART_CR3_HDSEL_Pos (3U)
6757 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
6758 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
6759 #define USART_CR3_NACK_Pos (4U)
6760 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
6761 #define USART_CR3_NACK USART_CR3_NACK_Msk
6762 #define USART_CR3_SCEN_Pos (5U)
6763 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
6764 #define USART_CR3_SCEN USART_CR3_SCEN_Msk
6765 #define USART_CR3_DMAR_Pos (6U)
6766 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
6767 #define USART_CR3_DMAR USART_CR3_DMAR_Msk
6768 #define USART_CR3_DMAT_Pos (7U)
6769 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
6770 #define USART_CR3_DMAT USART_CR3_DMAT_Msk
6771 #define USART_CR3_RTSE_Pos (8U)
6772 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
6773 #define USART_CR3_RTSE USART_CR3_RTSE_Msk
6774 #define USART_CR3_CTSE_Pos (9U)
6775 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
6776 #define USART_CR3_CTSE USART_CR3_CTSE_Msk
6777 #define USART_CR3_CTSIE_Pos (10U)
6778 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
6779 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
6780 #define USART_CR3_ONEBIT_Pos (11U)
6781 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
6782 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
6784 /****************** Bit definition for USART_GTPR register ******************/
6785 #define USART_GTPR_PSC_Pos (0U)
6786 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
6787 #define USART_GTPR_PSC USART_GTPR_PSC_Msk
6788 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
6789 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
6790 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
6791 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
6792 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
6793 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
6794 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
6795 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
6797 #define USART_GTPR_GT_Pos (8U)
6798 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
6799 #define USART_GTPR_GT USART_GTPR_GT_Msk
6801 /******************************************************************************/
6802 /* */
6803 /* Window WATCHDOG */
6804 /* */
6805 /******************************************************************************/
6806 /******************* Bit definition for WWDG_CR register ********************/
6807 #define WWDG_CR_T_Pos (0U)
6808 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
6809 #define WWDG_CR_T WWDG_CR_T_Msk
6810 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
6811 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
6812 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
6813 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
6814 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
6815 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
6816 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
6817 /* Legacy defines */
6818 #define WWDG_CR_T0 WWDG_CR_T_0
6819 #define WWDG_CR_T1 WWDG_CR_T_1
6820 #define WWDG_CR_T2 WWDG_CR_T_2
6821 #define WWDG_CR_T3 WWDG_CR_T_3
6822 #define WWDG_CR_T4 WWDG_CR_T_4
6823 #define WWDG_CR_T5 WWDG_CR_T_5
6824 #define WWDG_CR_T6 WWDG_CR_T_6
6825 
6826 #define WWDG_CR_WDGA_Pos (7U)
6827 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
6828 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
6830 /******************* Bit definition for WWDG_CFR register *******************/
6831 #define WWDG_CFR_W_Pos (0U)
6832 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
6833 #define WWDG_CFR_W WWDG_CFR_W_Msk
6834 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
6835 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
6836 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
6837 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
6838 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
6839 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
6840 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
6841 /* Legacy defines */
6842 #define WWDG_CFR_W0 WWDG_CFR_W_0
6843 #define WWDG_CFR_W1 WWDG_CFR_W_1
6844 #define WWDG_CFR_W2 WWDG_CFR_W_2
6845 #define WWDG_CFR_W3 WWDG_CFR_W_3
6846 #define WWDG_CFR_W4 WWDG_CFR_W_4
6847 #define WWDG_CFR_W5 WWDG_CFR_W_5
6848 #define WWDG_CFR_W6 WWDG_CFR_W_6
6849 
6850 #define WWDG_CFR_WDGTB_Pos (7U)
6851 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
6852 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
6853 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
6854 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
6855 /* Legacy defines */
6856 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
6857 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
6858 
6859 #define WWDG_CFR_EWI_Pos (9U)
6860 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
6861 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
6863 /******************* Bit definition for WWDG_SR register ********************/
6864 #define WWDG_SR_EWIF_Pos (0U)
6865 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
6866 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
6869 /******************************************************************************/
6870 /* */
6871 /* DBG */
6872 /* */
6873 /******************************************************************************/
6874 /******************** Bit definition for DBGMCU_IDCODE register *************/
6875 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
6876 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
6877 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
6878 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
6879 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
6880 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
6881 
6882 /******************** Bit definition for DBGMCU_CR register *****************/
6883 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
6884 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
6885 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
6886 #define DBGMCU_CR_DBG_STOP_Pos (1U)
6887 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
6888 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
6889 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
6890 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
6891 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
6892 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
6893 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
6894 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
6895 
6896 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
6897 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
6898 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
6899 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
6900 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
6902 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
6903 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
6904 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
6905 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
6906 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
6907 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
6908 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
6909 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
6910 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
6911 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
6912 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
6913 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
6914 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
6915 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
6916 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
6917 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
6918 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
6919 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
6920 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
6921 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
6922 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
6923 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
6924 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
6925 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
6926 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
6927 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
6928 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
6929 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
6930 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
6931 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
6932 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
6933 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
6934 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
6935 
6936 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
6937 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
6938 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
6939 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
6940 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
6941 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
6942 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
6943 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
6944 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
6945 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
6946 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
6947 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
6948 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
6949 
6950 /******************************************************************************/
6951 /* */
6952 /* USB_OTG */
6953 /* */
6954 /******************************************************************************/
6955 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
6956 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
6957 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
6958 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
6959 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
6960 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
6961 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
6962 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
6963 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
6964 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
6965 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
6966 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
6967 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
6968 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
6969 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
6970 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
6971 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
6972 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
6973 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
6974 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
6975 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
6976 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
6977 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
6978 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
6979 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
6980 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
6981 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
6982 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
6983 #define USB_OTG_GOTGCTL_BSVLD_Pos (19U)
6984 #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)
6985 #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk
6987 /******************** Bit definition forUSB_OTG_HCFG register ********************/
6988 
6989 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
6990 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
6991 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
6992 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
6993 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
6994 #define USB_OTG_HCFG_FSLSS_Pos (2U)
6995 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
6996 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
6998 /******************** Bit definition for USB_OTG_DCFG register ********************/
6999 
7000 #define USB_OTG_DCFG_DSPD_Pos (0U)
7001 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
7002 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
7003 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
7004 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
7005 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
7006 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
7007 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
7009 #define USB_OTG_DCFG_DAD_Pos (4U)
7010 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
7011 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
7012 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
7013 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
7014 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
7015 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
7016 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
7017 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
7018 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
7020 #define USB_OTG_DCFG_PFIVL_Pos (11U)
7021 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
7022 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
7023 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
7024 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
7026 #define USB_OTG_DCFG_XCVRDLY_Pos (14U)
7027 #define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
7028 #define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
7030 #define USB_OTG_DCFG_ERRATIM_Pos (15U)
7031 #define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
7032 #define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
7034 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
7035 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
7036 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
7037 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
7038 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
7040 /******************** Bit definition for USB_OTG_PCGCR register ********************/
7041 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
7042 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
7043 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
7044 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
7045 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
7046 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
7047 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
7048 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
7049 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
7051 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
7052 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
7053 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
7054 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
7055 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
7056 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
7057 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
7058 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
7059 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
7060 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
7061 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
7062 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
7063 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
7064 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
7065 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
7066 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
7067 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
7068 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
7069 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
7071 /******************** Bit definition for USB_OTG_DCTL register ********************/
7072 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
7073 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
7074 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
7075 #define USB_OTG_DCTL_SDIS_Pos (1U)
7076 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
7077 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
7078 #define USB_OTG_DCTL_GINSTS_Pos (2U)
7079 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
7080 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
7081 #define USB_OTG_DCTL_GONSTS_Pos (3U)
7082 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
7083 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
7085 #define USB_OTG_DCTL_TCTL_Pos (4U)
7086 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
7087 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
7088 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
7089 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
7090 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
7091 #define USB_OTG_DCTL_SGINAK_Pos (7U)
7092 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
7093 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
7094 #define USB_OTG_DCTL_CGINAK_Pos (8U)
7095 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
7096 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
7097 #define USB_OTG_DCTL_SGONAK_Pos (9U)
7098 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
7099 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
7100 #define USB_OTG_DCTL_CGONAK_Pos (10U)
7101 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
7102 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
7103 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
7104 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
7105 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
7107 /******************** Bit definition for USB_OTG_HFIR register ********************/
7108 #define USB_OTG_HFIR_FRIVL_Pos (0U)
7109 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
7110 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
7112 /******************** Bit definition for USB_OTG_HFNUM register ********************/
7113 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
7114 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
7115 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
7116 #define USB_OTG_HFNUM_FTREM_Pos (16U)
7117 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
7118 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
7120 /******************** Bit definition for USB_OTG_DSTS register ********************/
7121 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
7122 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
7123 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
7125 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
7126 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
7127 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
7128 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
7129 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
7130 #define USB_OTG_DSTS_EERR_Pos (3U)
7131 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
7132 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
7133 #define USB_OTG_DSTS_FNSOF_Pos (8U)
7134 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
7135 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
7137 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
7138 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
7139 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
7140 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
7141 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
7142 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
7143 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
7144 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
7145 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
7146 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
7147 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
7148 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
7149 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
7150 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
7151 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
7152 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
7153 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
7154 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
7155 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
7156 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
7157 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
7159 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
7160 
7161 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
7162 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
7163 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
7164 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
7165 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
7166 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
7167 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
7168 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
7169 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
7170 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
7171 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
7172 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
7173 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
7174 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
7175 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
7176 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
7177 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
7178 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
7179 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
7180 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
7181 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
7182 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
7183 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
7184 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
7185 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
7186 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
7187 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
7188 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
7189 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
7190 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
7191 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
7192 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
7193 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
7194 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
7195 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
7196 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
7197 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
7198 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
7199 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
7200 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
7201 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
7202 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
7203 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
7204 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
7205 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
7206 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
7207 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
7208 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
7209 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
7210 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
7211 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
7212 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
7213 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
7214 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
7215 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
7216 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
7217 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
7218 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
7219 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
7220 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
7221 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
7223 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
7224 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
7225 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
7226 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
7227 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
7228 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
7229 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
7230 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
7231 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
7232 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
7233 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
7234 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
7235 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
7236 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
7237 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
7238 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
7241 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
7242 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
7243 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
7244 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
7245 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
7246 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
7247 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
7248 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
7249 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
7250 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
7251 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
7252 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
7253 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
7254 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
7256 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
7257 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
7258 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
7259 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
7260 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
7261 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
7262 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
7263 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
7264 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
7265 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
7266 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
7267 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
7268 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
7269 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
7270 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
7271 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
7272 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
7273 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
7274 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
7275 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
7276 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
7277 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
7278 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
7279 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
7280 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
7282 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
7283 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
7284 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
7285 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
7286 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
7287 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
7288 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
7289 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
7290 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
7291 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
7292 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
7293 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
7294 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
7295 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
7296 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
7298 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
7299 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
7300 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
7301 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
7302 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
7303 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
7304 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
7305 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
7306 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
7307 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
7308 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
7310 /******************** Bit definition for USB_OTG_HAINT register ********************/
7311 #define USB_OTG_HAINT_HAINT_Pos (0U)
7312 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
7313 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
7315 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
7316 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
7317 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
7318 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
7319 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
7320 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
7321 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
7322 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
7323 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
7324 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
7325 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
7326 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
7327 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
7328 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
7329 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
7330 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
7331 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
7332 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
7333 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
7334 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
7335 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
7336 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
7337 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
7338 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
7339 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
7340 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
7341 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
7342 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
7343 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
7344 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
7345 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
7346 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
7347 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
7348 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
7349 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
7350 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
7351 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
7352 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
7353 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
7354 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
7355 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
7356 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
7357 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
7358 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
7359 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
7360 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
7361 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
7362 #define USB_OTG_GINTSTS_SOF_Pos (3U)
7363 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
7364 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
7365 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
7366 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
7367 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
7368 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
7369 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
7370 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
7371 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
7372 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
7373 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
7374 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
7375 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
7376 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
7377 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
7378 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
7379 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
7380 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
7381 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
7382 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
7383 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
7384 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
7385 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
7386 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
7387 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
7388 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
7389 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
7390 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
7391 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
7392 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
7393 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
7394 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
7395 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
7396 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
7397 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
7398 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
7399 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
7400 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
7401 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
7402 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
7403 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
7404 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
7405 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
7406 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
7407 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
7408 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
7409 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
7410 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
7411 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
7412 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
7413 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
7414 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
7415 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
7416 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
7417 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
7418 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
7419 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
7420 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
7421 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
7422 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
7423 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
7424 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
7425 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
7426 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
7427 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
7428 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
7429 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
7430 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
7432 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
7433 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
7434 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
7435 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
7436 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
7437 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
7438 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
7439 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
7440 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
7441 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
7442 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
7443 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
7444 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
7445 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
7446 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
7447 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
7448 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
7449 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
7450 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
7451 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
7452 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
7453 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
7454 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
7455 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
7456 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
7457 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
7458 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
7459 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
7460 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
7461 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
7462 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
7463 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
7464 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
7465 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
7466 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
7467 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
7468 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
7469 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
7470 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
7471 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
7472 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
7473 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
7474 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
7475 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
7476 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
7477 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
7478 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
7479 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
7480 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
7481 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
7482 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
7483 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
7484 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
7485 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
7486 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
7487 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
7488 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
7489 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
7490 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
7491 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
7492 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
7493 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
7494 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
7495 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
7496 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
7497 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
7498 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
7499 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
7500 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
7501 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
7502 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
7503 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
7504 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
7505 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
7506 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
7507 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
7508 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
7509 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
7510 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
7512 /******************** Bit definition for USB_OTG_DAINT register ********************/
7513 #define USB_OTG_DAINT_IEPINT_Pos (0U)
7514 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
7515 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
7516 #define USB_OTG_DAINT_OEPINT_Pos (16U)
7517 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
7518 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
7520 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
7521 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
7522 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
7523 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
7525 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
7526 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
7527 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
7528 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
7529 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
7530 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
7531 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
7532 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
7533 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
7534 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
7535 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
7536 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
7537 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
7539 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
7540 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
7541 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
7542 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
7543 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
7544 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
7545 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
7547 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
7548 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
7549 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
7550 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
7552 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
7553 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
7554 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
7555 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
7557 /******************** Bit definition for OTG register ********************/
7558 #define USB_OTG_NPTXFSA_Pos (0U)
7559 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
7560 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
7561 #define USB_OTG_NPTXFD_Pos (16U)
7562 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
7563 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
7564 #define USB_OTG_TX0FSA_Pos (0U)
7565 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
7566 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
7567 #define USB_OTG_TX0FD_Pos (16U)
7568 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
7569 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
7571 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
7572 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
7573 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
7574 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
7576 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
7577 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
7578 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
7579 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
7581 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
7582 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
7583 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
7584 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
7585 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
7586 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
7587 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
7588 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
7589 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
7590 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
7591 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
7593 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
7594 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
7595 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
7596 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
7597 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
7598 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
7599 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
7600 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
7601 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
7602 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
7604 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
7605 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
7606 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
7607 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
7608 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
7609 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
7610 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
7612 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
7613 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7614 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
7615 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7616 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7617 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7618 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7619 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7620 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7621 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7622 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7623 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
7624 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
7625 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
7626 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
7628 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
7629 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7630 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
7631 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7632 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7633 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7634 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7635 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7636 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7637 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7638 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7639 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
7640 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
7641 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
7642 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
7644 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
7645 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
7646 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
7647 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
7649 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
7650 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
7651 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
7652 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
7653 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
7654 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
7655 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
7657 /******************** Bit definition for USB_OTG_GCCFG register ********************/
7658 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
7659 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
7660 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
7661 #define USB_OTG_GCCFG_I2CPADEN_Pos (17U)
7662 #define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos)
7663 #define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk
7664 #define USB_OTG_GCCFG_VBUSASEN_Pos (18U)
7665 #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)
7666 #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk
7667 #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U)
7668 #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)
7669 #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk
7670 #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U)
7671 #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)
7672 #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk
7673 #define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U)
7674 #define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos)
7675 #define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk
7677 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
7678 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
7679 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
7680 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
7681 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
7682 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
7683 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
7685 /******************** Bit definition for USB_OTG_CID register ********************/
7686 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
7687 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
7688 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
7690 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
7691 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
7692 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
7693 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
7694 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
7695 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
7696 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
7697 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
7698 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
7699 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
7700 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
7701 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
7702 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
7703 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
7704 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
7705 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
7706 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
7707 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
7708 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
7709 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
7710 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
7711 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
7712 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
7713 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
7714 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
7715 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
7716 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
7717 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
7719 /******************** Bit definition for USB_OTG_HPRT register ********************/
7720 #define USB_OTG_HPRT_PCSTS_Pos (0U)
7721 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
7722 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
7723 #define USB_OTG_HPRT_PCDET_Pos (1U)
7724 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
7725 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
7726 #define USB_OTG_HPRT_PENA_Pos (2U)
7727 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
7728 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
7729 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
7730 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
7731 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
7732 #define USB_OTG_HPRT_POCA_Pos (4U)
7733 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
7734 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
7735 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
7736 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
7737 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
7738 #define USB_OTG_HPRT_PRES_Pos (6U)
7739 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
7740 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
7741 #define USB_OTG_HPRT_PSUSP_Pos (7U)
7742 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
7743 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
7744 #define USB_OTG_HPRT_PRST_Pos (8U)
7745 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
7746 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
7748 #define USB_OTG_HPRT_PLSTS_Pos (10U)
7749 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
7750 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
7751 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
7752 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
7753 #define USB_OTG_HPRT_PPWR_Pos (12U)
7754 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
7755 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
7757 #define USB_OTG_HPRT_PTCTL_Pos (13U)
7758 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
7759 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
7760 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
7761 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
7762 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
7763 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
7765 #define USB_OTG_HPRT_PSPD_Pos (17U)
7766 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
7767 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
7768 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
7769 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
7771 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
7772 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
7773 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
7774 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
7775 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
7776 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
7777 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
7778 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
7779 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
7780 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
7781 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
7782 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
7783 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
7784 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
7785 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
7786 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
7787 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
7788 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
7789 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
7790 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
7791 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
7792 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
7793 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
7794 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
7795 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
7796 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
7797 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
7798 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
7799 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
7800 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
7801 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
7802 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
7803 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
7804 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
7806 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
7807 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
7808 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
7809 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
7810 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
7811 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
7812 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
7814 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
7815 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
7816 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
7817 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
7818 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
7819 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
7820 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
7821 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
7822 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
7823 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
7824 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
7825 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
7826 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
7828 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
7829 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
7830 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
7831 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
7832 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
7833 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
7834 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
7835 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
7837 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
7838 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
7839 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
7840 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
7841 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
7842 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
7843 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
7844 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
7845 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
7846 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
7847 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
7848 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
7849 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
7850 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
7851 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
7852 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
7853 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
7854 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
7855 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
7856 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
7857 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
7858 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
7859 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
7860 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
7861 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
7863 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
7864 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
7865 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
7866 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
7868 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
7869 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
7870 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
7871 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
7872 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
7873 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
7874 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
7875 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
7876 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
7877 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
7878 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
7879 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
7880 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
7882 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
7883 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
7884 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
7885 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
7886 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
7888 #define USB_OTG_HCCHAR_MC_Pos (20U)
7889 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
7890 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
7891 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
7892 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
7894 #define USB_OTG_HCCHAR_DAD_Pos (22U)
7895 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
7896 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
7897 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
7898 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
7899 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
7900 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
7901 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
7902 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
7903 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
7904 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
7905 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
7906 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
7907 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
7908 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
7909 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
7910 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
7911 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
7912 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
7914 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
7915 
7916 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
7917 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
7918 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
7919 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
7920 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
7921 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
7922 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
7923 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
7924 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
7925 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
7927 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
7928 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
7929 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
7930 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
7931 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
7932 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
7933 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
7934 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
7935 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
7936 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
7938 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
7939 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
7940 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
7941 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
7942 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
7943 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
7944 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
7945 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
7946 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
7947 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
7948 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
7950 /******************** Bit definition for USB_OTG_HCINT register ********************/
7951 #define USB_OTG_HCINT_XFRC_Pos (0U)
7952 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
7953 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
7954 #define USB_OTG_HCINT_CHH_Pos (1U)
7955 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
7956 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
7957 #define USB_OTG_HCINT_AHBERR_Pos (2U)
7958 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
7959 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
7960 #define USB_OTG_HCINT_STALL_Pos (3U)
7961 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
7962 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
7963 #define USB_OTG_HCINT_NAK_Pos (4U)
7964 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
7965 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
7966 #define USB_OTG_HCINT_ACK_Pos (5U)
7967 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
7968 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
7969 #define USB_OTG_HCINT_NYET_Pos (6U)
7970 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
7971 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
7972 #define USB_OTG_HCINT_TXERR_Pos (7U)
7973 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
7974 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
7975 #define USB_OTG_HCINT_BBERR_Pos (8U)
7976 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
7977 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
7978 #define USB_OTG_HCINT_FRMOR_Pos (9U)
7979 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
7980 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
7981 #define USB_OTG_HCINT_DTERR_Pos (10U)
7982 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
7983 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
7985 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
7986 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
7987 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
7988 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
7989 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
7990 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
7991 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
7992 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
7993 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
7994 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
7995 #define USB_OTG_DIEPINT_TOC_Pos (3U)
7996 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
7997 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
7998 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
7999 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
8000 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
8001 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
8002 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
8003 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
8004 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
8005 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
8006 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
8007 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
8008 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
8009 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
8010 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
8011 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
8012 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
8013 #define USB_OTG_DIEPINT_BNA_Pos (9U)
8014 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
8015 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
8016 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
8017 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
8018 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
8019 #define USB_OTG_DIEPINT_BERR_Pos (12U)
8020 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
8021 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
8022 #define USB_OTG_DIEPINT_NAK_Pos (13U)
8023 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
8024 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
8026 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
8027 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
8028 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
8029 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
8030 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
8031 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
8032 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
8033 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
8034 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
8035 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
8036 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
8037 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
8038 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
8039 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
8040 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
8041 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
8042 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
8043 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
8044 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
8045 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
8046 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
8047 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
8048 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
8049 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
8050 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
8051 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
8052 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
8053 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
8054 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
8055 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
8056 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
8057 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
8058 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
8059 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
8061 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
8062 
8063 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
8064 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
8065 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
8066 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
8067 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
8068 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
8069 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
8070 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
8071 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
8072 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
8073 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
8074 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
8075 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
8076 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
8077 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
8078 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
8079 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
8080 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
8081 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
8082 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
8083 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
8084 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
8085 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
8086 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
8088 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
8089 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
8090 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
8091 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
8093 /******************** Bit definition for USB_OTG_HCDMA register ********************/
8094 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
8095 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
8096 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
8098 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
8099 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
8100 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
8101 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
8103 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
8104 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
8105 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
8106 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
8107 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
8108 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
8109 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
8111 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
8112 
8113 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
8114 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
8115 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
8116 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
8117 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
8118 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
8119 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
8120 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
8121 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
8122 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
8123 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
8124 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
8125 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
8126 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
8127 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
8128 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
8129 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
8130 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
8131 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
8132 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
8133 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
8134 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
8135 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
8136 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
8137 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
8138 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
8139 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
8140 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
8141 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
8142 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
8143 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
8144 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
8145 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
8146 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
8147 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
8148 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
8149 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
8150 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
8152 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
8153 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
8154 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
8155 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
8156 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
8157 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
8158 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
8159 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
8160 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
8161 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
8162 #define USB_OTG_DOEPINT_STUP_Pos (3U)
8163 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
8164 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
8165 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
8166 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
8167 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
8168 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
8169 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
8170 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
8171 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
8172 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
8173 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
8174 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
8175 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
8176 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
8177 #define USB_OTG_DOEPINT_NAK_Pos (13U)
8178 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
8179 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
8180 #define USB_OTG_DOEPINT_NYET_Pos (14U)
8181 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
8182 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
8183 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
8184 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
8185 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
8186 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
8187 
8188 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
8189 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
8190 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
8191 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
8192 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
8193 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
8195 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
8196 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
8197 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
8198 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
8199 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
8201 /******************** Bit definition for PCGCCTL register ********************/
8202 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
8203 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
8204 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
8205 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
8206 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
8207 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
8208 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
8209 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
8210 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
8212 /* Legacy define */
8213 /******************** Bit definition for OTG register ********************/
8214 #define USB_OTG_CHNUM_Pos (0U)
8215 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
8216 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
8217 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
8218 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
8219 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
8220 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
8221 #define USB_OTG_BCNT_Pos (4U)
8222 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
8223 #define USB_OTG_BCNT USB_OTG_BCNT_Msk
8225 #define USB_OTG_DPID_Pos (15U)
8226 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
8227 #define USB_OTG_DPID USB_OTG_DPID_Msk
8228 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
8229 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
8231 #define USB_OTG_PKTSTS_Pos (17U)
8232 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
8233 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
8234 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
8235 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
8236 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
8237 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
8239 #define USB_OTG_EPNUM_Pos (0U)
8240 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
8241 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
8242 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
8243 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
8244 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
8245 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
8247 #define USB_OTG_FRMNUM_Pos (21U)
8248 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
8249 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
8250 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
8251 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
8252 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
8253 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
8266 /******************************* ADC Instances ********************************/
8267 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
8268 
8269 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
8270 /******************************* CRC Instances ********************************/
8271 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
8272 
8273 
8274 /******************************** DMA Instances *******************************/
8275 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
8276  ((INSTANCE) == DMA1_Stream1) || \
8277  ((INSTANCE) == DMA1_Stream2) || \
8278  ((INSTANCE) == DMA1_Stream3) || \
8279  ((INSTANCE) == DMA1_Stream4) || \
8280  ((INSTANCE) == DMA1_Stream5) || \
8281  ((INSTANCE) == DMA1_Stream6) || \
8282  ((INSTANCE) == DMA1_Stream7) || \
8283  ((INSTANCE) == DMA2_Stream0) || \
8284  ((INSTANCE) == DMA2_Stream1) || \
8285  ((INSTANCE) == DMA2_Stream2) || \
8286  ((INSTANCE) == DMA2_Stream3) || \
8287  ((INSTANCE) == DMA2_Stream4) || \
8288  ((INSTANCE) == DMA2_Stream5) || \
8289  ((INSTANCE) == DMA2_Stream6) || \
8290  ((INSTANCE) == DMA2_Stream7))
8291 
8292 /******************************* GPIO Instances *******************************/
8293 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
8294  ((INSTANCE) == GPIOB) || \
8295  ((INSTANCE) == GPIOC) || \
8296  ((INSTANCE) == GPIOD) || \
8297  ((INSTANCE) == GPIOE) || \
8298  ((INSTANCE) == GPIOH))
8299 
8300 /******************************** I2C Instances *******************************/
8301 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
8302  ((INSTANCE) == I2C2) || \
8303  ((INSTANCE) == I2C3))
8304 
8305 /******************************* SMBUS Instances ******************************/
8306 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
8307 
8308 /******************************** I2S Instances *******************************/
8309 
8310 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8311  ((INSTANCE) == SPI2) || \
8312  ((INSTANCE) == SPI3) || \
8313  ((INSTANCE) == SPI4) || \
8314  ((INSTANCE) == SPI5))
8315 
8316 /*************************** I2S Extended Instances ***************************/
8317 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
8318  ((INSTANCE) == I2S3ext))
8319 /* Legacy Defines */
8320 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
8321 
8322 
8323 /****************************** RTC Instances *********************************/
8324 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
8325 
8326 
8327 /******************************** SPI Instances *******************************/
8328 
8329 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8330  ((INSTANCE) == SPI2) || \
8331  ((INSTANCE) == SPI3) || \
8332  ((INSTANCE) == SPI4) || \
8333  ((INSTANCE) == SPI5))
8334 
8335 
8336 /****************** TIM Instances : All supported instances *******************/
8337 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8338  ((INSTANCE) == TIM2) || \
8339  ((INSTANCE) == TIM3) || \
8340  ((INSTANCE) == TIM4) || \
8341  ((INSTANCE) == TIM5) || \
8342  ((INSTANCE) == TIM9) || \
8343  ((INSTANCE) == TIM10) || \
8344  ((INSTANCE) == TIM11))
8345 
8346 /************* TIM Instances : at least 1 capture/compare channel *************/
8347 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8348  ((INSTANCE) == TIM2) || \
8349  ((INSTANCE) == TIM3) || \
8350  ((INSTANCE) == TIM4) || \
8351  ((INSTANCE) == TIM5) || \
8352  ((INSTANCE) == TIM9) || \
8353  ((INSTANCE) == TIM10) || \
8354  ((INSTANCE) == TIM11))
8355 
8356 /************ TIM Instances : at least 2 capture/compare channels *************/
8357 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8358  ((INSTANCE) == TIM2) || \
8359  ((INSTANCE) == TIM3) || \
8360  ((INSTANCE) == TIM4) || \
8361  ((INSTANCE) == TIM5) || \
8362  ((INSTANCE) == TIM9))
8363 
8364 /************ TIM Instances : at least 3 capture/compare channels *************/
8365 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8366  ((INSTANCE) == TIM2) || \
8367  ((INSTANCE) == TIM3) || \
8368  ((INSTANCE) == TIM4) || \
8369  ((INSTANCE) == TIM5))
8370 
8371 /************ TIM Instances : at least 4 capture/compare channels *************/
8372 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8373  ((INSTANCE) == TIM2) || \
8374  ((INSTANCE) == TIM3) || \
8375  ((INSTANCE) == TIM4) || \
8376  ((INSTANCE) == TIM5))
8377 
8378 /******************** TIM Instances : Advanced-control timers *****************/
8379 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
8380 
8381 /******************* TIM Instances : Timer input XOR function *****************/
8382 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8383  ((INSTANCE) == TIM2) || \
8384  ((INSTANCE) == TIM3) || \
8385  ((INSTANCE) == TIM4) || \
8386  ((INSTANCE) == TIM5))
8387 
8388 /****************** TIM Instances : DMA requests generation (UDE) *************/
8389 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8390  ((INSTANCE) == TIM2) || \
8391  ((INSTANCE) == TIM3) || \
8392  ((INSTANCE) == TIM4) || \
8393  ((INSTANCE) == TIM5))
8394 
8395 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
8396 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8397  ((INSTANCE) == TIM2) || \
8398  ((INSTANCE) == TIM3) || \
8399  ((INSTANCE) == TIM4) || \
8400  ((INSTANCE) == TIM5))
8401 
8402 /************ TIM Instances : DMA requests generation (COMDE) *****************/
8403 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8404  ((INSTANCE) == TIM2) || \
8405  ((INSTANCE) == TIM3) || \
8406  ((INSTANCE) == TIM4) || \
8407  ((INSTANCE) == TIM5))
8408 
8409 /******************** TIM Instances : DMA burst feature ***********************/
8410 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8411  ((INSTANCE) == TIM2) || \
8412  ((INSTANCE) == TIM3) || \
8413  ((INSTANCE) == TIM4) || \
8414  ((INSTANCE) == TIM5))
8415 
8416 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
8417 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8418  ((INSTANCE) == TIM2) || \
8419  ((INSTANCE) == TIM3) || \
8420  ((INSTANCE) == TIM4) || \
8421  ((INSTANCE) == TIM5))
8422 
8423 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
8424 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8425  ((INSTANCE) == TIM2) || \
8426  ((INSTANCE) == TIM3) || \
8427  ((INSTANCE) == TIM4) || \
8428  ((INSTANCE) == TIM5) || \
8429  ((INSTANCE) == TIM9))
8430 /********************** TIM Instances : 32 bit Counter ************************/
8431 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
8432  ((INSTANCE) == TIM5))
8433 
8434 /***************** TIM Instances : external trigger input availabe ************/
8435 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8436  ((INSTANCE) == TIM2) || \
8437  ((INSTANCE) == TIM3) || \
8438  ((INSTANCE) == TIM4) || \
8439  ((INSTANCE) == TIM5))
8440 
8441 /****************** TIM Instances : remapping capability **********************/
8442 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
8443  ((INSTANCE) == TIM5) || \
8444  ((INSTANCE) == TIM11))
8445 
8446 /******************* TIM Instances : output(s) available **********************/
8447 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8448  ((((INSTANCE) == TIM1) && \
8449  (((CHANNEL) == TIM_CHANNEL_1) || \
8450  ((CHANNEL) == TIM_CHANNEL_2) || \
8451  ((CHANNEL) == TIM_CHANNEL_3) || \
8452  ((CHANNEL) == TIM_CHANNEL_4))) \
8453  || \
8454  (((INSTANCE) == TIM2) && \
8455  (((CHANNEL) == TIM_CHANNEL_1) || \
8456  ((CHANNEL) == TIM_CHANNEL_2) || \
8457  ((CHANNEL) == TIM_CHANNEL_3) || \
8458  ((CHANNEL) == TIM_CHANNEL_4))) \
8459  || \
8460  (((INSTANCE) == TIM3) && \
8461  (((CHANNEL) == TIM_CHANNEL_1) || \
8462  ((CHANNEL) == TIM_CHANNEL_2) || \
8463  ((CHANNEL) == TIM_CHANNEL_3) || \
8464  ((CHANNEL) == TIM_CHANNEL_4))) \
8465  || \
8466  (((INSTANCE) == TIM4) && \
8467  (((CHANNEL) == TIM_CHANNEL_1) || \
8468  ((CHANNEL) == TIM_CHANNEL_2) || \
8469  ((CHANNEL) == TIM_CHANNEL_3) || \
8470  ((CHANNEL) == TIM_CHANNEL_4))) \
8471  || \
8472  (((INSTANCE) == TIM5) && \
8473  (((CHANNEL) == TIM_CHANNEL_1) || \
8474  ((CHANNEL) == TIM_CHANNEL_2) || \
8475  ((CHANNEL) == TIM_CHANNEL_3) || \
8476  ((CHANNEL) == TIM_CHANNEL_4))) \
8477  || \
8478  (((INSTANCE) == TIM9) && \
8479  (((CHANNEL) == TIM_CHANNEL_1) || \
8480  ((CHANNEL) == TIM_CHANNEL_2))) \
8481  || \
8482  (((INSTANCE) == TIM10) && \
8483  (((CHANNEL) == TIM_CHANNEL_1))) \
8484  || \
8485  (((INSTANCE) == TIM11) && \
8486  (((CHANNEL) == TIM_CHANNEL_1))))
8487 
8488 /************ TIM Instances : complementary output(s) available ***************/
8489 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
8490  ((((INSTANCE) == TIM1) && \
8491  (((CHANNEL) == TIM_CHANNEL_1) || \
8492  ((CHANNEL) == TIM_CHANNEL_2) || \
8493  ((CHANNEL) == TIM_CHANNEL_3))))
8494 
8495 /****************** TIM Instances : supporting counting mode selection ********/
8496 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8497  ((INSTANCE) == TIM2) || \
8498  ((INSTANCE) == TIM3) || \
8499  ((INSTANCE) == TIM4) || \
8500  ((INSTANCE) == TIM5))
8501 
8502 /****************** TIM Instances : supporting clock division *****************/
8503 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8504  ((INSTANCE) == TIM2) || \
8505  ((INSTANCE) == TIM3) || \
8506  ((INSTANCE) == TIM4) || \
8507  ((INSTANCE) == TIM5) || \
8508  ((INSTANCE) == TIM9) || \
8509  ((INSTANCE) == TIM10) || \
8510  ((INSTANCE) == TIM11))
8511 
8512 /****************** TIM Instances : supporting commutation event generation ***/
8513 
8514 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
8515 
8516 /****************** TIM Instances : supporting OCxREF clear *******************/
8517 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8518  ((INSTANCE) == TIM2) || \
8519  ((INSTANCE) == TIM3) || \
8520  ((INSTANCE) == TIM4) || \
8521  ((INSTANCE) == TIM5))
8522 
8523 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
8524 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8525  ((INSTANCE) == TIM2) || \
8526  ((INSTANCE) == TIM3) || \
8527  ((INSTANCE) == TIM4) || \
8528  ((INSTANCE) == TIM5) || \
8529  ((INSTANCE) == TIM9))
8530 
8531 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
8532 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
8533  ((INSTANCE) == TIM2) || \
8534  ((INSTANCE) == TIM3) || \
8535  ((INSTANCE) == TIM4) || \
8536  ((INSTANCE) == TIM5))
8537 
8538 /****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
8539 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8540  ((INSTANCE) == TIM2) || \
8541  ((INSTANCE) == TIM3) || \
8542  ((INSTANCE) == TIM4) || \
8543  ((INSTANCE) == TIM5) || \
8544  ((INSTANCE) == TIM9))
8545 
8546 /********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
8547 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8548  ((INSTANCE) == TIM2) || \
8549  ((INSTANCE) == TIM3) || \
8550  ((INSTANCE) == TIM4) || \
8551  ((INSTANCE) == TIM5) || \
8552  ((INSTANCE) == TIM9))
8553 
8554 /****************** TIM Instances : supporting repetition counter *************/
8555 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
8556 
8557 /****************** TIM Instances : supporting encoder interface **************/
8558 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8559  ((INSTANCE) == TIM2) || \
8560  ((INSTANCE) == TIM3) || \
8561  ((INSTANCE) == TIM4) || \
8562  ((INSTANCE) == TIM5) || \
8563  ((INSTANCE) == TIM9))
8564 /****************** TIM Instances : supporting Hall sensor interface **********/
8565 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
8566  ((INSTANCE) == TIM2) || \
8567  ((INSTANCE) == TIM3) || \
8568  ((INSTANCE) == TIM4) || \
8569  ((INSTANCE) == TIM5))
8570 /****************** TIM Instances : supporting the break function *************/
8571 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1))
8572 
8573 /******************** USART Instances : Synchronous mode **********************/
8574 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8575  ((INSTANCE) == USART2) || \
8576  ((INSTANCE) == USART6))
8577 
8578 /******************** UART Instances : Half-Duplex mode **********************/
8579 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8580  ((INSTANCE) == USART2) || \
8581  ((INSTANCE) == USART6))
8582 
8583 /* Legacy defines */
8584 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
8585 
8586 /****************** UART Instances : Hardware Flow control ********************/
8587 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8588  ((INSTANCE) == USART2) || \
8589  ((INSTANCE) == USART6))
8590 /******************** UART Instances : LIN mode **********************/
8591 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
8592 
8593 /********************* UART Instances : Smart card mode ***********************/
8594 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8595  ((INSTANCE) == USART2) || \
8596  ((INSTANCE) == USART6))
8597 
8598 /*********************** UART Instances : IRDA mode ***************************/
8599 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8600  ((INSTANCE) == USART2) || \
8601  ((INSTANCE) == USART6))
8602 
8603 /*********************** PCD Instances ****************************************/
8604 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
8605 
8606 /*********************** HCD Instances ****************************************/
8607 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))
8608 
8609 /****************************** SDIO Instances ********************************/
8610 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
8611 
8612 /****************************** IWDG Instances ********************************/
8613 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
8614 
8615 /****************************** WWDG Instances ********************************/
8616 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
8617 
8618 /****************************** USB Exported Constants ************************/
8619 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 8U
8620 #define USB_OTG_FS_MAX_IN_ENDPOINTS 4U /* Including EP0 */
8621 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 4U /* Including EP0 */
8622 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
8623 
8624 /*
8625  * @brief Specific devices reset values definitions
8626  */
8627 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
8628 #define RCC_PLLI2SCFGR_RST_VALUE 0x20003010U
8629 
8630 #define RCC_MAX_FREQUENCY 100000000U
8631 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY
8632 #define RCC_MAX_FREQUENCY_SCALE2 84000000U
8633 #define RCC_MAX_FREQUENCY_SCALE3 64000000U
8634 #define RCC_PLLVCO_OUTPUT_MIN 100000000U
8635 #define RCC_PLLVCO_INPUT_MIN 950000U
8636 #define RCC_PLLVCO_INPUT_MAX 2100000U
8637 #define RCC_PLLVCO_OUTPUT_MAX 432000000U
8639 #define RCC_PLLN_MIN_VALUE 50U
8640 #define RCC_PLLN_MAX_VALUE 432U
8641 
8642 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U
8643 #define FLASH_SCALE1_LATENCY2_FREQ 64000000U
8644 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U
8646 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U
8647 #define FLASH_SCALE2_LATENCY2_FREQ 64000000U
8649 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U
8650 #define FLASH_SCALE3_LATENCY2_FREQ 64000000U
8665 #ifdef __cplusplus
8666 }
8667 #endif /* __cplusplus */
8668 
8669 #endif /* __STM32F411xE_H */
8670 
8671 
8672 
8673 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32f411xe.h:80
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f407xx.h:711
__IO
#define __IO
Definition: imxrt1050/imxrt1050-evkb/CMSIS/core_cm7.h:237
SDIO_IRQn
@ SDIO_IRQn
Definition: stm32f411xe.h:117
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32f411xe.h:121
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f407xx.h:758
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f407xx.h:346
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32f411xe.h:82
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32f411xe.h:125
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32f411xe.h:91
DMA_TypeDef
Definition: stm32f407xx.h:356
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32f411xe.h:85
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32f411xe.h:131
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32f411xe.h:106
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32f411xe.h:133
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32f411xe.h:74
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32f411xe.h:127
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f407xx.h:557
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32f411xe.h:103
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f407xx.h:315
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f407xx.h:875
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32f411xe.h:86
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32f411xe.h:116
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f407xx.h:846
I2C_TypeDef::FLTR
__IO uint32_t FLTR
Definition: stm32f411xe.h:307
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32f411xe.h:87
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32f411xe.h:97
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32f411xe.h:72
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32f411xe.h:130
TIM_TypeDef
TIM.
Definition: stm32f407xx.h:729
SDIO_TypeDef
SD host Interface.
Definition: stm32f407xx.h:683
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f407xx.h:574
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f407xx.h:794
USART6_IRQn
@ USART6_IRQn
Definition: stm32f411xe.h:129
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f407xx.h:861
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32f411xe.h:109
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32f411xe.h:124
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32f411xe.h:101
CRC_TypeDef
CRC calculation unit.
Definition: stm32f407xx.h:280
PWR_TypeDef
Power Control.
Definition: stm32f407xx.h:587
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f407xx.h:597
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32f411xe.h:70
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32f411xe.h:118
PVD_IRQn
@ PVD_IRQn
Definition: stm32f411xe.h:79
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32f411xe.h:102
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition: stm32f411xe.h:99
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32f411xe.h:76
IRQn_Type
IRQn_Type
STM32F4XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f411xe.h:66
RCC_IRQn
@ RCC_IRQn
Definition: stm32f411xe.h:83
FPU_IRQn
@ FPU_IRQn
Definition: stm32f411xe.h:132
ADC_TypeDef
Analog to Digital Converter
Definition: stm32f407xx.h:179
USART1_IRQn
@ USART1_IRQn
Definition: stm32f411xe.h:111
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32f411xe.h:113
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f407xx.h:443
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32f411xe.h:89
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32f411xe.h:105
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f407xx.h:889
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32f411xe.h:128
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32f411xe.h:108
system_stm32f4xx.h
CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32f411xe.h:71
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32f411xe.h:104
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f407xx.h:527
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32f411xe.h:110
ADC_IRQn
@ ADC_IRQn
Definition: stm32f411xe.h:96
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f407xx.h:773
ADC_Common_TypeDef
Definition: stm32f407xx.h:203
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32f411xe.h:120
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32f411xe.h:95
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32f411xe.h:88
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32f411xe.h:73
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32f411xe.h:122
RCC_TypeDef::DCKCFGR
__IO uint32_t DCKCFGR
Definition: stm32f411xe.h:370
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32f411xe.h:90
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f411xe.h:100
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f407xx.h:819
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32f411xe.h:84
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32f411xe.h:93
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32f411xe.h:78
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32f411xe.h:75
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32f411xe.h:114
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32f411xe.h:94
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32f411xe.h:69
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32f411xe.h:126
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition: stm32f411xe.h:115
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32f411xe.h:92
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32f411xe.h:81
FLASH_TypeDef
FLASH Registers.
Definition: stm32f407xx.h:457
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32f411xe.h:119
SPI5_IRQn
@ SPI5_IRQn
Definition: stm32f411xe.h:134
USART2_IRQn
@ USART2_IRQn
Definition: stm32f411xe.h:112
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f407xx.h:544
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32f411xe.h:123
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32f411xe.h:107
RTC_TypeDef
Real-Time Clock.
Definition: stm32f407xx.h:635
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition: stm32f411xe.h:98

picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:14:51