Collaboration diagram for PWR CSR Register alias address:
Macros | |
| #define | CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) |
| #define | CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) |
| #define | CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) |
| #define | EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos |
| #define | EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos |
| #define | EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos |
Detailed Description
Macro Definition Documentation
◆ CSR_EWUP_BB [1/3]
| #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) |
Definition at line 380 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h.
◆ CSR_EWUP_BB [2/3]
| #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) |
Definition at line 380 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h.
◆ CSR_EWUP_BB [3/3]
| #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) |
Definition at line 380 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h.
◆ EWUP_BIT_NUMBER [1/3]
| #define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos |
Definition at line 379 of file stm32f407/stm32f407g-disc1/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h.
◆ EWUP_BIT_NUMBER [2/3]
| #define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos |
Definition at line 379 of file stm32f469/stm32f469i-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h.
◆ EWUP_BIT_NUMBER [3/3]
| #define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos |
Definition at line 379 of file stm32f411/stm32f411e-disco/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h.