Macros
PWM Register Masks
Mapping Information » Edma_request » Iomuxc_pads » Device Peripheral Access Layer » PWM Peripheral Access Layer
Collaboration diagram for PWM Register Masks:

Macros

#define PWM_CAPTCOMPA_COUNT   (4U)
 
#define PWM_CAPTCOMPB_COUNT   (4U)
 
#define PWM_CAPTCOMPX_COUNT   (4U)
 
#define PWM_CAPTCTRLA_COUNT   (4U)
 
#define PWM_CAPTCTRLB_COUNT   (4U)
 
#define PWM_CAPTCTRLX_COUNT   (4U)
 
#define PWM_CNT_COUNT   (4U)
 
#define PWM_CTRL2_COUNT   (4U)
 
#define PWM_CTRL_COUNT   (4U)
 
#define PWM_CVAL0_COUNT   (4U)
 
#define PWM_CVAL0CYC_COUNT   (4U)
 
#define PWM_CVAL1_COUNT   (4U)
 
#define PWM_CVAL1CYC_COUNT   (4U)
 
#define PWM_CVAL2_COUNT   (4U)
 
#define PWM_CVAL2CYC_COUNT   (4U)
 
#define PWM_CVAL3_COUNT   (4U)
 
#define PWM_CVAL3CYC_COUNT   (4U)
 
#define PWM_CVAL4_COUNT   (4U)
 
#define PWM_CVAL4CYC_COUNT   (4U)
 
#define PWM_CVAL5_COUNT   (4U)
 
#define PWM_CVAL5CYC_COUNT   (4U)
 
#define PWM_DISMAP_COUNT   (4U)
 
#define PWM_DISMAP_COUNT2   (2U)
 
#define PWM_DMAEN_COUNT   (4U)
 
#define PWM_DTCNT0_COUNT   (4U)
 
#define PWM_DTCNT1_COUNT   (4U)
 
#define PWM_FRACVAL1_COUNT   (4U)
 
#define PWM_FRACVAL2_COUNT   (4U)
 
#define PWM_FRACVAL3_COUNT   (4U)
 
#define PWM_FRACVAL4_COUNT   (4U)
 
#define PWM_FRACVAL5_COUNT   (4U)
 
#define PWM_FRCTRL_COUNT   (4U)
 
#define PWM_INIT_COUNT   (4U)
 
#define PWM_INTEN_COUNT   (4U)
 
#define PWM_OCTRL_COUNT   (4U)
 
#define PWM_STS_COUNT   (4U)
 
#define PWM_TCTRL_COUNT   (4U)
 
#define PWM_VAL0_COUNT   (4U)
 
#define PWM_VAL1_COUNT   (4U)
 
#define PWM_VAL2_COUNT   (4U)
 
#define PWM_VAL3_COUNT   (4U)
 
#define PWM_VAL4_COUNT   (4U)
 
#define PWM_VAL5_COUNT   (4U)
 

CTRL - Control Register

#define PWM_CTRL_DBLEN_MASK   (0x1U)
 
#define PWM_CTRL_DBLEN_SHIFT   (0U)
 
#define PWM_CTRL_DBLEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
 
#define PWM_CTRL_DBLX_MASK   (0x2U)
 
#define PWM_CTRL_DBLX_SHIFT   (1U)
 
#define PWM_CTRL_DBLX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
 
#define PWM_CTRL_LDMOD_MASK   (0x4U)
 
#define PWM_CTRL_LDMOD_SHIFT   (2U)
 
#define PWM_CTRL_LDMOD(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
 
#define PWM_CTRL_SPLIT_MASK   (0x8U)
 
#define PWM_CTRL_SPLIT_SHIFT   (3U)
 
#define PWM_CTRL_SPLIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
 
#define PWM_CTRL_PRSC_MASK   (0x70U)
 
#define PWM_CTRL_PRSC_SHIFT   (4U)
 
#define PWM_CTRL_PRSC(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
 
#define PWM_CTRL_COMPMODE_MASK   (0x80U)
 
#define PWM_CTRL_COMPMODE_SHIFT   (7U)
 
#define PWM_CTRL_COMPMODE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
 
#define PWM_CTRL_DT_MASK   (0x300U)
 
#define PWM_CTRL_DT_SHIFT   (8U)
 
#define PWM_CTRL_DT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
 
#define PWM_CTRL_FULL_MASK   (0x400U)
 
#define PWM_CTRL_FULL_SHIFT   (10U)
 
#define PWM_CTRL_FULL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
 
#define PWM_CTRL_HALF_MASK   (0x800U)
 
#define PWM_CTRL_HALF_SHIFT   (11U)
 
#define PWM_CTRL_HALF(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
 
#define PWM_CTRL_LDFQ_MASK   (0xF000U)
 
#define PWM_CTRL_LDFQ_SHIFT   (12U)
 
#define PWM_CTRL_LDFQ(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
 

CTRL2 - Control 2 Register

#define PWM_CTRL2_CLK_SEL_MASK   (0x3U)
 
#define PWM_CTRL2_CLK_SEL_SHIFT   (0U)
 
#define PWM_CTRL2_CLK_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
 
#define PWM_CTRL2_RELOAD_SEL_MASK   (0x4U)
 
#define PWM_CTRL2_RELOAD_SEL_SHIFT   (2U)
 
#define PWM_CTRL2_RELOAD_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
 
#define PWM_CTRL2_FORCE_SEL_MASK   (0x38U)
 
#define PWM_CTRL2_FORCE_SEL_SHIFT   (3U)
 
#define PWM_CTRL2_FORCE_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
 
#define PWM_CTRL2_FORCE_MASK   (0x40U)
 
#define PWM_CTRL2_FORCE_SHIFT   (6U)
 
#define PWM_CTRL2_FORCE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
 
#define PWM_CTRL2_FRCEN_MASK   (0x80U)
 
#define PWM_CTRL2_FRCEN_SHIFT   (7U)
 
#define PWM_CTRL2_FRCEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
 
#define PWM_CTRL2_INIT_SEL_MASK   (0x300U)
 
#define PWM_CTRL2_INIT_SEL_SHIFT   (8U)
 
#define PWM_CTRL2_INIT_SEL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
 
#define PWM_CTRL2_PWMX_INIT_MASK   (0x400U)
 
#define PWM_CTRL2_PWMX_INIT_SHIFT   (10U)
 
#define PWM_CTRL2_PWMX_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
 
#define PWM_CTRL2_PWM45_INIT_MASK   (0x800U)
 
#define PWM_CTRL2_PWM45_INIT_SHIFT   (11U)
 
#define PWM_CTRL2_PWM45_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
 
#define PWM_CTRL2_PWM23_INIT_MASK   (0x1000U)
 
#define PWM_CTRL2_PWM23_INIT_SHIFT   (12U)
 
#define PWM_CTRL2_PWM23_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
 
#define PWM_CTRL2_INDEP_MASK   (0x2000U)
 
#define PWM_CTRL2_INDEP_SHIFT   (13U)
 
#define PWM_CTRL2_INDEP(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
 
#define PWM_CTRL2_WAITEN_MASK   (0x4000U)
 
#define PWM_CTRL2_WAITEN_SHIFT   (14U)
 
#define PWM_CTRL2_WAITEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
 
#define PWM_CTRL2_DBGEN_MASK   (0x8000U)
 
#define PWM_CTRL2_DBGEN_SHIFT   (15U)
 
#define PWM_CTRL2_DBGEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
 

INTEN - Interrupt Enable Register

#define PWM_INTEN_CMPIE_MASK   (0x3FU)
 
#define PWM_INTEN_CMPIE_SHIFT   (0U)
 
#define PWM_INTEN_CMPIE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
 
#define PWM_INTEN_CX0IE_MASK   (0x40U)
 
#define PWM_INTEN_CX0IE_SHIFT   (6U)
 
#define PWM_INTEN_CX0IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
 
#define PWM_INTEN_CX1IE_MASK   (0x80U)
 
#define PWM_INTEN_CX1IE_SHIFT   (7U)
 
#define PWM_INTEN_CX1IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
 
#define PWM_INTEN_CB0IE_MASK   (0x100U)
 
#define PWM_INTEN_CB0IE_SHIFT   (8U)
 
#define PWM_INTEN_CB0IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
 
#define PWM_INTEN_CB1IE_MASK   (0x200U)
 
#define PWM_INTEN_CB1IE_SHIFT   (9U)
 
#define PWM_INTEN_CB1IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
 
#define PWM_INTEN_CA0IE_MASK   (0x400U)
 
#define PWM_INTEN_CA0IE_SHIFT   (10U)
 
#define PWM_INTEN_CA0IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
 
#define PWM_INTEN_CA1IE_MASK   (0x800U)
 
#define PWM_INTEN_CA1IE_SHIFT   (11U)
 
#define PWM_INTEN_CA1IE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
 
#define PWM_INTEN_RIE_MASK   (0x1000U)
 
#define PWM_INTEN_RIE_SHIFT   (12U)
 
#define PWM_INTEN_RIE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
 
#define PWM_INTEN_REIE_MASK   (0x2000U)
 
#define PWM_INTEN_REIE_SHIFT   (13U)
 
#define PWM_INTEN_REIE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
 

CNT - Counter Register

#define PWM_CNT_CNT_MASK   (0xFFFFU)
 
#define PWM_CNT_CNT_SHIFT   (0U)
 
#define PWM_CNT_CNT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
 

INIT - Initial Count Register

#define PWM_INIT_INIT_MASK   (0xFFFFU)
 
#define PWM_INIT_INIT_SHIFT   (0U)
 
#define PWM_INIT_INIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
 

VAL0 - Value Register 0

#define PWM_VAL0_VAL0_MASK   (0xFFFFU)
 
#define PWM_VAL0_VAL0_SHIFT   (0U)
 
#define PWM_VAL0_VAL0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
 

FRACVAL1 - Fractional Value Register 1

#define PWM_FRACVAL1_FRACVAL1_MASK   (0xF800U)
 
#define PWM_FRACVAL1_FRACVAL1_SHIFT   (11U)
 
#define PWM_FRACVAL1_FRACVAL1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
 

VAL1 - Value Register 1

#define PWM_VAL1_VAL1_MASK   (0xFFFFU)
 
#define PWM_VAL1_VAL1_SHIFT   (0U)
 
#define PWM_VAL1_VAL1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
 

FRACVAL2 - Fractional Value Register 2

#define PWM_FRACVAL2_FRACVAL2_MASK   (0xF800U)
 
#define PWM_FRACVAL2_FRACVAL2_SHIFT   (11U)
 
#define PWM_FRACVAL2_FRACVAL2(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
 

VAL2 - Value Register 2

#define PWM_VAL2_VAL2_MASK   (0xFFFFU)
 
#define PWM_VAL2_VAL2_SHIFT   (0U)
 
#define PWM_VAL2_VAL2(x)   (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
 

FRACVAL3 - Fractional Value Register 3

#define PWM_FRACVAL3_FRACVAL3_MASK   (0xF800U)
 
#define PWM_FRACVAL3_FRACVAL3_SHIFT   (11U)
 
#define PWM_FRACVAL3_FRACVAL3(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
 

VAL3 - Value Register 3

#define PWM_VAL3_VAL3_MASK   (0xFFFFU)
 
#define PWM_VAL3_VAL3_SHIFT   (0U)
 
#define PWM_VAL3_VAL3(x)   (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
 

FRACVAL4 - Fractional Value Register 4

#define PWM_FRACVAL4_FRACVAL4_MASK   (0xF800U)
 
#define PWM_FRACVAL4_FRACVAL4_SHIFT   (11U)
 
#define PWM_FRACVAL4_FRACVAL4(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
 

VAL4 - Value Register 4

#define PWM_VAL4_VAL4_MASK   (0xFFFFU)
 
#define PWM_VAL4_VAL4_SHIFT   (0U)
 
#define PWM_VAL4_VAL4(x)   (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
 

FRACVAL5 - Fractional Value Register 5

#define PWM_FRACVAL5_FRACVAL5_MASK   (0xF800U)
 
#define PWM_FRACVAL5_FRACVAL5_SHIFT   (11U)
 
#define PWM_FRACVAL5_FRACVAL5(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
 

VAL5 - Value Register 5

#define PWM_VAL5_VAL5_MASK   (0xFFFFU)
 
#define PWM_VAL5_VAL5_SHIFT   (0U)
 
#define PWM_VAL5_VAL5(x)   (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
 

FRCTRL - Fractional Control Register

#define PWM_FRCTRL_FRAC1_EN_MASK   (0x2U)
 
#define PWM_FRCTRL_FRAC1_EN_SHIFT   (1U)
 
#define PWM_FRCTRL_FRAC1_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
 
#define PWM_FRCTRL_FRAC23_EN_MASK   (0x4U)
 
#define PWM_FRCTRL_FRAC23_EN_SHIFT   (2U)
 
#define PWM_FRCTRL_FRAC23_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
 
#define PWM_FRCTRL_FRAC45_EN_MASK   (0x10U)
 
#define PWM_FRCTRL_FRAC45_EN_SHIFT   (4U)
 
#define PWM_FRCTRL_FRAC45_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
 
#define PWM_FRCTRL_FRAC_PU_MASK   (0x100U)
 
#define PWM_FRCTRL_FRAC_PU_SHIFT   (8U)
 
#define PWM_FRCTRL_FRAC_PU(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)
 
#define PWM_FRCTRL_TEST_MASK   (0x8000U)
 
#define PWM_FRCTRL_TEST_SHIFT   (15U)
 
#define PWM_FRCTRL_TEST(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
 

OCTRL - Output Control Register

#define PWM_OCTRL_PWMXFS_MASK   (0x3U)
 
#define PWM_OCTRL_PWMXFS_SHIFT   (0U)
 
#define PWM_OCTRL_PWMXFS(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
 
#define PWM_OCTRL_PWMBFS_MASK   (0xCU)
 
#define PWM_OCTRL_PWMBFS_SHIFT   (2U)
 
#define PWM_OCTRL_PWMBFS(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
 
#define PWM_OCTRL_PWMAFS_MASK   (0x30U)
 
#define PWM_OCTRL_PWMAFS_SHIFT   (4U)
 
#define PWM_OCTRL_PWMAFS(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
 
#define PWM_OCTRL_POLX_MASK   (0x100U)
 
#define PWM_OCTRL_POLX_SHIFT   (8U)
 
#define PWM_OCTRL_POLX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
 
#define PWM_OCTRL_POLB_MASK   (0x200U)
 
#define PWM_OCTRL_POLB_SHIFT   (9U)
 
#define PWM_OCTRL_POLB(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
 
#define PWM_OCTRL_POLA_MASK   (0x400U)
 
#define PWM_OCTRL_POLA_SHIFT   (10U)
 
#define PWM_OCTRL_POLA(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
 
#define PWM_OCTRL_PWMX_IN_MASK   (0x2000U)
 
#define PWM_OCTRL_PWMX_IN_SHIFT   (13U)
 
#define PWM_OCTRL_PWMX_IN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
 
#define PWM_OCTRL_PWMB_IN_MASK   (0x4000U)
 
#define PWM_OCTRL_PWMB_IN_SHIFT   (14U)
 
#define PWM_OCTRL_PWMB_IN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
 
#define PWM_OCTRL_PWMA_IN_MASK   (0x8000U)
 
#define PWM_OCTRL_PWMA_IN_SHIFT   (15U)
 
#define PWM_OCTRL_PWMA_IN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
 

STS - Status Register

#define PWM_STS_CMPF_MASK   (0x3FU)
 
#define PWM_STS_CMPF_SHIFT   (0U)
 
#define PWM_STS_CMPF(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
 
#define PWM_STS_CFX0_MASK   (0x40U)
 
#define PWM_STS_CFX0_SHIFT   (6U)
 
#define PWM_STS_CFX0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
 
#define PWM_STS_CFX1_MASK   (0x80U)
 
#define PWM_STS_CFX1_SHIFT   (7U)
 
#define PWM_STS_CFX1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
 
#define PWM_STS_CFB0_MASK   (0x100U)
 
#define PWM_STS_CFB0_SHIFT   (8U)
 
#define PWM_STS_CFB0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
 
#define PWM_STS_CFB1_MASK   (0x200U)
 
#define PWM_STS_CFB1_SHIFT   (9U)
 
#define PWM_STS_CFB1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
 
#define PWM_STS_CFA0_MASK   (0x400U)
 
#define PWM_STS_CFA0_SHIFT   (10U)
 
#define PWM_STS_CFA0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
 
#define PWM_STS_CFA1_MASK   (0x800U)
 
#define PWM_STS_CFA1_SHIFT   (11U)
 
#define PWM_STS_CFA1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
 
#define PWM_STS_RF_MASK   (0x1000U)
 
#define PWM_STS_RF_SHIFT   (12U)
 
#define PWM_STS_RF(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
 
#define PWM_STS_REF_MASK   (0x2000U)
 
#define PWM_STS_REF_SHIFT   (13U)
 
#define PWM_STS_REF(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
 
#define PWM_STS_RUF_MASK   (0x4000U)
 
#define PWM_STS_RUF_SHIFT   (14U)
 
#define PWM_STS_RUF(x)   (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
 

DMAEN - DMA Enable Register

#define PWM_DMAEN_CX0DE_MASK   (0x1U)
 
#define PWM_DMAEN_CX0DE_SHIFT   (0U)
 
#define PWM_DMAEN_CX0DE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
 
#define PWM_DMAEN_CX1DE_MASK   (0x2U)
 
#define PWM_DMAEN_CX1DE_SHIFT   (1U)
 
#define PWM_DMAEN_CX1DE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
 
#define PWM_DMAEN_CB0DE_MASK   (0x4U)
 
#define PWM_DMAEN_CB0DE_SHIFT   (2U)
 
#define PWM_DMAEN_CB0DE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
 
#define PWM_DMAEN_CB1DE_MASK   (0x8U)
 
#define PWM_DMAEN_CB1DE_SHIFT   (3U)
 
#define PWM_DMAEN_CB1DE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
 
#define PWM_DMAEN_CA0DE_MASK   (0x10U)
 
#define PWM_DMAEN_CA0DE_SHIFT   (4U)
 
#define PWM_DMAEN_CA0DE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
 
#define PWM_DMAEN_CA1DE_MASK   (0x20U)
 
#define PWM_DMAEN_CA1DE_SHIFT   (5U)
 
#define PWM_DMAEN_CA1DE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
 
#define PWM_DMAEN_CAPTDE_MASK   (0xC0U)
 
#define PWM_DMAEN_CAPTDE_SHIFT   (6U)
 
#define PWM_DMAEN_CAPTDE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
 
#define PWM_DMAEN_FAND_MASK   (0x100U)
 
#define PWM_DMAEN_FAND_SHIFT   (8U)
 
#define PWM_DMAEN_FAND(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
 
#define PWM_DMAEN_VALDE_MASK   (0x200U)
 
#define PWM_DMAEN_VALDE_SHIFT   (9U)
 
#define PWM_DMAEN_VALDE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
 

TCTRL - Output Trigger Control Register

#define PWM_TCTRL_OUT_TRIG_EN_MASK   (0x3FU)
 
#define PWM_TCTRL_OUT_TRIG_EN_SHIFT   (0U)
 
#define PWM_TCTRL_OUT_TRIG_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
 
#define PWM_TCTRL_TRGFRQ_MASK   (0x1000U)
 
#define PWM_TCTRL_TRGFRQ_SHIFT   (12U)
 
#define PWM_TCTRL_TRGFRQ(x)   (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
 
#define PWM_TCTRL_PWBOT1_MASK   (0x4000U)
 
#define PWM_TCTRL_PWBOT1_SHIFT   (14U)
 
#define PWM_TCTRL_PWBOT1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
 
#define PWM_TCTRL_PWAOT0_MASK   (0x8000U)
 
#define PWM_TCTRL_PWAOT0_SHIFT   (15U)
 
#define PWM_TCTRL_PWAOT0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
 

DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1

#define PWM_DISMAP_DIS0A_MASK   (0xFU)
 
#define PWM_DISMAP_DIS0A_SHIFT   (0U)
 
#define PWM_DISMAP_DIS0A(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
 
#define PWM_DISMAP_DIS1A_MASK   (0xFU)
 
#define PWM_DISMAP_DIS1A_SHIFT   (0U)
 
#define PWM_DISMAP_DIS1A(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)
 
#define PWM_DISMAP_DIS0B_MASK   (0xF0U)
 
#define PWM_DISMAP_DIS0B_SHIFT   (4U)
 
#define PWM_DISMAP_DIS0B(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
 
#define PWM_DISMAP_DIS1B_MASK   (0xF0U)
 
#define PWM_DISMAP_DIS1B_SHIFT   (4U)
 
#define PWM_DISMAP_DIS1B(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)
 
#define PWM_DISMAP_DIS0X_MASK   (0xF00U)
 
#define PWM_DISMAP_DIS0X_SHIFT   (8U)
 
#define PWM_DISMAP_DIS0X(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
 
#define PWM_DISMAP_DIS1X_MASK   (0xF00U)
 
#define PWM_DISMAP_DIS1X_SHIFT   (8U)
 
#define PWM_DISMAP_DIS1X(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)
 

DTCNT0 - Deadtime Count Register 0

#define PWM_DTCNT0_DTCNT0_MASK   (0xFFFFU)
 
#define PWM_DTCNT0_DTCNT0_SHIFT   (0U)
 
#define PWM_DTCNT0_DTCNT0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
 

DTCNT1 - Deadtime Count Register 1

#define PWM_DTCNT1_DTCNT1_MASK   (0xFFFFU)
 
#define PWM_DTCNT1_DTCNT1_SHIFT   (0U)
 
#define PWM_DTCNT1_DTCNT1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
 

CAPTCTRLA - Capture Control A Register

#define PWM_CAPTCTRLA_ARMA_MASK   (0x1U)
 
#define PWM_CAPTCTRLA_ARMA_SHIFT   (0U)
 
#define PWM_CAPTCTRLA_ARMA(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
 
#define PWM_CAPTCTRLA_ONESHOTA_MASK   (0x2U)
 
#define PWM_CAPTCTRLA_ONESHOTA_SHIFT   (1U)
 
#define PWM_CAPTCTRLA_ONESHOTA(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
 
#define PWM_CAPTCTRLA_EDGA0_MASK   (0xCU)
 
#define PWM_CAPTCTRLA_EDGA0_SHIFT   (2U)
 
#define PWM_CAPTCTRLA_EDGA0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
 
#define PWM_CAPTCTRLA_EDGA1_MASK   (0x30U)
 
#define PWM_CAPTCTRLA_EDGA1_SHIFT   (4U)
 
#define PWM_CAPTCTRLA_EDGA1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
 
#define PWM_CAPTCTRLA_INP_SELA_MASK   (0x40U)
 
#define PWM_CAPTCTRLA_INP_SELA_SHIFT   (6U)
 
#define PWM_CAPTCTRLA_INP_SELA(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
 
#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK   (0x80U)
 
#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT   (7U)
 
#define PWM_CAPTCTRLA_EDGCNTA_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
 
#define PWM_CAPTCTRLA_CFAWM_MASK   (0x300U)
 
#define PWM_CAPTCTRLA_CFAWM_SHIFT   (8U)
 
#define PWM_CAPTCTRLA_CFAWM(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
 
#define PWM_CAPTCTRLA_CA0CNT_MASK   (0x1C00U)
 
#define PWM_CAPTCTRLA_CA0CNT_SHIFT   (10U)
 
#define PWM_CAPTCTRLA_CA0CNT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
 
#define PWM_CAPTCTRLA_CA1CNT_MASK   (0xE000U)
 
#define PWM_CAPTCTRLA_CA1CNT_SHIFT   (13U)
 
#define PWM_CAPTCTRLA_CA1CNT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
 

CAPTCOMPA - Capture Compare A Register

#define PWM_CAPTCOMPA_EDGCMPA_MASK   (0xFFU)
 
#define PWM_CAPTCOMPA_EDGCMPA_SHIFT   (0U)
 
#define PWM_CAPTCOMPA_EDGCMPA(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
 
#define PWM_CAPTCOMPA_EDGCNTA_MASK   (0xFF00U)
 
#define PWM_CAPTCOMPA_EDGCNTA_SHIFT   (8U)
 
#define PWM_CAPTCOMPA_EDGCNTA(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
 

CAPTCTRLB - Capture Control B Register

#define PWM_CAPTCTRLB_ARMB_MASK   (0x1U)
 
#define PWM_CAPTCTRLB_ARMB_SHIFT   (0U)
 
#define PWM_CAPTCTRLB_ARMB(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
 
#define PWM_CAPTCTRLB_ONESHOTB_MASK   (0x2U)
 
#define PWM_CAPTCTRLB_ONESHOTB_SHIFT   (1U)
 
#define PWM_CAPTCTRLB_ONESHOTB(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
 
#define PWM_CAPTCTRLB_EDGB0_MASK   (0xCU)
 
#define PWM_CAPTCTRLB_EDGB0_SHIFT   (2U)
 
#define PWM_CAPTCTRLB_EDGB0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
 
#define PWM_CAPTCTRLB_EDGB1_MASK   (0x30U)
 
#define PWM_CAPTCTRLB_EDGB1_SHIFT   (4U)
 
#define PWM_CAPTCTRLB_EDGB1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
 
#define PWM_CAPTCTRLB_INP_SELB_MASK   (0x40U)
 
#define PWM_CAPTCTRLB_INP_SELB_SHIFT   (6U)
 
#define PWM_CAPTCTRLB_INP_SELB(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
 
#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK   (0x80U)
 
#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT   (7U)
 
#define PWM_CAPTCTRLB_EDGCNTB_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
 
#define PWM_CAPTCTRLB_CFBWM_MASK   (0x300U)
 
#define PWM_CAPTCTRLB_CFBWM_SHIFT   (8U)
 
#define PWM_CAPTCTRLB_CFBWM(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
 
#define PWM_CAPTCTRLB_CB0CNT_MASK   (0x1C00U)
 
#define PWM_CAPTCTRLB_CB0CNT_SHIFT   (10U)
 
#define PWM_CAPTCTRLB_CB0CNT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
 
#define PWM_CAPTCTRLB_CB1CNT_MASK   (0xE000U)
 
#define PWM_CAPTCTRLB_CB1CNT_SHIFT   (13U)
 
#define PWM_CAPTCTRLB_CB1CNT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
 

CAPTCOMPB - Capture Compare B Register

#define PWM_CAPTCOMPB_EDGCMPB_MASK   (0xFFU)
 
#define PWM_CAPTCOMPB_EDGCMPB_SHIFT   (0U)
 
#define PWM_CAPTCOMPB_EDGCMPB(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
 
#define PWM_CAPTCOMPB_EDGCNTB_MASK   (0xFF00U)
 
#define PWM_CAPTCOMPB_EDGCNTB_SHIFT   (8U)
 
#define PWM_CAPTCOMPB_EDGCNTB(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
 

CAPTCTRLX - Capture Control X Register

#define PWM_CAPTCTRLX_ARMX_MASK   (0x1U)
 
#define PWM_CAPTCTRLX_ARMX_SHIFT   (0U)
 
#define PWM_CAPTCTRLX_ARMX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
 
#define PWM_CAPTCTRLX_ONESHOTX_MASK   (0x2U)
 
#define PWM_CAPTCTRLX_ONESHOTX_SHIFT   (1U)
 
#define PWM_CAPTCTRLX_ONESHOTX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
 
#define PWM_CAPTCTRLX_EDGX0_MASK   (0xCU)
 
#define PWM_CAPTCTRLX_EDGX0_SHIFT   (2U)
 
#define PWM_CAPTCTRLX_EDGX0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
 
#define PWM_CAPTCTRLX_EDGX1_MASK   (0x30U)
 
#define PWM_CAPTCTRLX_EDGX1_SHIFT   (4U)
 
#define PWM_CAPTCTRLX_EDGX1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
 
#define PWM_CAPTCTRLX_INP_SELX_MASK   (0x40U)
 
#define PWM_CAPTCTRLX_INP_SELX_SHIFT   (6U)
 
#define PWM_CAPTCTRLX_INP_SELX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
 
#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK   (0x80U)
 
#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT   (7U)
 
#define PWM_CAPTCTRLX_EDGCNTX_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
 
#define PWM_CAPTCTRLX_CFXWM_MASK   (0x300U)
 
#define PWM_CAPTCTRLX_CFXWM_SHIFT   (8U)
 
#define PWM_CAPTCTRLX_CFXWM(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
 
#define PWM_CAPTCTRLX_CX0CNT_MASK   (0x1C00U)
 
#define PWM_CAPTCTRLX_CX0CNT_SHIFT   (10U)
 
#define PWM_CAPTCTRLX_CX0CNT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
 
#define PWM_CAPTCTRLX_CX1CNT_MASK   (0xE000U)
 
#define PWM_CAPTCTRLX_CX1CNT_SHIFT   (13U)
 
#define PWM_CAPTCTRLX_CX1CNT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
 

CAPTCOMPX - Capture Compare X Register

#define PWM_CAPTCOMPX_EDGCMPX_MASK   (0xFFU)
 
#define PWM_CAPTCOMPX_EDGCMPX_SHIFT   (0U)
 
#define PWM_CAPTCOMPX_EDGCMPX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
 
#define PWM_CAPTCOMPX_EDGCNTX_MASK   (0xFF00U)
 
#define PWM_CAPTCOMPX_EDGCNTX_SHIFT   (8U)
 
#define PWM_CAPTCOMPX_EDGCNTX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
 

CVAL0 - Capture Value 0 Register

#define PWM_CVAL0_CAPTVAL0_MASK   (0xFFFFU)
 
#define PWM_CVAL0_CAPTVAL0_SHIFT   (0U)
 
#define PWM_CVAL0_CAPTVAL0(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
 

CVAL0CYC - Capture Value 0 Cycle Register

#define PWM_CVAL0CYC_CVAL0CYC_MASK   (0xFU)
 
#define PWM_CVAL0CYC_CVAL0CYC_SHIFT   (0U)
 
#define PWM_CVAL0CYC_CVAL0CYC(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
 

CVAL1 - Capture Value 1 Register

#define PWM_CVAL1_CAPTVAL1_MASK   (0xFFFFU)
 
#define PWM_CVAL1_CAPTVAL1_SHIFT   (0U)
 
#define PWM_CVAL1_CAPTVAL1(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
 

CVAL1CYC - Capture Value 1 Cycle Register

#define PWM_CVAL1CYC_CVAL1CYC_MASK   (0xFU)
 
#define PWM_CVAL1CYC_CVAL1CYC_SHIFT   (0U)
 
#define PWM_CVAL1CYC_CVAL1CYC(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
 

CVAL2 - Capture Value 2 Register

#define PWM_CVAL2_CAPTVAL2_MASK   (0xFFFFU)
 
#define PWM_CVAL2_CAPTVAL2_SHIFT   (0U)
 
#define PWM_CVAL2_CAPTVAL2(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
 

CVAL2CYC - Capture Value 2 Cycle Register

#define PWM_CVAL2CYC_CVAL2CYC_MASK   (0xFU)
 
#define PWM_CVAL2CYC_CVAL2CYC_SHIFT   (0U)
 
#define PWM_CVAL2CYC_CVAL2CYC(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
 

CVAL3 - Capture Value 3 Register

#define PWM_CVAL3_CAPTVAL3_MASK   (0xFFFFU)
 
#define PWM_CVAL3_CAPTVAL3_SHIFT   (0U)
 
#define PWM_CVAL3_CAPTVAL3(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
 

CVAL3CYC - Capture Value 3 Cycle Register

#define PWM_CVAL3CYC_CVAL3CYC_MASK   (0xFU)
 
#define PWM_CVAL3CYC_CVAL3CYC_SHIFT   (0U)
 
#define PWM_CVAL3CYC_CVAL3CYC(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
 

CVAL4 - Capture Value 4 Register

#define PWM_CVAL4_CAPTVAL4_MASK   (0xFFFFU)
 
#define PWM_CVAL4_CAPTVAL4_SHIFT   (0U)
 
#define PWM_CVAL4_CAPTVAL4(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
 

CVAL4CYC - Capture Value 4 Cycle Register

#define PWM_CVAL4CYC_CVAL4CYC_MASK   (0xFU)
 
#define PWM_CVAL4CYC_CVAL4CYC_SHIFT   (0U)
 
#define PWM_CVAL4CYC_CVAL4CYC(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
 

CVAL5 - Capture Value 5 Register

#define PWM_CVAL5_CAPTVAL5_MASK   (0xFFFFU)
 
#define PWM_CVAL5_CAPTVAL5_SHIFT   (0U)
 
#define PWM_CVAL5_CAPTVAL5(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
 

CVAL5CYC - Capture Value 5 Cycle Register

#define PWM_CVAL5CYC_CVAL5CYC_MASK   (0xFU)
 
#define PWM_CVAL5CYC_CVAL5CYC_SHIFT   (0U)
 
#define PWM_CVAL5CYC_CVAL5CYC(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
 

OUTEN - Output Enable Register

#define PWM_OUTEN_PWMX_EN_MASK   (0xFU)
 
#define PWM_OUTEN_PWMX_EN_SHIFT   (0U)
 
#define PWM_OUTEN_PWMX_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
 
#define PWM_OUTEN_PWMB_EN_MASK   (0xF0U)
 
#define PWM_OUTEN_PWMB_EN_SHIFT   (4U)
 
#define PWM_OUTEN_PWMB_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
 
#define PWM_OUTEN_PWMA_EN_MASK   (0xF00U)
 
#define PWM_OUTEN_PWMA_EN_SHIFT   (8U)
 
#define PWM_OUTEN_PWMA_EN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
 

MASK - Mask Register

#define PWM_MASK_MASKX_MASK   (0xFU)
 
#define PWM_MASK_MASKX_SHIFT   (0U)
 
#define PWM_MASK_MASKX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
 
#define PWM_MASK_MASKB_MASK   (0xF0U)
 
#define PWM_MASK_MASKB_SHIFT   (4U)
 
#define PWM_MASK_MASKB(x)   (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
 
#define PWM_MASK_MASKA_MASK   (0xF00U)
 
#define PWM_MASK_MASKA_SHIFT   (8U)
 
#define PWM_MASK_MASKA(x)   (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
 
#define PWM_MASK_UPDATE_MASK_MASK   (0xF000U)
 
#define PWM_MASK_UPDATE_MASK_SHIFT   (12U)
 
#define PWM_MASK_UPDATE_MASK(x)   (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)
 

SWCOUT - Software Controlled Output Register

#define PWM_SWCOUT_SM0OUT45_MASK   (0x1U)
 
#define PWM_SWCOUT_SM0OUT45_SHIFT   (0U)
 
#define PWM_SWCOUT_SM0OUT45(x)   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
 
#define PWM_SWCOUT_SM0OUT23_MASK   (0x2U)
 
#define PWM_SWCOUT_SM0OUT23_SHIFT   (1U)
 
#define PWM_SWCOUT_SM0OUT23(x)   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
 
#define PWM_SWCOUT_SM1OUT45_MASK   (0x4U)
 
#define PWM_SWCOUT_SM1OUT45_SHIFT   (2U)
 
#define PWM_SWCOUT_SM1OUT45(x)   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
 
#define PWM_SWCOUT_SM1OUT23_MASK   (0x8U)
 
#define PWM_SWCOUT_SM1OUT23_SHIFT   (3U)
 
#define PWM_SWCOUT_SM1OUT23(x)   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
 
#define PWM_SWCOUT_SM2OUT45_MASK   (0x10U)
 
#define PWM_SWCOUT_SM2OUT45_SHIFT   (4U)
 
#define PWM_SWCOUT_SM2OUT45(x)   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
 
#define PWM_SWCOUT_SM2OUT23_MASK   (0x20U)
 
#define PWM_SWCOUT_SM2OUT23_SHIFT   (5U)
 
#define PWM_SWCOUT_SM2OUT23(x)   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
 
#define PWM_SWCOUT_SM3OUT45_MASK   (0x40U)
 
#define PWM_SWCOUT_SM3OUT45_SHIFT   (6U)
 
#define PWM_SWCOUT_SM3OUT45(x)   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
 
#define PWM_SWCOUT_SM3OUT23_MASK   (0x80U)
 
#define PWM_SWCOUT_SM3OUT23_SHIFT   (7U)
 
#define PWM_SWCOUT_SM3OUT23(x)   (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
 

DTSRCSEL - PWM Source Select Register

#define PWM_DTSRCSEL_SM0SEL45_MASK   (0x3U)
 
#define PWM_DTSRCSEL_SM0SEL45_SHIFT   (0U)
 
#define PWM_DTSRCSEL_SM0SEL45(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
 
#define PWM_DTSRCSEL_SM0SEL23_MASK   (0xCU)
 
#define PWM_DTSRCSEL_SM0SEL23_SHIFT   (2U)
 
#define PWM_DTSRCSEL_SM0SEL23(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
 
#define PWM_DTSRCSEL_SM1SEL45_MASK   (0x30U)
 
#define PWM_DTSRCSEL_SM1SEL45_SHIFT   (4U)
 
#define PWM_DTSRCSEL_SM1SEL45(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
 
#define PWM_DTSRCSEL_SM1SEL23_MASK   (0xC0U)
 
#define PWM_DTSRCSEL_SM1SEL23_SHIFT   (6U)
 
#define PWM_DTSRCSEL_SM1SEL23(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
 
#define PWM_DTSRCSEL_SM2SEL45_MASK   (0x300U)
 
#define PWM_DTSRCSEL_SM2SEL45_SHIFT   (8U)
 
#define PWM_DTSRCSEL_SM2SEL45(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
 
#define PWM_DTSRCSEL_SM2SEL23_MASK   (0xC00U)
 
#define PWM_DTSRCSEL_SM2SEL23_SHIFT   (10U)
 
#define PWM_DTSRCSEL_SM2SEL23(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
 
#define PWM_DTSRCSEL_SM3SEL45_MASK   (0x3000U)
 
#define PWM_DTSRCSEL_SM3SEL45_SHIFT   (12U)
 
#define PWM_DTSRCSEL_SM3SEL45(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
 
#define PWM_DTSRCSEL_SM3SEL23_MASK   (0xC000U)
 
#define PWM_DTSRCSEL_SM3SEL23_SHIFT   (14U)
 
#define PWM_DTSRCSEL_SM3SEL23(x)   (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
 

MCTRL - Master Control Register

#define PWM_MCTRL_LDOK_MASK   (0xFU)
 
#define PWM_MCTRL_LDOK_SHIFT   (0U)
 
#define PWM_MCTRL_LDOK(x)   (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
 
#define PWM_MCTRL_CLDOK_MASK   (0xF0U)
 
#define PWM_MCTRL_CLDOK_SHIFT   (4U)
 
#define PWM_MCTRL_CLDOK(x)   (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
 
#define PWM_MCTRL_RUN_MASK   (0xF00U)
 
#define PWM_MCTRL_RUN_SHIFT   (8U)
 
#define PWM_MCTRL_RUN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
 
#define PWM_MCTRL_IPOL_MASK   (0xF000U)
 
#define PWM_MCTRL_IPOL_SHIFT   (12U)
 
#define PWM_MCTRL_IPOL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
 

MCTRL2 - Master Control 2 Register

#define PWM_MCTRL2_MONPLL_MASK   (0x3U)
 
#define PWM_MCTRL2_MONPLL_SHIFT   (0U)
 
#define PWM_MCTRL2_MONPLL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
 

FCTRL - Fault Control Register

#define PWM_FCTRL_FIE_MASK   (0xFU)
 
#define PWM_FCTRL_FIE_SHIFT   (0U)
 
#define PWM_FCTRL_FIE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
 
#define PWM_FCTRL_FSAFE_MASK   (0xF0U)
 
#define PWM_FCTRL_FSAFE_SHIFT   (4U)
 
#define PWM_FCTRL_FSAFE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
 
#define PWM_FCTRL_FAUTO_MASK   (0xF00U)
 
#define PWM_FCTRL_FAUTO_SHIFT   (8U)
 
#define PWM_FCTRL_FAUTO(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
 
#define PWM_FCTRL_FLVL_MASK   (0xF000U)
 
#define PWM_FCTRL_FLVL_SHIFT   (12U)
 
#define PWM_FCTRL_FLVL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
 

FSTS - Fault Status Register

#define PWM_FSTS_FFLAG_MASK   (0xFU)
 
#define PWM_FSTS_FFLAG_SHIFT   (0U)
 
#define PWM_FSTS_FFLAG(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
 
#define PWM_FSTS_FFULL_MASK   (0xF0U)
 
#define PWM_FSTS_FFULL_SHIFT   (4U)
 
#define PWM_FSTS_FFULL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
 
#define PWM_FSTS_FFPIN_MASK   (0xF00U)
 
#define PWM_FSTS_FFPIN_SHIFT   (8U)
 
#define PWM_FSTS_FFPIN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
 
#define PWM_FSTS_FHALF_MASK   (0xF000U)
 
#define PWM_FSTS_FHALF_SHIFT   (12U)
 
#define PWM_FSTS_FHALF(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
 

FFILT - Fault Filter Register

#define PWM_FFILT_FILT_PER_MASK   (0xFFU)
 
#define PWM_FFILT_FILT_PER_SHIFT   (0U)
 
#define PWM_FFILT_FILT_PER(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
 
#define PWM_FFILT_FILT_CNT_MASK   (0x700U)
 
#define PWM_FFILT_FILT_CNT_SHIFT   (8U)
 
#define PWM_FFILT_FILT_CNT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
 
#define PWM_FFILT_GSTR_MASK   (0x8000U)
 
#define PWM_FFILT_GSTR_SHIFT   (15U)
 
#define PWM_FFILT_GSTR(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
 

FTST - Fault Test Register

#define PWM_FTST_FTEST_MASK   (0x1U)
 
#define PWM_FTST_FTEST_SHIFT   (0U)
 
#define PWM_FTST_FTEST(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
 

FCTRL2 - Fault Control 2 Register

#define PWM_FCTRL2_NOCOMB_MASK   (0xFU)
 
#define PWM_FCTRL2_NOCOMB_SHIFT   (0U)
 
#define PWM_FCTRL2_NOCOMB(x)   (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
 

Detailed Description

Macro Definition Documentation

◆ PWM_CAPTCOMPA_COUNT

#define PWM_CAPTCOMPA_COUNT   (4U)

Definition at line 31768 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPA_EDGCMPA

#define PWM_CAPTCOMPA_EDGCMPA (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)

EDGCMPA - Edge Compare A

Definition at line 31759 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPA_EDGCMPA_MASK

#define PWM_CAPTCOMPA_EDGCMPA_MASK   (0xFFU)

Definition at line 31755 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPA_EDGCMPA_SHIFT

#define PWM_CAPTCOMPA_EDGCMPA_SHIFT   (0U)

Definition at line 31756 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPA_EDGCNTA

#define PWM_CAPTCOMPA_EDGCNTA (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)

EDGCNTA - Edge Counter A

Definition at line 31764 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPA_EDGCNTA_MASK

#define PWM_CAPTCOMPA_EDGCNTA_MASK   (0xFF00U)

Definition at line 31760 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPA_EDGCNTA_SHIFT

#define PWM_CAPTCOMPA_EDGCNTA_SHIFT   (8U)

Definition at line 31761 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPB_COUNT

#define PWM_CAPTCOMPB_COUNT   (4U)

Definition at line 31864 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPB_EDGCMPB

#define PWM_CAPTCOMPB_EDGCMPB (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)

EDGCMPB - Edge Compare B

Definition at line 31855 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPB_EDGCMPB_MASK

#define PWM_CAPTCOMPB_EDGCMPB_MASK   (0xFFU)

Definition at line 31851 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPB_EDGCMPB_SHIFT

#define PWM_CAPTCOMPB_EDGCMPB_SHIFT   (0U)

Definition at line 31852 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPB_EDGCNTB

#define PWM_CAPTCOMPB_EDGCNTB (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)

EDGCNTB - Edge Counter B

Definition at line 31860 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPB_EDGCNTB_MASK

#define PWM_CAPTCOMPB_EDGCNTB_MASK   (0xFF00U)

Definition at line 31856 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPB_EDGCNTB_SHIFT

#define PWM_CAPTCOMPB_EDGCNTB_SHIFT   (8U)

Definition at line 31857 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPX_COUNT

#define PWM_CAPTCOMPX_COUNT   (4U)

Definition at line 31960 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPX_EDGCMPX

#define PWM_CAPTCOMPX_EDGCMPX (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)

EDGCMPX - Edge Compare X

Definition at line 31951 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPX_EDGCMPX_MASK

#define PWM_CAPTCOMPX_EDGCMPX_MASK   (0xFFU)

Definition at line 31947 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPX_EDGCMPX_SHIFT

#define PWM_CAPTCOMPX_EDGCMPX_SHIFT   (0U)

Definition at line 31948 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPX_EDGCNTX

#define PWM_CAPTCOMPX_EDGCNTX (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)

EDGCNTX - Edge Counter X

Definition at line 31956 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPX_EDGCNTX_MASK

#define PWM_CAPTCOMPX_EDGCNTX_MASK   (0xFF00U)

Definition at line 31952 of file MIMXRT1052.h.

◆ PWM_CAPTCOMPX_EDGCNTX_SHIFT

#define PWM_CAPTCOMPX_EDGCNTX_SHIFT   (8U)

Definition at line 31953 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_ARMA

#define PWM_CAPTCTRLA_ARMA (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)

ARMA - Arm A 0b0..Input capture operation is disabled. 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.

Definition at line 31682 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_ARMA_MASK

#define PWM_CAPTCTRLA_ARMA_MASK   (0x1U)

Definition at line 31676 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_ARMA_SHIFT

#define PWM_CAPTCTRLA_ARMA_SHIFT   (0U)

Definition at line 31677 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_CA0CNT

#define PWM_CAPTCTRLA_CA0CNT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)

CA0CNT - Capture A0 FIFO Word Count

Definition at line 31742 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_CA0CNT_MASK

#define PWM_CAPTCTRLA_CA0CNT_MASK   (0x1C00U)

Definition at line 31738 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_CA0CNT_SHIFT

#define PWM_CAPTCTRLA_CA0CNT_SHIFT   (10U)

Definition at line 31739 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_CA1CNT

#define PWM_CAPTCTRLA_CA1CNT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)

CA1CNT - Capture A1 FIFO Word Count

Definition at line 31747 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_CA1CNT_MASK

#define PWM_CAPTCTRLA_CA1CNT_MASK   (0xE000U)

Definition at line 31743 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_CA1CNT_SHIFT

#define PWM_CAPTCTRLA_CA1CNT_SHIFT   (13U)

Definition at line 31744 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_CFAWM

#define PWM_CAPTCTRLA_CFAWM (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)

CFAWM - Capture A FIFOs Water Mark

Definition at line 31737 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_CFAWM_MASK

#define PWM_CAPTCTRLA_CFAWM_MASK   (0x300U)

Definition at line 31733 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_CFAWM_SHIFT

#define PWM_CAPTCTRLA_CFAWM_SHIFT   (8U)

Definition at line 31734 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_COUNT

#define PWM_CAPTCTRLA_COUNT   (4U)

Definition at line 31751 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_EDGA0

#define PWM_CAPTCTRLA_EDGA0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)

EDGA0 - Edge A 0 0b00..Disabled 0b01..Capture falling edges 0b10..Capture rising edges 0b11..Capture any edge

Definition at line 31706 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_EDGA0_MASK

#define PWM_CAPTCTRLA_EDGA0_MASK   (0xCU)

Definition at line 31698 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_EDGA0_SHIFT

#define PWM_CAPTCTRLA_EDGA0_SHIFT   (2U)

Definition at line 31699 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_EDGA1

#define PWM_CAPTCTRLA_EDGA1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)

EDGA1 - Edge A 1 0b00..Disabled 0b01..Capture falling edges 0b10..Capture rising edges 0b11..Capture any edge

Definition at line 31715 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_EDGA1_MASK

#define PWM_CAPTCTRLA_EDGA1_MASK   (0x30U)

Definition at line 31707 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_EDGA1_SHIFT

#define PWM_CAPTCTRLA_EDGA1_SHIFT   (4U)

Definition at line 31708 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_EDGCNTA_EN

#define PWM_CAPTCTRLA_EDGCNTA_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)

EDGCNTA_EN - Edge Counter A Enable 0b0..Edge counter disabled and held in reset 0b1..Edge counter enabled

Definition at line 31732 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_EDGCNTA_EN_MASK

#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK   (0x80U)

Definition at line 31726 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT

#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT   (7U)

Definition at line 31727 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_INP_SELA

#define PWM_CAPTCTRLA_INP_SELA (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)

INP_SELA - Input Select A 0b0..Raw PWM_A input signal selected as source. 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLA[EDGA0] and CAPTCTRLA[EDGA1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRA[EDGA0] and/or CAPTCTRLA[EDGA1] fields in order to enable one or both of the capture registers.

Definition at line 31725 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_INP_SELA_MASK

#define PWM_CAPTCTRLA_INP_SELA_MASK   (0x40U)

Definition at line 31716 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_INP_SELA_SHIFT

#define PWM_CAPTCTRLA_INP_SELA_SHIFT   (6U)

Definition at line 31717 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_ONESHOTA

#define PWM_CAPTCTRLA_ONESHOTA (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)

ONESHOTA - One Shot Mode A 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLA[ARMA] is cleared. No further captures will be performed until CAPTCTRLA[ARMA] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLA[ARMA] is then cleared.

Definition at line 31697 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_ONESHOTA_MASK

#define PWM_CAPTCTRLA_ONESHOTA_MASK   (0x2U)

Definition at line 31683 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLA_ONESHOTA_SHIFT

#define PWM_CAPTCTRLA_ONESHOTA_SHIFT   (1U)

Definition at line 31684 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_ARMB

#define PWM_CAPTCTRLB_ARMB (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)

ARMB - Arm B 0b0..Input capture operation is disabled. 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.

Definition at line 31778 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_ARMB_MASK

#define PWM_CAPTCTRLB_ARMB_MASK   (0x1U)

Definition at line 31772 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_ARMB_SHIFT

#define PWM_CAPTCTRLB_ARMB_SHIFT   (0U)

Definition at line 31773 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_CB0CNT

#define PWM_CAPTCTRLB_CB0CNT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)

CB0CNT - Capture B0 FIFO Word Count

Definition at line 31838 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_CB0CNT_MASK

#define PWM_CAPTCTRLB_CB0CNT_MASK   (0x1C00U)

Definition at line 31834 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_CB0CNT_SHIFT

#define PWM_CAPTCTRLB_CB0CNT_SHIFT   (10U)

Definition at line 31835 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_CB1CNT

#define PWM_CAPTCTRLB_CB1CNT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)

CB1CNT - Capture B1 FIFO Word Count

Definition at line 31843 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_CB1CNT_MASK

#define PWM_CAPTCTRLB_CB1CNT_MASK   (0xE000U)

Definition at line 31839 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_CB1CNT_SHIFT

#define PWM_CAPTCTRLB_CB1CNT_SHIFT   (13U)

Definition at line 31840 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_CFBWM

#define PWM_CAPTCTRLB_CFBWM (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)

CFBWM - Capture B FIFOs Water Mark

Definition at line 31833 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_CFBWM_MASK

#define PWM_CAPTCTRLB_CFBWM_MASK   (0x300U)

Definition at line 31829 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_CFBWM_SHIFT

#define PWM_CAPTCTRLB_CFBWM_SHIFT   (8U)

Definition at line 31830 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_COUNT

#define PWM_CAPTCTRLB_COUNT   (4U)

Definition at line 31847 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_EDGB0

#define PWM_CAPTCTRLB_EDGB0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)

EDGB0 - Edge B 0 0b00..Disabled 0b01..Capture falling edges 0b10..Capture rising edges 0b11..Capture any edge

Definition at line 31802 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_EDGB0_MASK

#define PWM_CAPTCTRLB_EDGB0_MASK   (0xCU)

Definition at line 31794 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_EDGB0_SHIFT

#define PWM_CAPTCTRLB_EDGB0_SHIFT   (2U)

Definition at line 31795 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_EDGB1

#define PWM_CAPTCTRLB_EDGB1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)

EDGB1 - Edge B 1 0b00..Disabled 0b01..Capture falling edges 0b10..Capture rising edges 0b11..Capture any edge

Definition at line 31811 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_EDGB1_MASK

#define PWM_CAPTCTRLB_EDGB1_MASK   (0x30U)

Definition at line 31803 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_EDGB1_SHIFT

#define PWM_CAPTCTRLB_EDGB1_SHIFT   (4U)

Definition at line 31804 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_EDGCNTB_EN

#define PWM_CAPTCTRLB_EDGCNTB_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)

EDGCNTB_EN - Edge Counter B Enable 0b0..Edge counter disabled and held in reset 0b1..Edge counter enabled

Definition at line 31828 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_EDGCNTB_EN_MASK

#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK   (0x80U)

Definition at line 31822 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT

#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT   (7U)

Definition at line 31823 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_INP_SELB

#define PWM_CAPTCTRLB_INP_SELB (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)

INP_SELB - Input Select B 0b0..Raw PWM_B input signal selected as source. 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLB[EDGB0] and CAPTCTRLB[EDGB1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRB[EDGB0] and/or CAPTCTRLB[EDGB1] fields in order to enable one or both of the capture registers.

Definition at line 31821 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_INP_SELB_MASK

#define PWM_CAPTCTRLB_INP_SELB_MASK   (0x40U)

Definition at line 31812 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_INP_SELB_SHIFT

#define PWM_CAPTCTRLB_INP_SELB_SHIFT   (6U)

Definition at line 31813 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_ONESHOTB

#define PWM_CAPTCTRLB_ONESHOTB (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)

ONESHOTB - One Shot Mode B 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLB[ARMB] is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and CAPTCTRLB[ARMB] is cleared. No further captures will be performed until CAPTCTRLB[ARMB] is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and CAPTCTRLB[ARMB] is then cleared.

Definition at line 31793 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_ONESHOTB_MASK

#define PWM_CAPTCTRLB_ONESHOTB_MASK   (0x2U)

Definition at line 31779 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLB_ONESHOTB_SHIFT

#define PWM_CAPTCTRLB_ONESHOTB_SHIFT   (1U)

Definition at line 31780 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_ARMX

#define PWM_CAPTCTRLX_ARMX (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)

ARMX - Arm X 0b0..Input capture operation is disabled. 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.

Definition at line 31874 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_ARMX_MASK

#define PWM_CAPTCTRLX_ARMX_MASK   (0x1U)

Definition at line 31868 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_ARMX_SHIFT

#define PWM_CAPTCTRLX_ARMX_SHIFT   (0U)

Definition at line 31869 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_CFXWM

#define PWM_CAPTCTRLX_CFXWM (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)

CFXWM - Capture X FIFOs Water Mark

Definition at line 31929 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_CFXWM_MASK

#define PWM_CAPTCTRLX_CFXWM_MASK   (0x300U)

Definition at line 31925 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_CFXWM_SHIFT

#define PWM_CAPTCTRLX_CFXWM_SHIFT   (8U)

Definition at line 31926 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_COUNT

#define PWM_CAPTCTRLX_COUNT   (4U)

Definition at line 31943 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_CX0CNT

#define PWM_CAPTCTRLX_CX0CNT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)

CX0CNT - Capture X0 FIFO Word Count

Definition at line 31934 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_CX0CNT_MASK

#define PWM_CAPTCTRLX_CX0CNT_MASK   (0x1C00U)

Definition at line 31930 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_CX0CNT_SHIFT

#define PWM_CAPTCTRLX_CX0CNT_SHIFT   (10U)

Definition at line 31931 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_CX1CNT

#define PWM_CAPTCTRLX_CX1CNT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)

CX1CNT - Capture X1 FIFO Word Count

Definition at line 31939 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_CX1CNT_MASK

#define PWM_CAPTCTRLX_CX1CNT_MASK   (0xE000U)

Definition at line 31935 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_CX1CNT_SHIFT

#define PWM_CAPTCTRLX_CX1CNT_SHIFT   (13U)

Definition at line 31936 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_EDGCNTX_EN

#define PWM_CAPTCTRLX_EDGCNTX_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)

EDGCNTX_EN - Edge Counter X Enable 0b0..Edge counter disabled and held in reset 0b1..Edge counter enabled

Definition at line 31924 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_EDGCNTX_EN_MASK

#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK   (0x80U)

Definition at line 31918 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT

#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT   (7U)

Definition at line 31919 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_EDGX0

#define PWM_CAPTCTRLX_EDGX0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)

EDGX0 - Edge X 0 0b00..Disabled 0b01..Capture falling edges 0b10..Capture rising edges 0b11..Capture any edge

Definition at line 31898 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_EDGX0_MASK

#define PWM_CAPTCTRLX_EDGX0_MASK   (0xCU)

Definition at line 31890 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_EDGX0_SHIFT

#define PWM_CAPTCTRLX_EDGX0_SHIFT   (2U)

Definition at line 31891 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_EDGX1

#define PWM_CAPTCTRLX_EDGX1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)

EDGX1 - Edge X 1 0b00..Disabled 0b01..Capture falling edges 0b10..Capture rising edges 0b11..Capture any edge

Definition at line 31907 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_EDGX1_MASK

#define PWM_CAPTCTRLX_EDGX1_MASK   (0x30U)

Definition at line 31899 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_EDGX1_SHIFT

#define PWM_CAPTCTRLX_EDGX1_SHIFT   (4U)

Definition at line 31900 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_INP_SELX

#define PWM_CAPTCTRLX_INP_SELX (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)

INP_SELX - Input Select X 0b0..Raw PWM_X input signal selected as source. 0b1..Output of edge counter/compare selected as source. Note that when this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored. The software must still place a value other than 00 in either or both of the CAPTCTLRX[EDGX0] and/or CAPTCTRLX[EDGX1] fields in order to enable one or both of the capture registers.

Definition at line 31917 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_INP_SELX_MASK

#define PWM_CAPTCTRLX_INP_SELX_MASK   (0x40U)

Definition at line 31908 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_INP_SELX_SHIFT

#define PWM_CAPTCTRLX_INP_SELX_SHIFT   (6U)

Definition at line 31909 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_ONESHOTX

#define PWM_CAPTCTRLX_ONESHOTX (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)

ONESHOTX - One Shot Mode Aux 0b0..Free running mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and capture circuit 0 is re-armed. The process continues indefinitely.If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. 0b1..One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after the ARMX bit is set. Once a capture occurs, capture circuit 0 is disarmed and capture circuit 1 is armed. After capture circuit 1 performs a capture, it is disarmed and the ARMX bit is cleared. No further captures will be performed until the ARMX bit is set again.If only one of the capture circuits is enabled, then a single capture will occur on the enabled capture circuit and the ARMX bit is then cleared.

Definition at line 31889 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_ONESHOTX_MASK

#define PWM_CAPTCTRLX_ONESHOTX_MASK   (0x2U)

Definition at line 31875 of file MIMXRT1052.h.

◆ PWM_CAPTCTRLX_ONESHOTX_SHIFT

#define PWM_CAPTCTRLX_ONESHOTX_SHIFT   (1U)

Definition at line 31876 of file MIMXRT1052.h.

◆ PWM_CNT_CNT

#define PWM_CNT_CNT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)

CNT - Counter Register Bits

Definition at line 30918 of file MIMXRT1052.h.

◆ PWM_CNT_CNT_MASK

#define PWM_CNT_CNT_MASK   (0xFFFFU)

Definition at line 30914 of file MIMXRT1052.h.

◆ PWM_CNT_CNT_SHIFT

#define PWM_CNT_CNT_SHIFT   (0U)

Definition at line 30915 of file MIMXRT1052.h.

◆ PWM_CNT_COUNT

#define PWM_CNT_COUNT   (4U)

Definition at line 30922 of file MIMXRT1052.h.

◆ PWM_CTRL2_CLK_SEL

#define PWM_CTRL2_CLK_SEL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)

CLK_SEL - Clock Source Select 0b00..The IPBus clock is used as the clock for the local prescaler and counter. 0b01..EXT_CLK is used as the clock for the local prescaler and counter. 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This setting should not be used in submodule 0 as it will force the clock to logic 0. 0b11..reserved

Definition at line 30947 of file MIMXRT1052.h.

◆ PWM_CTRL2_CLK_SEL_MASK

#define PWM_CTRL2_CLK_SEL_MASK   (0x3U)

Definition at line 30938 of file MIMXRT1052.h.

◆ PWM_CTRL2_CLK_SEL_SHIFT

#define PWM_CTRL2_CLK_SEL_SHIFT   (0U)

Definition at line 30939 of file MIMXRT1052.h.

◆ PWM_CTRL2_COUNT

#define PWM_CTRL2_COUNT   (4U)

Definition at line 31031 of file MIMXRT1052.h.

◆ PWM_CTRL2_DBGEN

#define PWM_CTRL2_DBGEN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)

DBGEN - Debug Enable

Definition at line 31027 of file MIMXRT1052.h.

◆ PWM_CTRL2_DBGEN_MASK

#define PWM_CTRL2_DBGEN_MASK   (0x8000U)

Definition at line 31023 of file MIMXRT1052.h.

◆ PWM_CTRL2_DBGEN_SHIFT

#define PWM_CTRL2_DBGEN_SHIFT   (15U)

Definition at line 31024 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE

#define PWM_CTRL2_FORCE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)

FORCE - Force Initialization

Definition at line 30976 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_MASK

#define PWM_CTRL2_FORCE_MASK   (0x40U)

Definition at line 30972 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_SEL

#define PWM_CTRL2_FORCE_SEL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)

FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates. 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in submodule 0 as it will hold the FORCE OUTPUT signal to logic 0. 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK. 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b100..The local sync signal from this submodule is used to force updates. 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0. 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates. 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.

Definition at line 30971 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_SEL_MASK

#define PWM_CTRL2_FORCE_SEL_MASK   (0x38U)

Definition at line 30956 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_SEL_SHIFT

#define PWM_CTRL2_FORCE_SEL_SHIFT   (3U)

Definition at line 30957 of file MIMXRT1052.h.

◆ PWM_CTRL2_FORCE_SHIFT

#define PWM_CTRL2_FORCE_SHIFT   (6U)

Definition at line 30973 of file MIMXRT1052.h.

◆ PWM_CTRL2_FRCEN

#define PWM_CTRL2_FRCEN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)

FRCEN - FRCEN 0b0..Initialization from a FORCE_OUT is disabled. 0b1..Initialization from a FORCE_OUT is enabled.

Definition at line 30983 of file MIMXRT1052.h.

◆ PWM_CTRL2_FRCEN_MASK

#define PWM_CTRL2_FRCEN_MASK   (0x80U)

Definition at line 30977 of file MIMXRT1052.h.

◆ PWM_CTRL2_FRCEN_SHIFT

#define PWM_CTRL2_FRCEN_SHIFT   (7U)

Definition at line 30978 of file MIMXRT1052.h.

◆ PWM_CTRL2_INDEP

#define PWM_CTRL2_INDEP (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)

INDEP - Independent or Complementary Pair Operation 0b0..PWM_A and PWM_B form a complementary PWM pair. 0b1..PWM_A and PWM_B outputs are independent PWMs.

Definition at line 31017 of file MIMXRT1052.h.

◆ PWM_CTRL2_INDEP_MASK

#define PWM_CTRL2_INDEP_MASK   (0x2000U)

Definition at line 31011 of file MIMXRT1052.h.

◆ PWM_CTRL2_INDEP_SHIFT

#define PWM_CTRL2_INDEP_SHIFT   (13U)

Definition at line 31012 of file MIMXRT1052.h.

◆ PWM_CTRL2_INIT_SEL

#define PWM_CTRL2_INIT_SEL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)

INIT_SEL - Initialization Control Select 0b00..Local sync (PWM_X) causes initialization. 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master reload occurs. 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it will force the INIT signal to logic 0. 0b11..EXT_SYNC causes initialization.

Definition at line 30995 of file MIMXRT1052.h.

◆ PWM_CTRL2_INIT_SEL_MASK

#define PWM_CTRL2_INIT_SEL_MASK   (0x300U)

Definition at line 30984 of file MIMXRT1052.h.

◆ PWM_CTRL2_INIT_SEL_SHIFT

#define PWM_CTRL2_INIT_SEL_SHIFT   (8U)

Definition at line 30985 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM23_INIT

#define PWM_CTRL2_PWM23_INIT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)

PWM23_INIT - PWM23 Initial Value

Definition at line 31010 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM23_INIT_MASK

#define PWM_CTRL2_PWM23_INIT_MASK   (0x1000U)

Definition at line 31006 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM23_INIT_SHIFT

#define PWM_CTRL2_PWM23_INIT_SHIFT   (12U)

Definition at line 31007 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM45_INIT

#define PWM_CTRL2_PWM45_INIT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)

PWM45_INIT - PWM45 Initial Value

Definition at line 31005 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM45_INIT_MASK

#define PWM_CTRL2_PWM45_INIT_MASK   (0x800U)

Definition at line 31001 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWM45_INIT_SHIFT

#define PWM_CTRL2_PWM45_INIT_SHIFT   (11U)

Definition at line 31002 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWMX_INIT

#define PWM_CTRL2_PWMX_INIT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)

PWMX_INIT - PWM_X Initial Value

Definition at line 31000 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWMX_INIT_MASK

#define PWM_CTRL2_PWMX_INIT_MASK   (0x400U)

Definition at line 30996 of file MIMXRT1052.h.

◆ PWM_CTRL2_PWMX_INIT_SHIFT

#define PWM_CTRL2_PWMX_INIT_SHIFT   (10U)

Definition at line 30997 of file MIMXRT1052.h.

◆ PWM_CTRL2_RELOAD_SEL

#define PWM_CTRL2_RELOAD_SEL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)

RELOAD_SEL - Reload Source Select 0b0..The local RELOAD signal is used to reload registers. 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used in submodule 0 as it will force the RELOAD signal to logic 0.

Definition at line 30955 of file MIMXRT1052.h.

◆ PWM_CTRL2_RELOAD_SEL_MASK

#define PWM_CTRL2_RELOAD_SEL_MASK   (0x4U)

Definition at line 30948 of file MIMXRT1052.h.

◆ PWM_CTRL2_RELOAD_SEL_SHIFT

#define PWM_CTRL2_RELOAD_SEL_SHIFT   (2U)

Definition at line 30949 of file MIMXRT1052.h.

◆ PWM_CTRL2_WAITEN

#define PWM_CTRL2_WAITEN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)

WAITEN - WAIT Enable

Definition at line 31022 of file MIMXRT1052.h.

◆ PWM_CTRL2_WAITEN_MASK

#define PWM_CTRL2_WAITEN_MASK   (0x4000U)

Definition at line 31018 of file MIMXRT1052.h.

◆ PWM_CTRL2_WAITEN_SHIFT

#define PWM_CTRL2_WAITEN_SHIFT   (14U)

Definition at line 31019 of file MIMXRT1052.h.

◆ PWM_CTRL_COMPMODE

#define PWM_CTRL_COMPMODE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)

COMPMODE - Compare Mode 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.

Definition at line 31089 of file MIMXRT1052.h.

◆ PWM_CTRL_COMPMODE_MASK

#define PWM_CTRL_COMPMODE_MASK   (0x80U)

Definition at line 31077 of file MIMXRT1052.h.

◆ PWM_CTRL_COMPMODE_SHIFT

#define PWM_CTRL_COMPMODE_SHIFT   (7U)

Definition at line 31078 of file MIMXRT1052.h.

◆ PWM_CTRL_COUNT

#define PWM_CTRL_COUNT   (4U)

Definition at line 31133 of file MIMXRT1052.h.

◆ PWM_CTRL_DBLEN

#define PWM_CTRL_DBLEN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

DBLEN - Double Switching Enable 0b0..Double switching disabled. 0b1..Double switching enabled.

Definition at line 31041 of file MIMXRT1052.h.

◆ PWM_CTRL_DBLEN_MASK

#define PWM_CTRL_DBLEN_MASK   (0x1U)

Definition at line 31035 of file MIMXRT1052.h.

◆ PWM_CTRL_DBLEN_SHIFT

#define PWM_CTRL_DBLEN_SHIFT   (0U)

Definition at line 31036 of file MIMXRT1052.h.

◆ PWM_CTRL_DBLX

#define PWM_CTRL_DBLX (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

DBLX - PWMX Double Switching Enable 0b0..PWMX double pulse disabled. 0b1..PWMX double pulse enabled.

Definition at line 31048 of file MIMXRT1052.h.

◆ PWM_CTRL_DBLX_MASK

#define PWM_CTRL_DBLX_MASK   (0x2U)

Definition at line 31042 of file MIMXRT1052.h.

◆ PWM_CTRL_DBLX_SHIFT

#define PWM_CTRL_DBLX_SHIFT   (1U)

Definition at line 31043 of file MIMXRT1052.h.

◆ PWM_CTRL_DT

#define PWM_CTRL_DT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)

DT - Deadtime

Definition at line 31094 of file MIMXRT1052.h.

◆ PWM_CTRL_DT_MASK

#define PWM_CTRL_DT_MASK   (0x300U)

Definition at line 31090 of file MIMXRT1052.h.

◆ PWM_CTRL_DT_SHIFT

#define PWM_CTRL_DT_SHIFT   (8U)

Definition at line 31091 of file MIMXRT1052.h.

◆ PWM_CTRL_FULL

#define PWM_CTRL_FULL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

FULL - Full Cycle Reload 0b0..Full-cycle reloads disabled. 0b1..Full-cycle reloads enabled.

Definition at line 31101 of file MIMXRT1052.h.

◆ PWM_CTRL_FULL_MASK

#define PWM_CTRL_FULL_MASK   (0x400U)

Definition at line 31095 of file MIMXRT1052.h.

◆ PWM_CTRL_FULL_SHIFT

#define PWM_CTRL_FULL_SHIFT   (10U)

Definition at line 31096 of file MIMXRT1052.h.

◆ PWM_CTRL_HALF

#define PWM_CTRL_HALF (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

HALF - Half Cycle Reload 0b0..Half-cycle reloads disabled. 0b1..Half-cycle reloads enabled.

Definition at line 31108 of file MIMXRT1052.h.

◆ PWM_CTRL_HALF_MASK

#define PWM_CTRL_HALF_MASK   (0x800U)

Definition at line 31102 of file MIMXRT1052.h.

◆ PWM_CTRL_HALF_SHIFT

#define PWM_CTRL_HALF_SHIFT   (11U)

Definition at line 31103 of file MIMXRT1052.h.

◆ PWM_CTRL_LDFQ

#define PWM_CTRL_LDFQ (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

LDFQ - Load Frequency 0b0000..Every PWM opportunity 0b0001..Every 2 PWM opportunities 0b0010..Every 3 PWM opportunities 0b0011..Every 4 PWM opportunities 0b0100..Every 5 PWM opportunities 0b0101..Every 6 PWM opportunities 0b0110..Every 7 PWM opportunities 0b0111..Every 8 PWM opportunities 0b1000..Every 9 PWM opportunities 0b1001..Every 10 PWM opportunities 0b1010..Every 11 PWM opportunities 0b1011..Every 12 PWM opportunities 0b1100..Every 13 PWM opportunities 0b1101..Every 14 PWM opportunities 0b1110..Every 15 PWM opportunities 0b1111..Every 16 PWM opportunities

Definition at line 31129 of file MIMXRT1052.h.

◆ PWM_CTRL_LDFQ_MASK

#define PWM_CTRL_LDFQ_MASK   (0xF000U)

Definition at line 31109 of file MIMXRT1052.h.

◆ PWM_CTRL_LDFQ_SHIFT

#define PWM_CTRL_LDFQ_SHIFT   (12U)

Definition at line 31110 of file MIMXRT1052.h.

◆ PWM_CTRL_LDMOD

#define PWM_CTRL_LDMOD (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

LDMOD - Load Mode Select 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].

Definition at line 31056 of file MIMXRT1052.h.

◆ PWM_CTRL_LDMOD_MASK

#define PWM_CTRL_LDMOD_MASK   (0x4U)

Definition at line 31049 of file MIMXRT1052.h.

◆ PWM_CTRL_LDMOD_SHIFT

#define PWM_CTRL_LDMOD_SHIFT   (2U)

Definition at line 31050 of file MIMXRT1052.h.

◆ PWM_CTRL_PRSC

#define PWM_CTRL_PRSC (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

PRSC - Prescaler 0b000..PWM clock frequency = fclk 0b001..PWM clock frequency = fclk/2 0b010..PWM clock frequency = fclk/4 0b011..PWM clock frequency = fclk/8 0b100..PWM clock frequency = fclk/16 0b101..PWM clock frequency = fclk/32 0b110..PWM clock frequency = fclk/64 0b111..PWM clock frequency = fclk/128

Definition at line 31076 of file MIMXRT1052.h.

◆ PWM_CTRL_PRSC_MASK

#define PWM_CTRL_PRSC_MASK   (0x70U)

Definition at line 31064 of file MIMXRT1052.h.

◆ PWM_CTRL_PRSC_SHIFT

#define PWM_CTRL_PRSC_SHIFT   (4U)

Definition at line 31065 of file MIMXRT1052.h.

◆ PWM_CTRL_SPLIT

#define PWM_CTRL_SPLIT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)

SPLIT - Split the DBLPWM signal to PWMA and PWMB 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. 0b1..DBLPWM is split to PWMA and PWMB.

Definition at line 31063 of file MIMXRT1052.h.

◆ PWM_CTRL_SPLIT_MASK

#define PWM_CTRL_SPLIT_MASK   (0x8U)

Definition at line 31057 of file MIMXRT1052.h.

◆ PWM_CTRL_SPLIT_SHIFT

#define PWM_CTRL_SPLIT_SHIFT   (3U)

Definition at line 31058 of file MIMXRT1052.h.

◆ PWM_CVAL0_CAPTVAL0

#define PWM_CVAL0_CAPTVAL0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)

CAPTVAL0 - CAPTVAL0

Definition at line 31968 of file MIMXRT1052.h.

◆ PWM_CVAL0_CAPTVAL0_MASK

#define PWM_CVAL0_CAPTVAL0_MASK   (0xFFFFU)

Definition at line 31964 of file MIMXRT1052.h.

◆ PWM_CVAL0_CAPTVAL0_SHIFT

#define PWM_CVAL0_CAPTVAL0_SHIFT   (0U)

Definition at line 31965 of file MIMXRT1052.h.

◆ PWM_CVAL0_COUNT

#define PWM_CVAL0_COUNT   (4U)

Definition at line 31972 of file MIMXRT1052.h.

◆ PWM_CVAL0CYC_COUNT

#define PWM_CVAL0CYC_COUNT   (4U)

Definition at line 31984 of file MIMXRT1052.h.

◆ PWM_CVAL0CYC_CVAL0CYC

#define PWM_CVAL0CYC_CVAL0CYC (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)

CVAL0CYC - CVAL0CYC

Definition at line 31980 of file MIMXRT1052.h.

◆ PWM_CVAL0CYC_CVAL0CYC_MASK

#define PWM_CVAL0CYC_CVAL0CYC_MASK   (0xFU)

Definition at line 31976 of file MIMXRT1052.h.

◆ PWM_CVAL0CYC_CVAL0CYC_SHIFT

#define PWM_CVAL0CYC_CVAL0CYC_SHIFT   (0U)

Definition at line 31977 of file MIMXRT1052.h.

◆ PWM_CVAL1_CAPTVAL1

#define PWM_CVAL1_CAPTVAL1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)

CAPTVAL1 - CAPTVAL1

Definition at line 31992 of file MIMXRT1052.h.

◆ PWM_CVAL1_CAPTVAL1_MASK

#define PWM_CVAL1_CAPTVAL1_MASK   (0xFFFFU)

Definition at line 31988 of file MIMXRT1052.h.

◆ PWM_CVAL1_CAPTVAL1_SHIFT

#define PWM_CVAL1_CAPTVAL1_SHIFT   (0U)

Definition at line 31989 of file MIMXRT1052.h.

◆ PWM_CVAL1_COUNT

#define PWM_CVAL1_COUNT   (4U)

Definition at line 31996 of file MIMXRT1052.h.

◆ PWM_CVAL1CYC_COUNT

#define PWM_CVAL1CYC_COUNT   (4U)

Definition at line 32008 of file MIMXRT1052.h.

◆ PWM_CVAL1CYC_CVAL1CYC

#define PWM_CVAL1CYC_CVAL1CYC (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)

CVAL1CYC - CVAL1CYC

Definition at line 32004 of file MIMXRT1052.h.

◆ PWM_CVAL1CYC_CVAL1CYC_MASK

#define PWM_CVAL1CYC_CVAL1CYC_MASK   (0xFU)

Definition at line 32000 of file MIMXRT1052.h.

◆ PWM_CVAL1CYC_CVAL1CYC_SHIFT

#define PWM_CVAL1CYC_CVAL1CYC_SHIFT   (0U)

Definition at line 32001 of file MIMXRT1052.h.

◆ PWM_CVAL2_CAPTVAL2

#define PWM_CVAL2_CAPTVAL2 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)

CAPTVAL2 - CAPTVAL2

Definition at line 32016 of file MIMXRT1052.h.

◆ PWM_CVAL2_CAPTVAL2_MASK

#define PWM_CVAL2_CAPTVAL2_MASK   (0xFFFFU)

Definition at line 32012 of file MIMXRT1052.h.

◆ PWM_CVAL2_CAPTVAL2_SHIFT

#define PWM_CVAL2_CAPTVAL2_SHIFT   (0U)

Definition at line 32013 of file MIMXRT1052.h.

◆ PWM_CVAL2_COUNT

#define PWM_CVAL2_COUNT   (4U)

Definition at line 32020 of file MIMXRT1052.h.

◆ PWM_CVAL2CYC_COUNT

#define PWM_CVAL2CYC_COUNT   (4U)

Definition at line 32032 of file MIMXRT1052.h.

◆ PWM_CVAL2CYC_CVAL2CYC

#define PWM_CVAL2CYC_CVAL2CYC (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)

CVAL2CYC - CVAL2CYC

Definition at line 32028 of file MIMXRT1052.h.

◆ PWM_CVAL2CYC_CVAL2CYC_MASK

#define PWM_CVAL2CYC_CVAL2CYC_MASK   (0xFU)

Definition at line 32024 of file MIMXRT1052.h.

◆ PWM_CVAL2CYC_CVAL2CYC_SHIFT

#define PWM_CVAL2CYC_CVAL2CYC_SHIFT   (0U)

Definition at line 32025 of file MIMXRT1052.h.

◆ PWM_CVAL3_CAPTVAL3

#define PWM_CVAL3_CAPTVAL3 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)

CAPTVAL3 - CAPTVAL3

Definition at line 32040 of file MIMXRT1052.h.

◆ PWM_CVAL3_CAPTVAL3_MASK

#define PWM_CVAL3_CAPTVAL3_MASK   (0xFFFFU)

Definition at line 32036 of file MIMXRT1052.h.

◆ PWM_CVAL3_CAPTVAL3_SHIFT

#define PWM_CVAL3_CAPTVAL3_SHIFT   (0U)

Definition at line 32037 of file MIMXRT1052.h.

◆ PWM_CVAL3_COUNT

#define PWM_CVAL3_COUNT   (4U)

Definition at line 32044 of file MIMXRT1052.h.

◆ PWM_CVAL3CYC_COUNT

#define PWM_CVAL3CYC_COUNT   (4U)

Definition at line 32056 of file MIMXRT1052.h.

◆ PWM_CVAL3CYC_CVAL3CYC

#define PWM_CVAL3CYC_CVAL3CYC (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)

CVAL3CYC - CVAL3CYC

Definition at line 32052 of file MIMXRT1052.h.

◆ PWM_CVAL3CYC_CVAL3CYC_MASK

#define PWM_CVAL3CYC_CVAL3CYC_MASK   (0xFU)

Definition at line 32048 of file MIMXRT1052.h.

◆ PWM_CVAL3CYC_CVAL3CYC_SHIFT

#define PWM_CVAL3CYC_CVAL3CYC_SHIFT   (0U)

Definition at line 32049 of file MIMXRT1052.h.

◆ PWM_CVAL4_CAPTVAL4

#define PWM_CVAL4_CAPTVAL4 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)

CAPTVAL4 - CAPTVAL4

Definition at line 32064 of file MIMXRT1052.h.

◆ PWM_CVAL4_CAPTVAL4_MASK

#define PWM_CVAL4_CAPTVAL4_MASK   (0xFFFFU)

Definition at line 32060 of file MIMXRT1052.h.

◆ PWM_CVAL4_CAPTVAL4_SHIFT

#define PWM_CVAL4_CAPTVAL4_SHIFT   (0U)

Definition at line 32061 of file MIMXRT1052.h.

◆ PWM_CVAL4_COUNT

#define PWM_CVAL4_COUNT   (4U)

Definition at line 32068 of file MIMXRT1052.h.

◆ PWM_CVAL4CYC_COUNT

#define PWM_CVAL4CYC_COUNT   (4U)

Definition at line 32080 of file MIMXRT1052.h.

◆ PWM_CVAL4CYC_CVAL4CYC

#define PWM_CVAL4CYC_CVAL4CYC (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)

CVAL4CYC - CVAL4CYC

Definition at line 32076 of file MIMXRT1052.h.

◆ PWM_CVAL4CYC_CVAL4CYC_MASK

#define PWM_CVAL4CYC_CVAL4CYC_MASK   (0xFU)

Definition at line 32072 of file MIMXRT1052.h.

◆ PWM_CVAL4CYC_CVAL4CYC_SHIFT

#define PWM_CVAL4CYC_CVAL4CYC_SHIFT   (0U)

Definition at line 32073 of file MIMXRT1052.h.

◆ PWM_CVAL5_CAPTVAL5

#define PWM_CVAL5_CAPTVAL5 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)

CAPTVAL5 - CAPTVAL5

Definition at line 32088 of file MIMXRT1052.h.

◆ PWM_CVAL5_CAPTVAL5_MASK

#define PWM_CVAL5_CAPTVAL5_MASK   (0xFFFFU)

Definition at line 32084 of file MIMXRT1052.h.

◆ PWM_CVAL5_CAPTVAL5_SHIFT

#define PWM_CVAL5_CAPTVAL5_SHIFT   (0U)

Definition at line 32085 of file MIMXRT1052.h.

◆ PWM_CVAL5_COUNT

#define PWM_CVAL5_COUNT   (4U)

Definition at line 32092 of file MIMXRT1052.h.

◆ PWM_CVAL5CYC_COUNT

#define PWM_CVAL5CYC_COUNT   (4U)

Definition at line 32104 of file MIMXRT1052.h.

◆ PWM_CVAL5CYC_CVAL5CYC

#define PWM_CVAL5CYC_CVAL5CYC (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)

CVAL5CYC - CVAL5CYC

Definition at line 32100 of file MIMXRT1052.h.

◆ PWM_CVAL5CYC_CVAL5CYC_MASK

#define PWM_CVAL5CYC_CVAL5CYC_MASK   (0xFU)

Definition at line 32096 of file MIMXRT1052.h.

◆ PWM_CVAL5CYC_CVAL5CYC_SHIFT

#define PWM_CVAL5CYC_CVAL5CYC_SHIFT   (0U)

Definition at line 32097 of file MIMXRT1052.h.

◆ PWM_DISMAP_COUNT

#define PWM_DISMAP_COUNT   (4U)

Definition at line 31645 of file MIMXRT1052.h.

◆ PWM_DISMAP_COUNT2

#define PWM_DISMAP_COUNT2   (2U)

Definition at line 31648 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS0A

#define PWM_DISMAP_DIS0A (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)

DIS0A - PWM_A Fault Disable Mask 0

Definition at line 31616 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS0A_MASK

#define PWM_DISMAP_DIS0A_MASK   (0xFU)

Definition at line 31612 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS0A_SHIFT

#define PWM_DISMAP_DIS0A_SHIFT   (0U)

Definition at line 31613 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS0B

#define PWM_DISMAP_DIS0B (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)

DIS0B - PWM_B Fault Disable Mask 0

Definition at line 31626 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS0B_MASK

#define PWM_DISMAP_DIS0B_MASK   (0xF0U)

Definition at line 31622 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS0B_SHIFT

#define PWM_DISMAP_DIS0B_SHIFT   (4U)

Definition at line 31623 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS0X

#define PWM_DISMAP_DIS0X (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)

DIS0X - PWM_X Fault Disable Mask 0

Definition at line 31636 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS0X_MASK

#define PWM_DISMAP_DIS0X_MASK   (0xF00U)

Definition at line 31632 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS0X_SHIFT

#define PWM_DISMAP_DIS0X_SHIFT   (8U)

Definition at line 31633 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS1A

#define PWM_DISMAP_DIS1A (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK)

DIS1A - PWM_A Fault Disable Mask 1

Definition at line 31621 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS1A_MASK

#define PWM_DISMAP_DIS1A_MASK   (0xFU)

Definition at line 31617 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS1A_SHIFT

#define PWM_DISMAP_DIS1A_SHIFT   (0U)

Definition at line 31618 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS1B

#define PWM_DISMAP_DIS1B (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK)

DIS1B - PWM_B Fault Disable Mask 1

Definition at line 31631 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS1B_MASK

#define PWM_DISMAP_DIS1B_MASK   (0xF0U)

Definition at line 31627 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS1B_SHIFT

#define PWM_DISMAP_DIS1B_SHIFT   (4U)

Definition at line 31628 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS1X

#define PWM_DISMAP_DIS1X (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK)

DIS1X - PWM_X Fault Disable Mask 1

Definition at line 31641 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS1X_MASK

#define PWM_DISMAP_DIS1X_MASK   (0xF00U)

Definition at line 31637 of file MIMXRT1052.h.

◆ PWM_DISMAP_DIS1X_SHIFT

#define PWM_DISMAP_DIS1X_SHIFT   (8U)

Definition at line 31638 of file MIMXRT1052.h.

◆ PWM_DMAEN_CA0DE

#define PWM_DMAEN_CA0DE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)

CA0DE - Capture A0 FIFO DMA Enable

Definition at line 31538 of file MIMXRT1052.h.

◆ PWM_DMAEN_CA0DE_MASK

#define PWM_DMAEN_CA0DE_MASK   (0x10U)

Definition at line 31534 of file MIMXRT1052.h.

◆ PWM_DMAEN_CA0DE_SHIFT

#define PWM_DMAEN_CA0DE_SHIFT   (4U)

Definition at line 31535 of file MIMXRT1052.h.

◆ PWM_DMAEN_CA1DE

#define PWM_DMAEN_CA1DE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)

CA1DE - Capture A1 FIFO DMA Enable

Definition at line 31543 of file MIMXRT1052.h.

◆ PWM_DMAEN_CA1DE_MASK

#define PWM_DMAEN_CA1DE_MASK   (0x20U)

Definition at line 31539 of file MIMXRT1052.h.

◆ PWM_DMAEN_CA1DE_SHIFT

#define PWM_DMAEN_CA1DE_SHIFT   (5U)

Definition at line 31540 of file MIMXRT1052.h.

◆ PWM_DMAEN_CAPTDE

#define PWM_DMAEN_CAPTDE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)

CAPTDE - Capture DMA Enable Source Select 0b00..Read DMA requests disabled. 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE], DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to which watermark(s) the DMA request is sensitive. 0b10..A local sync (VAL1 matches counter) sets the read DMA request. 0b11..A local reload (STS[RF] being set) sets the read DMA request.

Definition at line 31554 of file MIMXRT1052.h.

◆ PWM_DMAEN_CAPTDE_MASK

#define PWM_DMAEN_CAPTDE_MASK   (0xC0U)

Definition at line 31544 of file MIMXRT1052.h.

◆ PWM_DMAEN_CAPTDE_SHIFT

#define PWM_DMAEN_CAPTDE_SHIFT   (6U)

Definition at line 31545 of file MIMXRT1052.h.

◆ PWM_DMAEN_CB0DE

#define PWM_DMAEN_CB0DE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)

CB0DE - Capture B0 FIFO DMA Enable

Definition at line 31528 of file MIMXRT1052.h.

◆ PWM_DMAEN_CB0DE_MASK

#define PWM_DMAEN_CB0DE_MASK   (0x4U)

Definition at line 31524 of file MIMXRT1052.h.

◆ PWM_DMAEN_CB0DE_SHIFT

#define PWM_DMAEN_CB0DE_SHIFT   (2U)

Definition at line 31525 of file MIMXRT1052.h.

◆ PWM_DMAEN_CB1DE

#define PWM_DMAEN_CB1DE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)

CB1DE - Capture B1 FIFO DMA Enable

Definition at line 31533 of file MIMXRT1052.h.

◆ PWM_DMAEN_CB1DE_MASK

#define PWM_DMAEN_CB1DE_MASK   (0x8U)

Definition at line 31529 of file MIMXRT1052.h.

◆ PWM_DMAEN_CB1DE_SHIFT

#define PWM_DMAEN_CB1DE_SHIFT   (3U)

Definition at line 31530 of file MIMXRT1052.h.

◆ PWM_DMAEN_COUNT

#define PWM_DMAEN_COUNT   (4U)

Definition at line 31572 of file MIMXRT1052.h.

◆ PWM_DMAEN_CX0DE

#define PWM_DMAEN_CX0DE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)

CX0DE - Capture X0 FIFO DMA Enable

Definition at line 31518 of file MIMXRT1052.h.

◆ PWM_DMAEN_CX0DE_MASK

#define PWM_DMAEN_CX0DE_MASK   (0x1U)

Definition at line 31514 of file MIMXRT1052.h.

◆ PWM_DMAEN_CX0DE_SHIFT

#define PWM_DMAEN_CX0DE_SHIFT   (0U)

Definition at line 31515 of file MIMXRT1052.h.

◆ PWM_DMAEN_CX1DE

#define PWM_DMAEN_CX1DE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)

CX1DE - Capture X1 FIFO DMA Enable

Definition at line 31523 of file MIMXRT1052.h.

◆ PWM_DMAEN_CX1DE_MASK

#define PWM_DMAEN_CX1DE_MASK   (0x2U)

Definition at line 31519 of file MIMXRT1052.h.

◆ PWM_DMAEN_CX1DE_SHIFT

#define PWM_DMAEN_CX1DE_SHIFT   (1U)

Definition at line 31520 of file MIMXRT1052.h.

◆ PWM_DMAEN_FAND

#define PWM_DMAEN_FAND (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)

FAND - FIFO Watermark AND Control 0b0..Selected FIFO watermarks are OR'ed together. 0b1..Selected FIFO watermarks are AND'ed together.

Definition at line 31561 of file MIMXRT1052.h.

◆ PWM_DMAEN_FAND_MASK

#define PWM_DMAEN_FAND_MASK   (0x100U)

Definition at line 31555 of file MIMXRT1052.h.

◆ PWM_DMAEN_FAND_SHIFT

#define PWM_DMAEN_FAND_SHIFT   (8U)

Definition at line 31556 of file MIMXRT1052.h.

◆ PWM_DMAEN_VALDE

#define PWM_DMAEN_VALDE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)

VALDE - Value Registers DMA Enable 0b0..DMA write requests disabled 0b1..DMA write requests for the VALx and FRACVALx registers enabled

Definition at line 31568 of file MIMXRT1052.h.

◆ PWM_DMAEN_VALDE_MASK

#define PWM_DMAEN_VALDE_MASK   (0x200U)

Definition at line 31562 of file MIMXRT1052.h.

◆ PWM_DMAEN_VALDE_SHIFT

#define PWM_DMAEN_VALDE_SHIFT   (9U)

Definition at line 31563 of file MIMXRT1052.h.

◆ PWM_DTCNT0_COUNT

#define PWM_DTCNT0_COUNT   (4U)

Definition at line 31660 of file MIMXRT1052.h.

◆ PWM_DTCNT0_DTCNT0

#define PWM_DTCNT0_DTCNT0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)

DTCNT0 - DTCNT0

Definition at line 31656 of file MIMXRT1052.h.

◆ PWM_DTCNT0_DTCNT0_MASK

#define PWM_DTCNT0_DTCNT0_MASK   (0xFFFFU)

Definition at line 31652 of file MIMXRT1052.h.

◆ PWM_DTCNT0_DTCNT0_SHIFT

#define PWM_DTCNT0_DTCNT0_SHIFT   (0U)

Definition at line 31653 of file MIMXRT1052.h.

◆ PWM_DTCNT1_COUNT

#define PWM_DTCNT1_COUNT   (4U)

Definition at line 31672 of file MIMXRT1052.h.

◆ PWM_DTCNT1_DTCNT1

#define PWM_DTCNT1_DTCNT1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)

DTCNT1 - DTCNT1

Definition at line 31668 of file MIMXRT1052.h.

◆ PWM_DTCNT1_DTCNT1_MASK

#define PWM_DTCNT1_DTCNT1_MASK   (0xFFFFU)

Definition at line 31664 of file MIMXRT1052.h.

◆ PWM_DTCNT1_DTCNT1_SHIFT

#define PWM_DTCNT1_DTCNT1_SHIFT   (0U)

Definition at line 31665 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM0SEL23

#define PWM_DTSRCSEL_SM0SEL23 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)

SM0SEL23 - Submodule 0 PWM23 Control Select 0b00..Generated SM0PWM23 signal is used by the deadtime logic. 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic. 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic. 0b11..PWM0_EXTA signal is used by the deadtime logic.

Definition at line 32242 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM0SEL23_MASK

#define PWM_DTSRCSEL_SM0SEL23_MASK   (0xCU)

Definition at line 32234 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM0SEL23_SHIFT

#define PWM_DTSRCSEL_SM0SEL23_SHIFT   (2U)

Definition at line 32235 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM0SEL45

#define PWM_DTSRCSEL_SM0SEL45 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)

SM0SEL45 - Submodule 0 PWM45 Control Select 0b00..Generated SM0PWM45 signal is used by the deadtime logic. 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic. 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic. 0b11..PWM0_EXTB signal is used by the deadtime logic.

Definition at line 32233 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM0SEL45_MASK

#define PWM_DTSRCSEL_SM0SEL45_MASK   (0x3U)

Definition at line 32225 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM0SEL45_SHIFT

#define PWM_DTSRCSEL_SM0SEL45_SHIFT   (0U)

Definition at line 32226 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM1SEL23

#define PWM_DTSRCSEL_SM1SEL23 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)

SM1SEL23 - Submodule 1 PWM23 Control Select 0b00..Generated SM1PWM23 signal is used by the deadtime logic. 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic. 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic. 0b11..PWM1_EXTA signal is used by the deadtime logic.

Definition at line 32260 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM1SEL23_MASK

#define PWM_DTSRCSEL_SM1SEL23_MASK   (0xC0U)

Definition at line 32252 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM1SEL23_SHIFT

#define PWM_DTSRCSEL_SM1SEL23_SHIFT   (6U)

Definition at line 32253 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM1SEL45

#define PWM_DTSRCSEL_SM1SEL45 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)

SM1SEL45 - Submodule 1 PWM45 Control Select 0b00..Generated SM1PWM45 signal is used by the deadtime logic. 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic. 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic. 0b11..PWM1_EXTB signal is used by the deadtime logic.

Definition at line 32251 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM1SEL45_MASK

#define PWM_DTSRCSEL_SM1SEL45_MASK   (0x30U)

Definition at line 32243 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM1SEL45_SHIFT

#define PWM_DTSRCSEL_SM1SEL45_SHIFT   (4U)

Definition at line 32244 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM2SEL23

#define PWM_DTSRCSEL_SM2SEL23 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)

SM2SEL23 - Submodule 2 PWM23 Control Select 0b00..Generated SM2PWM23 signal is used by the deadtime logic. 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic. 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic. 0b11..PWM2_EXTA signal is used by the deadtime logic.

Definition at line 32278 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM2SEL23_MASK

#define PWM_DTSRCSEL_SM2SEL23_MASK   (0xC00U)

Definition at line 32270 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM2SEL23_SHIFT

#define PWM_DTSRCSEL_SM2SEL23_SHIFT   (10U)

Definition at line 32271 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM2SEL45

#define PWM_DTSRCSEL_SM2SEL45 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)

SM2SEL45 - Submodule 2 PWM45 Control Select 0b00..Generated SM2PWM45 signal is used by the deadtime logic. 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic. 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic. 0b11..PWM2_EXTB signal is used by the deadtime logic.

Definition at line 32269 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM2SEL45_MASK

#define PWM_DTSRCSEL_SM2SEL45_MASK   (0x300U)

Definition at line 32261 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM2SEL45_SHIFT

#define PWM_DTSRCSEL_SM2SEL45_SHIFT   (8U)

Definition at line 32262 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM3SEL23

#define PWM_DTSRCSEL_SM3SEL23 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)

SM3SEL23 - Submodule 3 PWM23 Control Select 0b00..Generated SM3PWM23 signal is used by the deadtime logic. 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic. 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic. 0b11..PWM3_EXTA signal is used by the deadtime logic.

Definition at line 32296 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM3SEL23_MASK

#define PWM_DTSRCSEL_SM3SEL23_MASK   (0xC000U)

Definition at line 32288 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM3SEL23_SHIFT

#define PWM_DTSRCSEL_SM3SEL23_SHIFT   (14U)

Definition at line 32289 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM3SEL45

#define PWM_DTSRCSEL_SM3SEL45 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)

SM3SEL45 - Submodule 3 PWM45 Control Select 0b00..Generated SM3PWM45 signal is used by the deadtime logic. 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic. 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic. 0b11..PWM3_EXTB signal is used by the deadtime logic.

Definition at line 32287 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM3SEL45_MASK

#define PWM_DTSRCSEL_SM3SEL45_MASK   (0x3000U)

Definition at line 32279 of file MIMXRT1052.h.

◆ PWM_DTSRCSEL_SM3SEL45_SHIFT

#define PWM_DTSRCSEL_SM3SEL45_SHIFT   (12U)

Definition at line 32280 of file MIMXRT1052.h.

◆ PWM_FCTRL2_NOCOMB

#define PWM_FCTRL2_NOCOMB (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)

NOCOMB - No Combinational Path From Fault Input To PWM Output 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined with the filtered and latched fault signals to disable the PWM outputs. 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered and latched fault signals are used to disable the PWM outputs.

Definition at line 32457 of file MIMXRT1052.h.

◆ PWM_FCTRL2_NOCOMB_MASK

#define PWM_FCTRL2_NOCOMB_MASK   (0xFU)

Definition at line 32449 of file MIMXRT1052.h.

◆ PWM_FCTRL2_NOCOMB_SHIFT

#define PWM_FCTRL2_NOCOMB_SHIFT   (0U)

Definition at line 32450 of file MIMXRT1052.h.

◆ PWM_FCTRL_FAUTO

#define PWM_FCTRL_FAUTO (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)

FAUTO - Automatic Fault Clearing 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL]. This is further controlled by FCTRL[FSAFE]. 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFLAGx].

Definition at line 32375 of file MIMXRT1052.h.

◆ PWM_FCTRL_FAUTO_MASK

#define PWM_FCTRL_FAUTO_MASK   (0xF00U)

Definition at line 32365 of file MIMXRT1052.h.

◆ PWM_FCTRL_FAUTO_SHIFT

#define PWM_FCTRL_FAUTO_SHIFT   (8U)

Definition at line 32366 of file MIMXRT1052.h.

◆ PWM_FCTRL_FIE

#define PWM_FCTRL_FIE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)

FIE - Fault Interrupt Enables 0b0000..FAULTx CPU interrupt requests disabled. 0b0001..FAULTx CPU interrupt requests enabled.

Definition at line 32352 of file MIMXRT1052.h.

◆ PWM_FCTRL_FIE_MASK

#define PWM_FCTRL_FIE_MASK   (0xFU)

Definition at line 32346 of file MIMXRT1052.h.

◆ PWM_FCTRL_FIE_SHIFT

#define PWM_FCTRL_FIE_SHIFT   (0U)

Definition at line 32347 of file MIMXRT1052.h.

◆ PWM_FCTRL_FLVL

#define PWM_FCTRL_FLVL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)

FLVL - Fault Level 0b0000..A logic 0 on the fault input indicates a fault condition. 0b0001..A logic 1 on the fault input indicates a fault condition.

Definition at line 32382 of file MIMXRT1052.h.

◆ PWM_FCTRL_FLVL_MASK

#define PWM_FCTRL_FLVL_MASK   (0xF000U)

Definition at line 32376 of file MIMXRT1052.h.

◆ PWM_FCTRL_FLVL_SHIFT

#define PWM_FCTRL_FLVL_SHIFT   (12U)

Definition at line 32377 of file MIMXRT1052.h.

◆ PWM_FCTRL_FSAFE

#define PWM_FCTRL_FSAFE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)

FSAFE - Fault Safety Mode 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL] without regard to the state of FSTS[FFPINx]. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in DISMAPn). 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the state of FSTS[FFULL].

Definition at line 32364 of file MIMXRT1052.h.

◆ PWM_FCTRL_FSAFE_MASK

#define PWM_FCTRL_FSAFE_MASK   (0xF0U)

Definition at line 32353 of file MIMXRT1052.h.

◆ PWM_FCTRL_FSAFE_SHIFT

#define PWM_FCTRL_FSAFE_SHIFT   (4U)

Definition at line 32354 of file MIMXRT1052.h.

◆ PWM_FFILT_FILT_CNT

#define PWM_FFILT_FILT_CNT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)

FILT_CNT - Fault Filter Count

Definition at line 32426 of file MIMXRT1052.h.

◆ PWM_FFILT_FILT_CNT_MASK

#define PWM_FFILT_FILT_CNT_MASK   (0x700U)

Definition at line 32422 of file MIMXRT1052.h.

◆ PWM_FFILT_FILT_CNT_SHIFT

#define PWM_FFILT_FILT_CNT_SHIFT   (8U)

Definition at line 32423 of file MIMXRT1052.h.

◆ PWM_FFILT_FILT_PER

#define PWM_FFILT_FILT_PER (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)

FILT_PER - Fault Filter Period

Definition at line 32421 of file MIMXRT1052.h.

◆ PWM_FFILT_FILT_PER_MASK

#define PWM_FFILT_FILT_PER_MASK   (0xFFU)

Definition at line 32417 of file MIMXRT1052.h.

◆ PWM_FFILT_FILT_PER_SHIFT

#define PWM_FFILT_FILT_PER_SHIFT   (0U)

Definition at line 32418 of file MIMXRT1052.h.

◆ PWM_FFILT_GSTR

#define PWM_FFILT_GSTR (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)

GSTR - Fault Glitch Stretch Enable 0b0..Fault input glitch stretching is disabled. 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles.

Definition at line 32433 of file MIMXRT1052.h.

◆ PWM_FFILT_GSTR_MASK

#define PWM_FFILT_GSTR_MASK   (0x8000U)

Definition at line 32427 of file MIMXRT1052.h.

◆ PWM_FFILT_GSTR_SHIFT

#define PWM_FFILT_GSTR_SHIFT   (15U)

Definition at line 32428 of file MIMXRT1052.h.

◆ PWM_FRACVAL1_COUNT

#define PWM_FRACVAL1_COUNT   (4U)

Definition at line 31157 of file MIMXRT1052.h.

◆ PWM_FRACVAL1_FRACVAL1

#define PWM_FRACVAL1_FRACVAL1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)

FRACVAL1 - Fractional Value 1 Register

Definition at line 31153 of file MIMXRT1052.h.

◆ PWM_FRACVAL1_FRACVAL1_MASK

#define PWM_FRACVAL1_FRACVAL1_MASK   (0xF800U)

Definition at line 31149 of file MIMXRT1052.h.

◆ PWM_FRACVAL1_FRACVAL1_SHIFT

#define PWM_FRACVAL1_FRACVAL1_SHIFT   (11U)

Definition at line 31150 of file MIMXRT1052.h.

◆ PWM_FRACVAL2_COUNT

#define PWM_FRACVAL2_COUNT   (4U)

Definition at line 31181 of file MIMXRT1052.h.

◆ PWM_FRACVAL2_FRACVAL2

#define PWM_FRACVAL2_FRACVAL2 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)

FRACVAL2 - Fractional Value 2

Definition at line 31177 of file MIMXRT1052.h.

◆ PWM_FRACVAL2_FRACVAL2_MASK

#define PWM_FRACVAL2_FRACVAL2_MASK   (0xF800U)

Definition at line 31173 of file MIMXRT1052.h.

◆ PWM_FRACVAL2_FRACVAL2_SHIFT

#define PWM_FRACVAL2_FRACVAL2_SHIFT   (11U)

Definition at line 31174 of file MIMXRT1052.h.

◆ PWM_FRACVAL3_COUNT

#define PWM_FRACVAL3_COUNT   (4U)

Definition at line 31205 of file MIMXRT1052.h.

◆ PWM_FRACVAL3_FRACVAL3

#define PWM_FRACVAL3_FRACVAL3 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)

FRACVAL3 - Fractional Value 3

Definition at line 31201 of file MIMXRT1052.h.

◆ PWM_FRACVAL3_FRACVAL3_MASK

#define PWM_FRACVAL3_FRACVAL3_MASK   (0xF800U)

Definition at line 31197 of file MIMXRT1052.h.

◆ PWM_FRACVAL3_FRACVAL3_SHIFT

#define PWM_FRACVAL3_FRACVAL3_SHIFT   (11U)

Definition at line 31198 of file MIMXRT1052.h.

◆ PWM_FRACVAL4_COUNT

#define PWM_FRACVAL4_COUNT   (4U)

Definition at line 31229 of file MIMXRT1052.h.

◆ PWM_FRACVAL4_FRACVAL4

#define PWM_FRACVAL4_FRACVAL4 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)

FRACVAL4 - Fractional Value 4

Definition at line 31225 of file MIMXRT1052.h.

◆ PWM_FRACVAL4_FRACVAL4_MASK

#define PWM_FRACVAL4_FRACVAL4_MASK   (0xF800U)

Definition at line 31221 of file MIMXRT1052.h.

◆ PWM_FRACVAL4_FRACVAL4_SHIFT

#define PWM_FRACVAL4_FRACVAL4_SHIFT   (11U)

Definition at line 31222 of file MIMXRT1052.h.

◆ PWM_FRACVAL5_COUNT

#define PWM_FRACVAL5_COUNT   (4U)

Definition at line 31253 of file MIMXRT1052.h.

◆ PWM_FRACVAL5_FRACVAL5

#define PWM_FRACVAL5_FRACVAL5 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)

FRACVAL5 - Fractional Value 5

Definition at line 31249 of file MIMXRT1052.h.

◆ PWM_FRACVAL5_FRACVAL5_MASK

#define PWM_FRACVAL5_FRACVAL5_MASK   (0xF800U)

Definition at line 31245 of file MIMXRT1052.h.

◆ PWM_FRACVAL5_FRACVAL5_SHIFT

#define PWM_FRACVAL5_FRACVAL5_SHIFT   (11U)

Definition at line 31246 of file MIMXRT1052.h.

◆ PWM_FRCTRL_COUNT

#define PWM_FRCTRL_COUNT   (4U)

Definition at line 31305 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC1_EN

#define PWM_FRCTRL_FRAC1_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)

FRAC1_EN - Fractional Cycle PWM Period Enable 0b0..Disable fractional cycle length for the PWM period. 0b1..Enable fractional cycle length for the PWM period.

Definition at line 31275 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC1_EN_MASK

#define PWM_FRCTRL_FRAC1_EN_MASK   (0x2U)

Definition at line 31269 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC1_EN_SHIFT

#define PWM_FRCTRL_FRAC1_EN_SHIFT   (1U)

Definition at line 31270 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC23_EN

#define PWM_FRCTRL_FRAC23_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)

FRAC23_EN - Fractional Cycle Placement Enable for PWM_A 0b0..Disable fractional cycle placement for PWM_A. 0b1..Enable fractional cycle placement for PWM_A.

Definition at line 31282 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC23_EN_MASK

#define PWM_FRCTRL_FRAC23_EN_MASK   (0x4U)

Definition at line 31276 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC23_EN_SHIFT

#define PWM_FRCTRL_FRAC23_EN_SHIFT   (2U)

Definition at line 31277 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC45_EN

#define PWM_FRCTRL_FRAC45_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)

FRAC45_EN - Fractional Cycle Placement Enable for PWM_B 0b0..Disable fractional cycle placement for PWM_B. 0b1..Enable fractional cycle placement for PWM_B.

Definition at line 31289 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC45_EN_MASK

#define PWM_FRCTRL_FRAC45_EN_MASK   (0x10U)

Definition at line 31283 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC45_EN_SHIFT

#define PWM_FRCTRL_FRAC45_EN_SHIFT   (4U)

Definition at line 31284 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC_PU

#define PWM_FRCTRL_FRAC_PU (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK)

FRAC_PU - Fractional Delay Circuit Power Up 0b0..Turn off fractional delay logic. 0b1..Power up fractional delay logic.

Definition at line 31296 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC_PU_MASK

#define PWM_FRCTRL_FRAC_PU_MASK   (0x100U)

Definition at line 31290 of file MIMXRT1052.h.

◆ PWM_FRCTRL_FRAC_PU_SHIFT

#define PWM_FRCTRL_FRAC_PU_SHIFT   (8U)

Definition at line 31291 of file MIMXRT1052.h.

◆ PWM_FRCTRL_TEST

#define PWM_FRCTRL_TEST (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)

TEST - Test Status Bit

Definition at line 31301 of file MIMXRT1052.h.

◆ PWM_FRCTRL_TEST_MASK

#define PWM_FRCTRL_TEST_MASK   (0x8000U)

Definition at line 31297 of file MIMXRT1052.h.

◆ PWM_FRCTRL_TEST_SHIFT

#define PWM_FRCTRL_TEST_SHIFT   (15U)

Definition at line 31298 of file MIMXRT1052.h.

◆ PWM_FSTS_FFLAG

#define PWM_FSTS_FFLAG (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)

FFLAG - Fault Flags 0b0000..No fault on the FAULTx pin. 0b0001..Fault on the FAULTx pin.

Definition at line 32393 of file MIMXRT1052.h.

◆ PWM_FSTS_FFLAG_MASK

#define PWM_FSTS_FFLAG_MASK   (0xFU)

Definition at line 32387 of file MIMXRT1052.h.

◆ PWM_FSTS_FFLAG_SHIFT

#define PWM_FSTS_FFLAG_SHIFT   (0U)

Definition at line 32388 of file MIMXRT1052.h.

◆ PWM_FSTS_FFPIN

#define PWM_FSTS_FFPIN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)

FFPIN - Filtered Fault Pins

Definition at line 32405 of file MIMXRT1052.h.

◆ PWM_FSTS_FFPIN_MASK

#define PWM_FSTS_FFPIN_MASK   (0xF00U)

Definition at line 32401 of file MIMXRT1052.h.

◆ PWM_FSTS_FFPIN_SHIFT

#define PWM_FSTS_FFPIN_SHIFT   (8U)

Definition at line 32402 of file MIMXRT1052.h.

◆ PWM_FSTS_FFULL

#define PWM_FSTS_FFULL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)

FFULL - Full Cycle 0b0000..PWM outputs are not re-enabled at the start of a full cycle 0b0001..PWM outputs are re-enabled at the start of a full cycle

Definition at line 32400 of file MIMXRT1052.h.

◆ PWM_FSTS_FFULL_MASK

#define PWM_FSTS_FFULL_MASK   (0xF0U)

Definition at line 32394 of file MIMXRT1052.h.

◆ PWM_FSTS_FFULL_SHIFT

#define PWM_FSTS_FFULL_SHIFT   (4U)

Definition at line 32395 of file MIMXRT1052.h.

◆ PWM_FSTS_FHALF

#define PWM_FSTS_FHALF (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)

FHALF - Half Cycle Fault Recovery 0b0000..PWM outputs are not re-enabled at the start of a half cycle. 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).

Definition at line 32412 of file MIMXRT1052.h.

◆ PWM_FSTS_FHALF_MASK

#define PWM_FSTS_FHALF_MASK   (0xF000U)

Definition at line 32406 of file MIMXRT1052.h.

◆ PWM_FSTS_FHALF_SHIFT

#define PWM_FSTS_FHALF_SHIFT   (12U)

Definition at line 32407 of file MIMXRT1052.h.

◆ PWM_FTST_FTEST

#define PWM_FTST_FTEST (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)

FTEST - Fault Test 0b0..No fault 0b1..Cause a simulated fault

Definition at line 32444 of file MIMXRT1052.h.

◆ PWM_FTST_FTEST_MASK

#define PWM_FTST_FTEST_MASK   (0x1U)

Definition at line 32438 of file MIMXRT1052.h.

◆ PWM_FTST_FTEST_SHIFT

#define PWM_FTST_FTEST_SHIFT   (0U)

Definition at line 32439 of file MIMXRT1052.h.

◆ PWM_INIT_COUNT

#define PWM_INIT_COUNT   (4U)

Definition at line 30934 of file MIMXRT1052.h.

◆ PWM_INIT_INIT

#define PWM_INIT_INIT (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)

INIT - Initial Count Register Bits

Definition at line 30930 of file MIMXRT1052.h.

◆ PWM_INIT_INIT_MASK

#define PWM_INIT_INIT_MASK   (0xFFFFU)

Definition at line 30926 of file MIMXRT1052.h.

◆ PWM_INIT_INIT_SHIFT

#define PWM_INIT_INIT_SHIFT   (0U)

Definition at line 30927 of file MIMXRT1052.h.

◆ PWM_INTEN_CA0IE

#define PWM_INTEN_CA0IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)

CA0IE - Capture A 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA0]. 0b1..Interrupt request enabled for STS[CFA0].

Definition at line 31485 of file MIMXRT1052.h.

◆ PWM_INTEN_CA0IE_MASK

#define PWM_INTEN_CA0IE_MASK   (0x400U)

Definition at line 31479 of file MIMXRT1052.h.

◆ PWM_INTEN_CA0IE_SHIFT

#define PWM_INTEN_CA0IE_SHIFT   (10U)

Definition at line 31480 of file MIMXRT1052.h.

◆ PWM_INTEN_CA1IE

#define PWM_INTEN_CA1IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)

CA1IE - Capture A 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA1]. 0b1..Interrupt request enabled for STS[CFA1].

Definition at line 31492 of file MIMXRT1052.h.

◆ PWM_INTEN_CA1IE_MASK

#define PWM_INTEN_CA1IE_MASK   (0x800U)

Definition at line 31486 of file MIMXRT1052.h.

◆ PWM_INTEN_CA1IE_SHIFT

#define PWM_INTEN_CA1IE_SHIFT   (11U)

Definition at line 31487 of file MIMXRT1052.h.

◆ PWM_INTEN_CB0IE

#define PWM_INTEN_CB0IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)

CB0IE - Capture B 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB0]. 0b1..Interrupt request enabled for STS[CFB0].

Definition at line 31471 of file MIMXRT1052.h.

◆ PWM_INTEN_CB0IE_MASK

#define PWM_INTEN_CB0IE_MASK   (0x100U)

Definition at line 31465 of file MIMXRT1052.h.

◆ PWM_INTEN_CB0IE_SHIFT

#define PWM_INTEN_CB0IE_SHIFT   (8U)

Definition at line 31466 of file MIMXRT1052.h.

◆ PWM_INTEN_CB1IE

#define PWM_INTEN_CB1IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)

CB1IE - Capture B 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB1]. 0b1..Interrupt request enabled for STS[CFB1].

Definition at line 31478 of file MIMXRT1052.h.

◆ PWM_INTEN_CB1IE_MASK

#define PWM_INTEN_CB1IE_MASK   (0x200U)

Definition at line 31472 of file MIMXRT1052.h.

◆ PWM_INTEN_CB1IE_SHIFT

#define PWM_INTEN_CB1IE_SHIFT   (9U)

Definition at line 31473 of file MIMXRT1052.h.

◆ PWM_INTEN_CMPIE

#define PWM_INTEN_CMPIE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)

CMPIE - Compare Interrupt Enables 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.

Definition at line 31450 of file MIMXRT1052.h.

◆ PWM_INTEN_CMPIE_MASK

#define PWM_INTEN_CMPIE_MASK   (0x3FU)

Definition at line 31444 of file MIMXRT1052.h.

◆ PWM_INTEN_CMPIE_SHIFT

#define PWM_INTEN_CMPIE_SHIFT   (0U)

Definition at line 31445 of file MIMXRT1052.h.

◆ PWM_INTEN_COUNT

#define PWM_INTEN_COUNT   (4U)

Definition at line 31510 of file MIMXRT1052.h.

◆ PWM_INTEN_CX0IE

#define PWM_INTEN_CX0IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)

CX0IE - Capture X 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX0]. 0b1..Interrupt request enabled for STS[CFX0].

Definition at line 31457 of file MIMXRT1052.h.

◆ PWM_INTEN_CX0IE_MASK

#define PWM_INTEN_CX0IE_MASK   (0x40U)

Definition at line 31451 of file MIMXRT1052.h.

◆ PWM_INTEN_CX0IE_SHIFT

#define PWM_INTEN_CX0IE_SHIFT   (6U)

Definition at line 31452 of file MIMXRT1052.h.

◆ PWM_INTEN_CX1IE

#define PWM_INTEN_CX1IE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)

CX1IE - Capture X 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX1]. 0b1..Interrupt request enabled for STS[CFX1].

Definition at line 31464 of file MIMXRT1052.h.

◆ PWM_INTEN_CX1IE_MASK

#define PWM_INTEN_CX1IE_MASK   (0x80U)

Definition at line 31458 of file MIMXRT1052.h.

◆ PWM_INTEN_CX1IE_SHIFT

#define PWM_INTEN_CX1IE_SHIFT   (7U)

Definition at line 31459 of file MIMXRT1052.h.

◆ PWM_INTEN_REIE

#define PWM_INTEN_REIE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)

REIE - Reload Error Interrupt Enable 0b0..STS[REF] CPU interrupt requests disabled 0b1..STS[REF] CPU interrupt requests enabled

Definition at line 31506 of file MIMXRT1052.h.

◆ PWM_INTEN_REIE_MASK

#define PWM_INTEN_REIE_MASK   (0x2000U)

Definition at line 31500 of file MIMXRT1052.h.

◆ PWM_INTEN_REIE_SHIFT

#define PWM_INTEN_REIE_SHIFT   (13U)

Definition at line 31501 of file MIMXRT1052.h.

◆ PWM_INTEN_RIE

#define PWM_INTEN_RIE (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)

RIE - Reload Interrupt Enable 0b0..STS[RF] CPU interrupt requests disabled 0b1..STS[RF] CPU interrupt requests enabled

Definition at line 31499 of file MIMXRT1052.h.

◆ PWM_INTEN_RIE_MASK

#define PWM_INTEN_RIE_MASK   (0x1000U)

Definition at line 31493 of file MIMXRT1052.h.

◆ PWM_INTEN_RIE_SHIFT

#define PWM_INTEN_RIE_SHIFT   (12U)

Definition at line 31494 of file MIMXRT1052.h.

◆ PWM_MASK_MASKA

#define PWM_MASK_MASKA (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)

MASKA - PWM_A Masks 0b0000..PWM_A output normal. 0b0001..PWM_A output masked.

Definition at line 32153 of file MIMXRT1052.h.

◆ PWM_MASK_MASKA_MASK

#define PWM_MASK_MASKA_MASK   (0xF00U)

Definition at line 32147 of file MIMXRT1052.h.

◆ PWM_MASK_MASKA_SHIFT

#define PWM_MASK_MASKA_SHIFT   (8U)

Definition at line 32148 of file MIMXRT1052.h.

◆ PWM_MASK_MASKB

#define PWM_MASK_MASKB (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)

MASKB - PWM_B Masks 0b0000..PWM_B output normal. 0b0001..PWM_B output masked.

Definition at line 32146 of file MIMXRT1052.h.

◆ PWM_MASK_MASKB_MASK

#define PWM_MASK_MASKB_MASK   (0xF0U)

Definition at line 32140 of file MIMXRT1052.h.

◆ PWM_MASK_MASKB_SHIFT

#define PWM_MASK_MASKB_SHIFT   (4U)

Definition at line 32141 of file MIMXRT1052.h.

◆ PWM_MASK_MASKX

#define PWM_MASK_MASKX (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)

MASKX - PWM_X Masks 0b0000..PWM_X output normal. 0b0001..PWM_X output masked.

Definition at line 32139 of file MIMXRT1052.h.

◆ PWM_MASK_MASKX_MASK

#define PWM_MASK_MASKX_MASK   (0xFU)

Definition at line 32133 of file MIMXRT1052.h.

◆ PWM_MASK_MASKX_SHIFT

#define PWM_MASK_MASKX_SHIFT   (0U)

Definition at line 32134 of file MIMXRT1052.h.

◆ PWM_MASK_UPDATE_MASK

#define PWM_MASK_UPDATE_MASK (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_MASK_UPDATE_MASK_SHIFT)) & PWM_MASK_UPDATE_MASK_MASK)

UPDATE_MASK - Update Mask Bits Immediately 0b0000..Normal operation. MASK* bits within the corresponding submodule are not updated until a FORCE_OUT event occurs within the submodule. 0b0001..Immediate operation. MASK* bits within the corresponding submodule are updated on the following clock edge after setting this bit.

Definition at line 32160 of file MIMXRT1052.h.

◆ PWM_MASK_UPDATE_MASK_MASK

#define PWM_MASK_UPDATE_MASK_MASK   (0xF000U)

Definition at line 32154 of file MIMXRT1052.h.

◆ PWM_MASK_UPDATE_MASK_SHIFT

#define PWM_MASK_UPDATE_MASK_SHIFT   (12U)

Definition at line 32155 of file MIMXRT1052.h.

◆ PWM_MCTRL2_MONPLL

#define PWM_MCTRL2_MONPLL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)

MONPLL - Monitor PLL State 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software. These bits are write protected until the next reset. 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems. These bits are write protected until the next reset.

Definition at line 32341 of file MIMXRT1052.h.

◆ PWM_MCTRL2_MONPLL_MASK

#define PWM_MCTRL2_MONPLL_MASK   (0x3U)

Definition at line 32331 of file MIMXRT1052.h.

◆ PWM_MCTRL2_MONPLL_SHIFT

#define PWM_MCTRL2_MONPLL_SHIFT   (0U)

Definition at line 32332 of file MIMXRT1052.h.

◆ PWM_MCTRL_CLDOK

#define PWM_MCTRL_CLDOK (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)

CLDOK - Clear Load Okay

Definition at line 32312 of file MIMXRT1052.h.

◆ PWM_MCTRL_CLDOK_MASK

#define PWM_MCTRL_CLDOK_MASK   (0xF0U)

Definition at line 32308 of file MIMXRT1052.h.

◆ PWM_MCTRL_CLDOK_SHIFT

#define PWM_MCTRL_CLDOK_SHIFT   (4U)

Definition at line 32309 of file MIMXRT1052.h.

◆ PWM_MCTRL_IPOL

#define PWM_MCTRL_IPOL (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)

IPOL - Current Polarity 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule. 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.

Definition at line 32326 of file MIMXRT1052.h.

◆ PWM_MCTRL_IPOL_MASK

#define PWM_MCTRL_IPOL_MASK   (0xF000U)

Definition at line 32320 of file MIMXRT1052.h.

◆ PWM_MCTRL_IPOL_SHIFT

#define PWM_MCTRL_IPOL_SHIFT   (12U)

Definition at line 32321 of file MIMXRT1052.h.

◆ PWM_MCTRL_LDOK

#define PWM_MCTRL_LDOK (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)

LDOK - Load Okay 0b0000..Do not load new values. 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.

Definition at line 32307 of file MIMXRT1052.h.

◆ PWM_MCTRL_LDOK_MASK

#define PWM_MCTRL_LDOK_MASK   (0xFU)

Definition at line 32301 of file MIMXRT1052.h.

◆ PWM_MCTRL_LDOK_SHIFT

#define PWM_MCTRL_LDOK_SHIFT   (0U)

Definition at line 32302 of file MIMXRT1052.h.

◆ PWM_MCTRL_RUN

#define PWM_MCTRL_RUN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)

RUN - Run 0b0000..PWM generator is disabled in the corresponding submodule. 0b0001..PWM generator is enabled in the corresponding submodule.

Definition at line 32319 of file MIMXRT1052.h.

◆ PWM_MCTRL_RUN_MASK

#define PWM_MCTRL_RUN_MASK   (0xF00U)

Definition at line 32313 of file MIMXRT1052.h.

◆ PWM_MCTRL_RUN_SHIFT

#define PWM_MCTRL_RUN_SHIFT   (8U)

Definition at line 32314 of file MIMXRT1052.h.

◆ PWM_OCTRL_COUNT

#define PWM_OCTRL_COUNT   (4U)

Definition at line 31375 of file MIMXRT1052.h.

◆ PWM_OCTRL_POLA

#define PWM_OCTRL_POLA (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)

POLA - PWM_A Output Polarity 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state. 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.

Definition at line 31356 of file MIMXRT1052.h.

◆ PWM_OCTRL_POLA_MASK

#define PWM_OCTRL_POLA_MASK   (0x400U)

Definition at line 31350 of file MIMXRT1052.h.

◆ PWM_OCTRL_POLA_SHIFT

#define PWM_OCTRL_POLA_SHIFT   (10U)

Definition at line 31351 of file MIMXRT1052.h.

◆ PWM_OCTRL_POLB

#define PWM_OCTRL_POLB (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)

POLB - PWM_B Output Polarity 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state. 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.

Definition at line 31349 of file MIMXRT1052.h.

◆ PWM_OCTRL_POLB_MASK

#define PWM_OCTRL_POLB_MASK   (0x200U)

Definition at line 31343 of file MIMXRT1052.h.

◆ PWM_OCTRL_POLB_SHIFT

#define PWM_OCTRL_POLB_SHIFT   (9U)

Definition at line 31344 of file MIMXRT1052.h.

◆ PWM_OCTRL_POLX

#define PWM_OCTRL_POLX (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)

POLX - PWM_X Output Polarity 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state. 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.

Definition at line 31342 of file MIMXRT1052.h.

◆ PWM_OCTRL_POLX_MASK

#define PWM_OCTRL_POLX_MASK   (0x100U)

Definition at line 31336 of file MIMXRT1052.h.

◆ PWM_OCTRL_POLX_SHIFT

#define PWM_OCTRL_POLX_SHIFT   (8U)

Definition at line 31337 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMA_IN

#define PWM_OCTRL_PWMA_IN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)

PWMA_IN - PWM_A Input

Definition at line 31371 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMA_IN_MASK

#define PWM_OCTRL_PWMA_IN_MASK   (0x8000U)

Definition at line 31367 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMA_IN_SHIFT

#define PWM_OCTRL_PWMA_IN_SHIFT   (15U)

Definition at line 31368 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMAFS

#define PWM_OCTRL_PWMAFS (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)

PWMAFS - PWM_A Fault State 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. 0b10..Output is tristated. 0b11..Output is tristated.

Definition at line 31335 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMAFS_MASK

#define PWM_OCTRL_PWMAFS_MASK   (0x30U)

Definition at line 31327 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMAFS_SHIFT

#define PWM_OCTRL_PWMAFS_SHIFT   (4U)

Definition at line 31328 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMB_IN

#define PWM_OCTRL_PWMB_IN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)

PWMB_IN - PWM_B Input

Definition at line 31366 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMB_IN_MASK

#define PWM_OCTRL_PWMB_IN_MASK   (0x4000U)

Definition at line 31362 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMB_IN_SHIFT

#define PWM_OCTRL_PWMB_IN_SHIFT   (14U)

Definition at line 31363 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMBFS

#define PWM_OCTRL_PWMBFS (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)

PWMBFS - PWM_B Fault State 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. 0b10..Output is tristated. 0b11..Output is tristated.

Definition at line 31326 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMBFS_MASK

#define PWM_OCTRL_PWMBFS_MASK   (0xCU)

Definition at line 31318 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMBFS_SHIFT

#define PWM_OCTRL_PWMBFS_SHIFT   (2U)

Definition at line 31319 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMX_IN

#define PWM_OCTRL_PWMX_IN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)

PWMX_IN - PWM_X Input

Definition at line 31361 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMX_IN_MASK

#define PWM_OCTRL_PWMX_IN_MASK   (0x2000U)

Definition at line 31357 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMX_IN_SHIFT

#define PWM_OCTRL_PWMX_IN_SHIFT   (13U)

Definition at line 31358 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMXFS

#define PWM_OCTRL_PWMXFS (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)

PWMXFS - PWM_X Fault State 0b00..Output is forced to logic 0 state prior to consideration of output polarity control. 0b01..Output is forced to logic 1 state prior to consideration of output polarity control. 0b10..Output is tristated. 0b11..Output is tristated.

Definition at line 31317 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMXFS_MASK

#define PWM_OCTRL_PWMXFS_MASK   (0x3U)

Definition at line 31309 of file MIMXRT1052.h.

◆ PWM_OCTRL_PWMXFS_SHIFT

#define PWM_OCTRL_PWMXFS_SHIFT   (0U)

Definition at line 31310 of file MIMXRT1052.h.

◆ PWM_OUTEN_PWMA_EN

#define PWM_OUTEN_PWMA_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)

PWMA_EN - PWM_A Output Enables 0b0000..PWM_A output disabled. 0b0001..PWM_A output enabled.

Definition at line 32128 of file MIMXRT1052.h.

◆ PWM_OUTEN_PWMA_EN_MASK

#define PWM_OUTEN_PWMA_EN_MASK   (0xF00U)

Definition at line 32122 of file MIMXRT1052.h.

◆ PWM_OUTEN_PWMA_EN_SHIFT

#define PWM_OUTEN_PWMA_EN_SHIFT   (8U)

Definition at line 32123 of file MIMXRT1052.h.

◆ PWM_OUTEN_PWMB_EN

#define PWM_OUTEN_PWMB_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)

PWMB_EN - PWM_B Output Enables 0b0000..PWM_B output disabled. 0b0001..PWM_B output enabled.

Definition at line 32121 of file MIMXRT1052.h.

◆ PWM_OUTEN_PWMB_EN_MASK

#define PWM_OUTEN_PWMB_EN_MASK   (0xF0U)

Definition at line 32115 of file MIMXRT1052.h.

◆ PWM_OUTEN_PWMB_EN_SHIFT

#define PWM_OUTEN_PWMB_EN_SHIFT   (4U)

Definition at line 32116 of file MIMXRT1052.h.

◆ PWM_OUTEN_PWMX_EN

#define PWM_OUTEN_PWMX_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)

PWMX_EN - PWM_X Output Enables 0b0000..PWM_X output disabled. 0b0001..PWM_X output enabled.

Definition at line 32114 of file MIMXRT1052.h.

◆ PWM_OUTEN_PWMX_EN_MASK

#define PWM_OUTEN_PWMX_EN_MASK   (0xFU)

Definition at line 32108 of file MIMXRT1052.h.

◆ PWM_OUTEN_PWMX_EN_SHIFT

#define PWM_OUTEN_PWMX_EN_SHIFT   (0U)

Definition at line 32109 of file MIMXRT1052.h.

◆ PWM_STS_CFA0

#define PWM_STS_CFA0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)

CFA0 - Capture Flag A0

Definition at line 31410 of file MIMXRT1052.h.

◆ PWM_STS_CFA0_MASK

#define PWM_STS_CFA0_MASK   (0x400U)

Definition at line 31406 of file MIMXRT1052.h.

◆ PWM_STS_CFA0_SHIFT

#define PWM_STS_CFA0_SHIFT   (10U)

Definition at line 31407 of file MIMXRT1052.h.

◆ PWM_STS_CFA1

#define PWM_STS_CFA1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)

CFA1 - Capture Flag A1

Definition at line 31415 of file MIMXRT1052.h.

◆ PWM_STS_CFA1_MASK

#define PWM_STS_CFA1_MASK   (0x800U)

Definition at line 31411 of file MIMXRT1052.h.

◆ PWM_STS_CFA1_SHIFT

#define PWM_STS_CFA1_SHIFT   (11U)

Definition at line 31412 of file MIMXRT1052.h.

◆ PWM_STS_CFB0

#define PWM_STS_CFB0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)

CFB0 - Capture Flag B0

Definition at line 31400 of file MIMXRT1052.h.

◆ PWM_STS_CFB0_MASK

#define PWM_STS_CFB0_MASK   (0x100U)

Definition at line 31396 of file MIMXRT1052.h.

◆ PWM_STS_CFB0_SHIFT

#define PWM_STS_CFB0_SHIFT   (8U)

Definition at line 31397 of file MIMXRT1052.h.

◆ PWM_STS_CFB1

#define PWM_STS_CFB1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)

CFB1 - Capture Flag B1

Definition at line 31405 of file MIMXRT1052.h.

◆ PWM_STS_CFB1_MASK

#define PWM_STS_CFB1_MASK   (0x200U)

Definition at line 31401 of file MIMXRT1052.h.

◆ PWM_STS_CFB1_SHIFT

#define PWM_STS_CFB1_SHIFT   (9U)

Definition at line 31402 of file MIMXRT1052.h.

◆ PWM_STS_CFX0

#define PWM_STS_CFX0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)

CFX0 - Capture Flag X0

Definition at line 31390 of file MIMXRT1052.h.

◆ PWM_STS_CFX0_MASK

#define PWM_STS_CFX0_MASK   (0x40U)

Definition at line 31386 of file MIMXRT1052.h.

◆ PWM_STS_CFX0_SHIFT

#define PWM_STS_CFX0_SHIFT   (6U)

Definition at line 31387 of file MIMXRT1052.h.

◆ PWM_STS_CFX1

#define PWM_STS_CFX1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)

CFX1 - Capture Flag X1

Definition at line 31395 of file MIMXRT1052.h.

◆ PWM_STS_CFX1_MASK

#define PWM_STS_CFX1_MASK   (0x80U)

Definition at line 31391 of file MIMXRT1052.h.

◆ PWM_STS_CFX1_SHIFT

#define PWM_STS_CFX1_SHIFT   (7U)

Definition at line 31392 of file MIMXRT1052.h.

◆ PWM_STS_CMPF

#define PWM_STS_CMPF (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)

CMPF - Compare Flags 0b000000..No compare event has occurred for a particular VALx value. 0b000001..A compare event has occurred for a particular VALx value.

Definition at line 31385 of file MIMXRT1052.h.

◆ PWM_STS_CMPF_MASK

#define PWM_STS_CMPF_MASK   (0x3FU)

Definition at line 31379 of file MIMXRT1052.h.

◆ PWM_STS_CMPF_SHIFT

#define PWM_STS_CMPF_SHIFT   (0U)

Definition at line 31380 of file MIMXRT1052.h.

◆ PWM_STS_COUNT

#define PWM_STS_COUNT   (4U)

Definition at line 31440 of file MIMXRT1052.h.

◆ PWM_STS_REF

#define PWM_STS_REF (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)

REF - Reload Error Flag 0b0..No reload error occurred. 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.

Definition at line 31429 of file MIMXRT1052.h.

◆ PWM_STS_REF_MASK

#define PWM_STS_REF_MASK   (0x2000U)

Definition at line 31423 of file MIMXRT1052.h.

◆ PWM_STS_REF_SHIFT

#define PWM_STS_REF_SHIFT   (13U)

Definition at line 31424 of file MIMXRT1052.h.

◆ PWM_STS_RF

#define PWM_STS_RF (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)

RF - Reload Flag 0b0..No new reload cycle since last STS[RF] clearing 0b1..New reload cycle since last STS[RF] clearing

Definition at line 31422 of file MIMXRT1052.h.

◆ PWM_STS_RF_MASK

#define PWM_STS_RF_MASK   (0x1000U)

Definition at line 31416 of file MIMXRT1052.h.

◆ PWM_STS_RF_SHIFT

#define PWM_STS_RF_SHIFT   (12U)

Definition at line 31417 of file MIMXRT1052.h.

◆ PWM_STS_RUF

#define PWM_STS_RUF (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)

RUF - Registers Updated Flag 0b0..No register update has occurred since last reload. 0b1..At least one of the double buffered registers has been updated since the last reload.

Definition at line 31436 of file MIMXRT1052.h.

◆ PWM_STS_RUF_MASK

#define PWM_STS_RUF_MASK   (0x4000U)

Definition at line 31430 of file MIMXRT1052.h.

◆ PWM_STS_RUF_SHIFT

#define PWM_STS_RUF_SHIFT   (14U)

Definition at line 31431 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM0OUT23

#define PWM_SWCOUT_SM0OUT23 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)

SM0OUT23 - Submodule 0 Software Controlled Output 23 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23. 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.

Definition at line 32178 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM0OUT23_MASK

#define PWM_SWCOUT_SM0OUT23_MASK   (0x2U)

Definition at line 32172 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM0OUT23_SHIFT

#define PWM_SWCOUT_SM0OUT23_SHIFT   (1U)

Definition at line 32173 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM0OUT45

#define PWM_SWCOUT_SM0OUT45 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)

SM0OUT45 - Submodule 0 Software Controlled Output 45 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45. 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.

Definition at line 32171 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM0OUT45_MASK

#define PWM_SWCOUT_SM0OUT45_MASK   (0x1U)

Definition at line 32165 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM0OUT45_SHIFT

#define PWM_SWCOUT_SM0OUT45_SHIFT   (0U)

Definition at line 32166 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM1OUT23

#define PWM_SWCOUT_SM1OUT23 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)

SM1OUT23 - Submodule 1 Software Controlled Output 23 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23. 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.

Definition at line 32192 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM1OUT23_MASK

#define PWM_SWCOUT_SM1OUT23_MASK   (0x8U)

Definition at line 32186 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM1OUT23_SHIFT

#define PWM_SWCOUT_SM1OUT23_SHIFT   (3U)

Definition at line 32187 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM1OUT45

#define PWM_SWCOUT_SM1OUT45 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)

SM1OUT45 - Submodule 1 Software Controlled Output 45 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45. 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.

Definition at line 32185 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM1OUT45_MASK

#define PWM_SWCOUT_SM1OUT45_MASK   (0x4U)

Definition at line 32179 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM1OUT45_SHIFT

#define PWM_SWCOUT_SM1OUT45_SHIFT   (2U)

Definition at line 32180 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM2OUT23

#define PWM_SWCOUT_SM2OUT23 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)

SM2OUT23 - Submodule 2 Software Controlled Output 23 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23. 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.

Definition at line 32206 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM2OUT23_MASK

#define PWM_SWCOUT_SM2OUT23_MASK   (0x20U)

Definition at line 32200 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM2OUT23_SHIFT

#define PWM_SWCOUT_SM2OUT23_SHIFT   (5U)

Definition at line 32201 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM2OUT45

#define PWM_SWCOUT_SM2OUT45 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)

SM2OUT45 - Submodule 2 Software Controlled Output 45 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45. 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.

Definition at line 32199 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM2OUT45_MASK

#define PWM_SWCOUT_SM2OUT45_MASK   (0x10U)

Definition at line 32193 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM2OUT45_SHIFT

#define PWM_SWCOUT_SM2OUT45_SHIFT   (4U)

Definition at line 32194 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM3OUT23

#define PWM_SWCOUT_SM3OUT23 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)

SM3OUT23 - Submodule 3 Software Controlled Output 23 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23. 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.

Definition at line 32220 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM3OUT23_MASK

#define PWM_SWCOUT_SM3OUT23_MASK   (0x80U)

Definition at line 32214 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM3OUT23_SHIFT

#define PWM_SWCOUT_SM3OUT23_SHIFT   (7U)

Definition at line 32215 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM3OUT45

#define PWM_SWCOUT_SM3OUT45 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)

SM3OUT45 - Submodule 3 Software Controlled Output 45 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45. 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.

Definition at line 32213 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM3OUT45_MASK

#define PWM_SWCOUT_SM3OUT45_MASK   (0x40U)

Definition at line 32207 of file MIMXRT1052.h.

◆ PWM_SWCOUT_SM3OUT45_SHIFT

#define PWM_SWCOUT_SM3OUT45_SHIFT   (6U)

Definition at line 32208 of file MIMXRT1052.h.

◆ PWM_TCTRL_COUNT

#define PWM_TCTRL_COUNT   (4U)

Definition at line 31608 of file MIMXRT1052.h.

◆ PWM_TCTRL_OUT_TRIG_EN

#define PWM_TCTRL_OUT_TRIG_EN (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)

OUT_TRIG_EN - Output Trigger Enables 0b000000..PWM_OUT_TRIGx will not set when the counter value matches the VALx value. 0b000001..PWM_OUT_TRIGx will set when the counter value matches the VALx value.

Definition at line 31582 of file MIMXRT1052.h.

◆ PWM_TCTRL_OUT_TRIG_EN_MASK

#define PWM_TCTRL_OUT_TRIG_EN_MASK   (0x3FU)

Definition at line 31576 of file MIMXRT1052.h.

◆ PWM_TCTRL_OUT_TRIG_EN_SHIFT

#define PWM_TCTRL_OUT_TRIG_EN_SHIFT   (0U)

Definition at line 31577 of file MIMXRT1052.h.

◆ PWM_TCTRL_PWAOT0

#define PWM_TCTRL_PWAOT0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)

PWAOT0 - Output Trigger 0 Source Select 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port.

Definition at line 31604 of file MIMXRT1052.h.

◆ PWM_TCTRL_PWAOT0_MASK

#define PWM_TCTRL_PWAOT0_MASK   (0x8000U)

Definition at line 31598 of file MIMXRT1052.h.

◆ PWM_TCTRL_PWAOT0_SHIFT

#define PWM_TCTRL_PWAOT0_SHIFT   (15U)

Definition at line 31599 of file MIMXRT1052.h.

◆ PWM_TCTRL_PWBOT1

#define PWM_TCTRL_PWBOT1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)

PWBOT1 - Output Trigger 1 Source Select 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port.

Definition at line 31597 of file MIMXRT1052.h.

◆ PWM_TCTRL_PWBOT1_MASK

#define PWM_TCTRL_PWBOT1_MASK   (0x4000U)

Definition at line 31591 of file MIMXRT1052.h.

◆ PWM_TCTRL_PWBOT1_SHIFT

#define PWM_TCTRL_PWBOT1_SHIFT   (14U)

Definition at line 31592 of file MIMXRT1052.h.

◆ PWM_TCTRL_TRGFRQ

#define PWM_TCTRL_TRGFRQ (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)

TRGFRQ - Trigger frequency 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero. 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.

Definition at line 31590 of file MIMXRT1052.h.

◆ PWM_TCTRL_TRGFRQ_MASK

#define PWM_TCTRL_TRGFRQ_MASK   (0x1000U)

Definition at line 31583 of file MIMXRT1052.h.

◆ PWM_TCTRL_TRGFRQ_SHIFT

#define PWM_TCTRL_TRGFRQ_SHIFT   (12U)

Definition at line 31584 of file MIMXRT1052.h.

◆ PWM_VAL0_COUNT

#define PWM_VAL0_COUNT   (4U)

Definition at line 31145 of file MIMXRT1052.h.

◆ PWM_VAL0_VAL0

#define PWM_VAL0_VAL0 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)

VAL0 - Value Register 0

Definition at line 31141 of file MIMXRT1052.h.

◆ PWM_VAL0_VAL0_MASK

#define PWM_VAL0_VAL0_MASK   (0xFFFFU)

Definition at line 31137 of file MIMXRT1052.h.

◆ PWM_VAL0_VAL0_SHIFT

#define PWM_VAL0_VAL0_SHIFT   (0U)

Definition at line 31138 of file MIMXRT1052.h.

◆ PWM_VAL1_COUNT

#define PWM_VAL1_COUNT   (4U)

Definition at line 31169 of file MIMXRT1052.h.

◆ PWM_VAL1_VAL1

#define PWM_VAL1_VAL1 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)

VAL1 - Value Register 1

Definition at line 31165 of file MIMXRT1052.h.

◆ PWM_VAL1_VAL1_MASK

#define PWM_VAL1_VAL1_MASK   (0xFFFFU)

Definition at line 31161 of file MIMXRT1052.h.

◆ PWM_VAL1_VAL1_SHIFT

#define PWM_VAL1_VAL1_SHIFT   (0U)

Definition at line 31162 of file MIMXRT1052.h.

◆ PWM_VAL2_COUNT

#define PWM_VAL2_COUNT   (4U)

Definition at line 31193 of file MIMXRT1052.h.

◆ PWM_VAL2_VAL2

#define PWM_VAL2_VAL2 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)

VAL2 - Value Register 2

Definition at line 31189 of file MIMXRT1052.h.

◆ PWM_VAL2_VAL2_MASK

#define PWM_VAL2_VAL2_MASK   (0xFFFFU)

Definition at line 31185 of file MIMXRT1052.h.

◆ PWM_VAL2_VAL2_SHIFT

#define PWM_VAL2_VAL2_SHIFT   (0U)

Definition at line 31186 of file MIMXRT1052.h.

◆ PWM_VAL3_COUNT

#define PWM_VAL3_COUNT   (4U)

Definition at line 31217 of file MIMXRT1052.h.

◆ PWM_VAL3_VAL3

#define PWM_VAL3_VAL3 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)

VAL3 - Value Register 3

Definition at line 31213 of file MIMXRT1052.h.

◆ PWM_VAL3_VAL3_MASK

#define PWM_VAL3_VAL3_MASK   (0xFFFFU)

Definition at line 31209 of file MIMXRT1052.h.

◆ PWM_VAL3_VAL3_SHIFT

#define PWM_VAL3_VAL3_SHIFT   (0U)

Definition at line 31210 of file MIMXRT1052.h.

◆ PWM_VAL4_COUNT

#define PWM_VAL4_COUNT   (4U)

Definition at line 31241 of file MIMXRT1052.h.

◆ PWM_VAL4_VAL4

#define PWM_VAL4_VAL4 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)

VAL4 - Value Register 4

Definition at line 31237 of file MIMXRT1052.h.

◆ PWM_VAL4_VAL4_MASK

#define PWM_VAL4_VAL4_MASK   (0xFFFFU)

Definition at line 31233 of file MIMXRT1052.h.

◆ PWM_VAL4_VAL4_SHIFT

#define PWM_VAL4_VAL4_SHIFT   (0U)

Definition at line 31234 of file MIMXRT1052.h.

◆ PWM_VAL5_COUNT

#define PWM_VAL5_COUNT   (4U)

Definition at line 31265 of file MIMXRT1052.h.

◆ PWM_VAL5_VAL5

#define PWM_VAL5_VAL5 (   x)    (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)

VAL5 - Value Register 5

Definition at line 31261 of file MIMXRT1052.h.

◆ PWM_VAL5_VAL5_MASK

#define PWM_VAL5_VAL5_MASK   (0xFFFFU)

Definition at line 31257 of file MIMXRT1052.h.

◆ PWM_VAL5_VAL5_SHIFT

#define PWM_VAL5_VAL5_SHIFT   (0U)

Definition at line 31258 of file MIMXRT1052.h.


picovoice_driver
Author(s):
autogenerated on Fri Apr 1 2022 02:15:10