Macros | |
| #define | GPT_ICR_COUNT (2U) |
| #define | GPT_OCR_COUNT (3U) |
CR - GPT Control Register | |
| #define | GPT_CR_EN_MASK (0x1U) |
| #define | GPT_CR_EN_SHIFT (0U) |
| #define | GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) |
| #define | GPT_CR_ENMOD_MASK (0x2U) |
| #define | GPT_CR_ENMOD_SHIFT (1U) |
| #define | GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) |
| #define | GPT_CR_DBGEN_MASK (0x4U) |
| #define | GPT_CR_DBGEN_SHIFT (2U) |
| #define | GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) |
| #define | GPT_CR_WAITEN_MASK (0x8U) |
| #define | GPT_CR_WAITEN_SHIFT (3U) |
| #define | GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) |
| #define | GPT_CR_DOZEEN_MASK (0x10U) |
| #define | GPT_CR_DOZEEN_SHIFT (4U) |
| #define | GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) |
| #define | GPT_CR_STOPEN_MASK (0x20U) |
| #define | GPT_CR_STOPEN_SHIFT (5U) |
| #define | GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) |
| #define | GPT_CR_CLKSRC_MASK (0x1C0U) |
| #define | GPT_CR_CLKSRC_SHIFT (6U) |
| #define | GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) |
| #define | GPT_CR_FRR_MASK (0x200U) |
| #define | GPT_CR_FRR_SHIFT (9U) |
| #define | GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) |
| #define | GPT_CR_EN_24M_MASK (0x400U) |
| #define | GPT_CR_EN_24M_SHIFT (10U) |
| #define | GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) |
| #define | GPT_CR_SWR_MASK (0x8000U) |
| #define | GPT_CR_SWR_SHIFT (15U) |
| #define | GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) |
| #define | GPT_CR_IM1_MASK (0x30000U) |
| #define | GPT_CR_IM1_SHIFT (16U) |
| #define | GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) |
| #define | GPT_CR_IM2_MASK (0xC0000U) |
| #define | GPT_CR_IM2_SHIFT (18U) |
| #define | GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) |
| #define | GPT_CR_OM1_MASK (0x700000U) |
| #define | GPT_CR_OM1_SHIFT (20U) |
| #define | GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) |
| #define | GPT_CR_OM2_MASK (0x3800000U) |
| #define | GPT_CR_OM2_SHIFT (23U) |
| #define | GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) |
| #define | GPT_CR_OM3_MASK (0x1C000000U) |
| #define | GPT_CR_OM3_SHIFT (26U) |
| #define | GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) |
| #define | GPT_CR_FO1_MASK (0x20000000U) |
| #define | GPT_CR_FO1_SHIFT (29U) |
| #define | GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) |
| #define | GPT_CR_FO2_MASK (0x40000000U) |
| #define | GPT_CR_FO2_SHIFT (30U) |
| #define | GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) |
| #define | GPT_CR_FO3_MASK (0x80000000U) |
| #define | GPT_CR_FO3_SHIFT (31U) |
| #define | GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) |
PR - GPT Prescaler Register | |
| #define | GPT_PR_PRESCALER_MASK (0xFFFU) |
| #define | GPT_PR_PRESCALER_SHIFT (0U) |
| #define | GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) |
| #define | GPT_PR_PRESCALER24M_MASK (0xF000U) |
| #define | GPT_PR_PRESCALER24M_SHIFT (12U) |
| #define | GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) |
SR - GPT Status Register | |
| #define | GPT_SR_OF1_MASK (0x1U) |
| #define | GPT_SR_OF1_SHIFT (0U) |
| #define | GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) |
| #define | GPT_SR_OF2_MASK (0x2U) |
| #define | GPT_SR_OF2_SHIFT (1U) |
| #define | GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) |
| #define | GPT_SR_OF3_MASK (0x4U) |
| #define | GPT_SR_OF3_SHIFT (2U) |
| #define | GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) |
| #define | GPT_SR_IF1_MASK (0x8U) |
| #define | GPT_SR_IF1_SHIFT (3U) |
| #define | GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) |
| #define | GPT_SR_IF2_MASK (0x10U) |
| #define | GPT_SR_IF2_SHIFT (4U) |
| #define | GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) |
| #define | GPT_SR_ROV_MASK (0x20U) |
| #define | GPT_SR_ROV_SHIFT (5U) |
| #define | GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) |
IR - GPT Interrupt Register | |
| #define | GPT_IR_OF1IE_MASK (0x1U) |
| #define | GPT_IR_OF1IE_SHIFT (0U) |
| #define | GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) |
| #define | GPT_IR_OF2IE_MASK (0x2U) |
| #define | GPT_IR_OF2IE_SHIFT (1U) |
| #define | GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) |
| #define | GPT_IR_OF3IE_MASK (0x4U) |
| #define | GPT_IR_OF3IE_SHIFT (2U) |
| #define | GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) |
| #define | GPT_IR_IF1IE_MASK (0x8U) |
| #define | GPT_IR_IF1IE_SHIFT (3U) |
| #define | GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) |
| #define | GPT_IR_IF2IE_MASK (0x10U) |
| #define | GPT_IR_IF2IE_SHIFT (4U) |
| #define | GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) |
| #define | GPT_IR_ROVIE_MASK (0x20U) |
| #define | GPT_IR_ROVIE_SHIFT (5U) |
| #define | GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) |
OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 | |
| #define | GPT_OCR_COMP_MASK (0xFFFFFFFFU) |
| #define | GPT_OCR_COMP_SHIFT (0U) |
| #define | GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) |
ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 | |
| #define | GPT_ICR_CAPT_MASK (0xFFFFFFFFU) |
| #define | GPT_ICR_CAPT_SHIFT (0U) |
| #define | GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) |
CNT - GPT Counter Register | |
| #define | GPT_CNT_COUNT_MASK (0xFFFFFFFFU) |
| #define | GPT_CNT_COUNT_SHIFT (0U) |
| #define | GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) |
Detailed Description
Macro Definition Documentation
◆ GPT_CNT_COUNT
| #define GPT_CNT_COUNT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK) |
Definition at line 19827 of file MIMXRT1052.h.
◆ GPT_CNT_COUNT_MASK
| #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) |
Definition at line 19825 of file MIMXRT1052.h.
◆ GPT_CNT_COUNT_SHIFT
| #define GPT_CNT_COUNT_SHIFT (0U) |
Definition at line 19826 of file MIMXRT1052.h.
◆ GPT_CR_CLKSRC
| #define GPT_CR_CLKSRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) |
CLKSRC 0b000..No clock 0b001..Peripheral Clock (ipg_clk) 0b010..High Frequency Reference Clock (ipg_clk_highfreq) 0b011..External Clock 0b100..Low Frequency Reference Clock (ipg_clk_32k) 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
Definition at line 19650 of file MIMXRT1052.h.
◆ GPT_CR_CLKSRC_MASK
| #define GPT_CR_CLKSRC_MASK (0x1C0U) |
Definition at line 19640 of file MIMXRT1052.h.
◆ GPT_CR_CLKSRC_SHIFT
| #define GPT_CR_CLKSRC_SHIFT (6U) |
Definition at line 19641 of file MIMXRT1052.h.
◆ GPT_CR_DBGEN
| #define GPT_CR_DBGEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) |
DBGEN 0b0..GPT is disabled in debug mode. 0b1..GPT is enabled in debug mode.
Definition at line 19618 of file MIMXRT1052.h.
◆ GPT_CR_DBGEN_MASK
| #define GPT_CR_DBGEN_MASK (0x4U) |
Definition at line 19612 of file MIMXRT1052.h.
◆ GPT_CR_DBGEN_SHIFT
| #define GPT_CR_DBGEN_SHIFT (2U) |
Definition at line 19613 of file MIMXRT1052.h.
◆ GPT_CR_DOZEEN
| #define GPT_CR_DOZEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) |
DOZEEN 0b0..GPT is disabled in doze mode. 0b1..GPT is enabled in doze mode.
Definition at line 19632 of file MIMXRT1052.h.
◆ GPT_CR_DOZEEN_MASK
| #define GPT_CR_DOZEEN_MASK (0x10U) |
Definition at line 19626 of file MIMXRT1052.h.
◆ GPT_CR_DOZEEN_SHIFT
| #define GPT_CR_DOZEEN_SHIFT (4U) |
Definition at line 19627 of file MIMXRT1052.h.
◆ GPT_CR_EN
| #define GPT_CR_EN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) |
EN 0b0..GPT is disabled. 0b1..GPT is enabled.
Definition at line 19604 of file MIMXRT1052.h.
◆ GPT_CR_EN_24M
| #define GPT_CR_EN_24M | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) |
EN_24M 0b0..24M clock disabled 0b1..24M clock enabled
Definition at line 19664 of file MIMXRT1052.h.
◆ GPT_CR_EN_24M_MASK
| #define GPT_CR_EN_24M_MASK (0x400U) |
Definition at line 19658 of file MIMXRT1052.h.
◆ GPT_CR_EN_24M_SHIFT
| #define GPT_CR_EN_24M_SHIFT (10U) |
Definition at line 19659 of file MIMXRT1052.h.
◆ GPT_CR_EN_MASK
| #define GPT_CR_EN_MASK (0x1U) |
Definition at line 19598 of file MIMXRT1052.h.
◆ GPT_CR_EN_SHIFT
| #define GPT_CR_EN_SHIFT (0U) |
Definition at line 19599 of file MIMXRT1052.h.
◆ GPT_CR_ENMOD
| #define GPT_CR_ENMOD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) |
ENMOD 0b0..GPT counter will retain its value when it is disabled. 0b1..GPT counter value is reset to 0 when it is disabled.
Definition at line 19611 of file MIMXRT1052.h.
◆ GPT_CR_ENMOD_MASK
| #define GPT_CR_ENMOD_MASK (0x2U) |
Definition at line 19605 of file MIMXRT1052.h.
◆ GPT_CR_ENMOD_SHIFT
| #define GPT_CR_ENMOD_SHIFT (1U) |
Definition at line 19606 of file MIMXRT1052.h.
◆ GPT_CR_FO1
| #define GPT_CR_FO1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) |
Definition at line 19702 of file MIMXRT1052.h.
◆ GPT_CR_FO1_MASK
| #define GPT_CR_FO1_MASK (0x20000000U) |
Definition at line 19700 of file MIMXRT1052.h.
◆ GPT_CR_FO1_SHIFT
| #define GPT_CR_FO1_SHIFT (29U) |
Definition at line 19701 of file MIMXRT1052.h.
◆ GPT_CR_FO2
| #define GPT_CR_FO2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) |
Definition at line 19705 of file MIMXRT1052.h.
◆ GPT_CR_FO2_MASK
| #define GPT_CR_FO2_MASK (0x40000000U) |
Definition at line 19703 of file MIMXRT1052.h.
◆ GPT_CR_FO2_SHIFT
| #define GPT_CR_FO2_SHIFT (30U) |
Definition at line 19704 of file MIMXRT1052.h.
◆ GPT_CR_FO3
| #define GPT_CR_FO3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) |
FO3 0b0..Writing a 0 has no effect. 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
Definition at line 19712 of file MIMXRT1052.h.
◆ GPT_CR_FO3_MASK
| #define GPT_CR_FO3_MASK (0x80000000U) |
Definition at line 19706 of file MIMXRT1052.h.
◆ GPT_CR_FO3_SHIFT
| #define GPT_CR_FO3_SHIFT (31U) |
Definition at line 19707 of file MIMXRT1052.h.
◆ GPT_CR_FRR
| #define GPT_CR_FRR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) |
FRR 0b0..Restart mode 0b1..Free-Run mode
Definition at line 19657 of file MIMXRT1052.h.
◆ GPT_CR_FRR_MASK
| #define GPT_CR_FRR_MASK (0x200U) |
Definition at line 19651 of file MIMXRT1052.h.
◆ GPT_CR_FRR_SHIFT
| #define GPT_CR_FRR_SHIFT (9U) |
Definition at line 19652 of file MIMXRT1052.h.
◆ GPT_CR_IM1
| #define GPT_CR_IM1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) |
Definition at line 19674 of file MIMXRT1052.h.
◆ GPT_CR_IM1_MASK
| #define GPT_CR_IM1_MASK (0x30000U) |
Definition at line 19672 of file MIMXRT1052.h.
◆ GPT_CR_IM1_SHIFT
| #define GPT_CR_IM1_SHIFT (16U) |
Definition at line 19673 of file MIMXRT1052.h.
◆ GPT_CR_IM2
| #define GPT_CR_IM2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) |
IM2 0b00..capture disabled 0b01..capture on rising edge only 0b10..capture on falling edge only 0b11..capture on both edges
Definition at line 19683 of file MIMXRT1052.h.
◆ GPT_CR_IM2_MASK
| #define GPT_CR_IM2_MASK (0xC0000U) |
Definition at line 19675 of file MIMXRT1052.h.
◆ GPT_CR_IM2_SHIFT
| #define GPT_CR_IM2_SHIFT (18U) |
Definition at line 19676 of file MIMXRT1052.h.
◆ GPT_CR_OM1
| #define GPT_CR_OM1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) |
Definition at line 19686 of file MIMXRT1052.h.
◆ GPT_CR_OM1_MASK
| #define GPT_CR_OM1_MASK (0x700000U) |
Definition at line 19684 of file MIMXRT1052.h.
◆ GPT_CR_OM1_SHIFT
| #define GPT_CR_OM1_SHIFT (20U) |
Definition at line 19685 of file MIMXRT1052.h.
◆ GPT_CR_OM2
| #define GPT_CR_OM2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) |
Definition at line 19689 of file MIMXRT1052.h.
◆ GPT_CR_OM2_MASK
| #define GPT_CR_OM2_MASK (0x3800000U) |
Definition at line 19687 of file MIMXRT1052.h.
◆ GPT_CR_OM2_SHIFT
| #define GPT_CR_OM2_SHIFT (23U) |
Definition at line 19688 of file MIMXRT1052.h.
◆ GPT_CR_OM3
| #define GPT_CR_OM3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) |
OM3 0b000..Output disconnected. No response on pin. 0b001..Toggle output pin 0b010..Clear output pin 0b011..Set output pin 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
Definition at line 19699 of file MIMXRT1052.h.
◆ GPT_CR_OM3_MASK
| #define GPT_CR_OM3_MASK (0x1C000000U) |
Definition at line 19690 of file MIMXRT1052.h.
◆ GPT_CR_OM3_SHIFT
| #define GPT_CR_OM3_SHIFT (26U) |
Definition at line 19691 of file MIMXRT1052.h.
◆ GPT_CR_STOPEN
| #define GPT_CR_STOPEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) |
STOPEN 0b0..GPT is disabled in Stop mode. 0b1..GPT is enabled in Stop mode.
Definition at line 19639 of file MIMXRT1052.h.
◆ GPT_CR_STOPEN_MASK
| #define GPT_CR_STOPEN_MASK (0x20U) |
Definition at line 19633 of file MIMXRT1052.h.
◆ GPT_CR_STOPEN_SHIFT
| #define GPT_CR_STOPEN_SHIFT (5U) |
Definition at line 19634 of file MIMXRT1052.h.
◆ GPT_CR_SWR
| #define GPT_CR_SWR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) |
SWR 0b0..GPT is not in reset state 0b1..GPT is in reset state
Definition at line 19671 of file MIMXRT1052.h.
◆ GPT_CR_SWR_MASK
| #define GPT_CR_SWR_MASK (0x8000U) |
Definition at line 19665 of file MIMXRT1052.h.
◆ GPT_CR_SWR_SHIFT
| #define GPT_CR_SWR_SHIFT (15U) |
Definition at line 19666 of file MIMXRT1052.h.
◆ GPT_CR_WAITEN
| #define GPT_CR_WAITEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) |
WAITEN 0b0..GPT is disabled in wait mode. 0b1..GPT is enabled in wait mode.
Definition at line 19625 of file MIMXRT1052.h.
◆ GPT_CR_WAITEN_MASK
| #define GPT_CR_WAITEN_MASK (0x8U) |
Definition at line 19619 of file MIMXRT1052.h.
◆ GPT_CR_WAITEN_SHIFT
| #define GPT_CR_WAITEN_SHIFT (3U) |
Definition at line 19620 of file MIMXRT1052.h.
◆ GPT_ICR_CAPT
| #define GPT_ICR_CAPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK) |
Definition at line 19817 of file MIMXRT1052.h.
◆ GPT_ICR_CAPT_MASK
| #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) |
Definition at line 19815 of file MIMXRT1052.h.
◆ GPT_ICR_CAPT_SHIFT
| #define GPT_ICR_CAPT_SHIFT (0U) |
Definition at line 19816 of file MIMXRT1052.h.
◆ GPT_ICR_COUNT
| #define GPT_ICR_COUNT (2U) |
Definition at line 19821 of file MIMXRT1052.h.
◆ GPT_IR_IF1IE
| #define GPT_IR_IF1IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) |
Definition at line 19786 of file MIMXRT1052.h.
◆ GPT_IR_IF1IE_MASK
| #define GPT_IR_IF1IE_MASK (0x8U) |
Definition at line 19784 of file MIMXRT1052.h.
◆ GPT_IR_IF1IE_SHIFT
| #define GPT_IR_IF1IE_SHIFT (3U) |
Definition at line 19785 of file MIMXRT1052.h.
◆ GPT_IR_IF2IE
| #define GPT_IR_IF2IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) |
IF2IE 0b0..IF2IE Input Capture n Interrupt Enable is disabled. 0b1..IF2IE Input Capture n Interrupt Enable is enabled.
Definition at line 19793 of file MIMXRT1052.h.
◆ GPT_IR_IF2IE_MASK
| #define GPT_IR_IF2IE_MASK (0x10U) |
Definition at line 19787 of file MIMXRT1052.h.
◆ GPT_IR_IF2IE_SHIFT
| #define GPT_IR_IF2IE_SHIFT (4U) |
Definition at line 19788 of file MIMXRT1052.h.
◆ GPT_IR_OF1IE
| #define GPT_IR_OF1IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) |
Definition at line 19773 of file MIMXRT1052.h.
◆ GPT_IR_OF1IE_MASK
| #define GPT_IR_OF1IE_MASK (0x1U) |
Definition at line 19771 of file MIMXRT1052.h.
◆ GPT_IR_OF1IE_SHIFT
| #define GPT_IR_OF1IE_SHIFT (0U) |
Definition at line 19772 of file MIMXRT1052.h.
◆ GPT_IR_OF2IE
| #define GPT_IR_OF2IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) |
Definition at line 19776 of file MIMXRT1052.h.
◆ GPT_IR_OF2IE_MASK
| #define GPT_IR_OF2IE_MASK (0x2U) |
Definition at line 19774 of file MIMXRT1052.h.
◆ GPT_IR_OF2IE_SHIFT
| #define GPT_IR_OF2IE_SHIFT (1U) |
Definition at line 19775 of file MIMXRT1052.h.
◆ GPT_IR_OF3IE
| #define GPT_IR_OF3IE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) |
OF3IE 0b0..Output Compare Channel n interrupt is disabled. 0b1..Output Compare Channel n interrupt is enabled.
Definition at line 19783 of file MIMXRT1052.h.
◆ GPT_IR_OF3IE_MASK
| #define GPT_IR_OF3IE_MASK (0x4U) |
Definition at line 19777 of file MIMXRT1052.h.
◆ GPT_IR_OF3IE_SHIFT
| #define GPT_IR_OF3IE_SHIFT (2U) |
Definition at line 19778 of file MIMXRT1052.h.
◆ GPT_IR_ROVIE
| #define GPT_IR_ROVIE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) |
ROVIE 0b0..Rollover interrupt is disabled. 0b1..Rollover interrupt enabled.
Definition at line 19800 of file MIMXRT1052.h.
◆ GPT_IR_ROVIE_MASK
| #define GPT_IR_ROVIE_MASK (0x20U) |
Definition at line 19794 of file MIMXRT1052.h.
◆ GPT_IR_ROVIE_SHIFT
| #define GPT_IR_ROVIE_SHIFT (5U) |
Definition at line 19795 of file MIMXRT1052.h.
◆ GPT_OCR_COMP
| #define GPT_OCR_COMP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK) |
Definition at line 19807 of file MIMXRT1052.h.
◆ GPT_OCR_COMP_MASK
| #define GPT_OCR_COMP_MASK (0xFFFFFFFFU) |
Definition at line 19805 of file MIMXRT1052.h.
◆ GPT_OCR_COMP_SHIFT
| #define GPT_OCR_COMP_SHIFT (0U) |
Definition at line 19806 of file MIMXRT1052.h.
◆ GPT_OCR_COUNT
| #define GPT_OCR_COUNT (3U) |
Definition at line 19811 of file MIMXRT1052.h.
◆ GPT_PR_PRESCALER
| #define GPT_PR_PRESCALER | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) |
PRESCALER 0b000000000000..Divide by 1 0b000000000001..Divide by 2 0b111111111111..Divide by 4096
Definition at line 19724 of file MIMXRT1052.h.
◆ GPT_PR_PRESCALER24M
| #define GPT_PR_PRESCALER24M | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK) |
PRESCALER24M 0b0000..Divide by 1 0b0001..Divide by 2 0b1111..Divide by 16
Definition at line 19732 of file MIMXRT1052.h.
◆ GPT_PR_PRESCALER24M_MASK
| #define GPT_PR_PRESCALER24M_MASK (0xF000U) |
Definition at line 19725 of file MIMXRT1052.h.
◆ GPT_PR_PRESCALER24M_SHIFT
| #define GPT_PR_PRESCALER24M_SHIFT (12U) |
Definition at line 19726 of file MIMXRT1052.h.
◆ GPT_PR_PRESCALER_MASK
| #define GPT_PR_PRESCALER_MASK (0xFFFU) |
Definition at line 19717 of file MIMXRT1052.h.
◆ GPT_PR_PRESCALER_SHIFT
| #define GPT_PR_PRESCALER_SHIFT (0U) |
Definition at line 19718 of file MIMXRT1052.h.
◆ GPT_SR_IF1
| #define GPT_SR_IF1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) |
Definition at line 19752 of file MIMXRT1052.h.
◆ GPT_SR_IF1_MASK
| #define GPT_SR_IF1_MASK (0x8U) |
Definition at line 19750 of file MIMXRT1052.h.
◆ GPT_SR_IF1_SHIFT
| #define GPT_SR_IF1_SHIFT (3U) |
Definition at line 19751 of file MIMXRT1052.h.
◆ GPT_SR_IF2
| #define GPT_SR_IF2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) |
IF2 0b0..Capture event has not occurred. 0b1..Capture event has occurred.
Definition at line 19759 of file MIMXRT1052.h.
◆ GPT_SR_IF2_MASK
| #define GPT_SR_IF2_MASK (0x10U) |
Definition at line 19753 of file MIMXRT1052.h.
◆ GPT_SR_IF2_SHIFT
| #define GPT_SR_IF2_SHIFT (4U) |
Definition at line 19754 of file MIMXRT1052.h.
◆ GPT_SR_OF1
| #define GPT_SR_OF1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) |
Definition at line 19739 of file MIMXRT1052.h.
◆ GPT_SR_OF1_MASK
| #define GPT_SR_OF1_MASK (0x1U) |
Definition at line 19737 of file MIMXRT1052.h.
◆ GPT_SR_OF1_SHIFT
| #define GPT_SR_OF1_SHIFT (0U) |
Definition at line 19738 of file MIMXRT1052.h.
◆ GPT_SR_OF2
| #define GPT_SR_OF2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) |
Definition at line 19742 of file MIMXRT1052.h.
◆ GPT_SR_OF2_MASK
| #define GPT_SR_OF2_MASK (0x2U) |
Definition at line 19740 of file MIMXRT1052.h.
◆ GPT_SR_OF2_SHIFT
| #define GPT_SR_OF2_SHIFT (1U) |
Definition at line 19741 of file MIMXRT1052.h.
◆ GPT_SR_OF3
| #define GPT_SR_OF3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) |
OF3 0b0..Compare event has not occurred. 0b1..Compare event has occurred.
Definition at line 19749 of file MIMXRT1052.h.
◆ GPT_SR_OF3_MASK
| #define GPT_SR_OF3_MASK (0x4U) |
Definition at line 19743 of file MIMXRT1052.h.
◆ GPT_SR_OF3_SHIFT
| #define GPT_SR_OF3_SHIFT (2U) |
Definition at line 19744 of file MIMXRT1052.h.
◆ GPT_SR_ROV
| #define GPT_SR_ROV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK) |
ROV 0b0..Rollover has not occurred. 0b1..Rollover has occurred.
Definition at line 19766 of file MIMXRT1052.h.
◆ GPT_SR_ROV_MASK
| #define GPT_SR_ROV_MASK (0x20U) |
Definition at line 19760 of file MIMXRT1052.h.
◆ GPT_SR_ROV_SHIFT
| #define GPT_SR_ROV_SHIFT (5U) |
Definition at line 19761 of file MIMXRT1052.h.