Macros | |
| #define | GPC_IMR_COUNT (4U) |
| #define | GPC_ISR_COUNT (4U) |
CNTR - GPC Interface control register | |
| #define | GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) |
| #define | GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) |
| #define | GPC_CNTR_MEGA_PDN_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) |
| #define | GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) |
| #define | GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) |
| #define | GPC_CNTR_MEGA_PUP_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) |
| #define | GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) |
| #define | GPC_CNTR_PDRAM0_PGE_SHIFT (22U) |
| #define | GPC_CNTR_PDRAM0_PGE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) |
IMR - IRQ masking register 1..IRQ masking register 4 | |
| #define | GPC_IMR_IMR1_MASK (0xFFFFFFFFU) |
| #define | GPC_IMR_IMR1_SHIFT (0U) |
| #define | GPC_IMR_IMR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) |
| #define | GPC_IMR_IMR2_MASK (0xFFFFFFFFU) |
| #define | GPC_IMR_IMR2_SHIFT (0U) |
| #define | GPC_IMR_IMR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) |
| #define | GPC_IMR_IMR3_MASK (0xFFFFFFFFU) |
| #define | GPC_IMR_IMR3_SHIFT (0U) |
| #define | GPC_IMR_IMR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) |
| #define | GPC_IMR_IMR4_MASK (0xFFFFFFFFU) |
| #define | GPC_IMR_IMR4_SHIFT (0U) |
| #define | GPC_IMR_IMR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) |
ISR - IRQ status resister 1..IRQ status resister 4 | |
| #define | GPC_ISR_ISR1_MASK (0xFFFFFFFFU) |
| #define | GPC_ISR_ISR1_SHIFT (0U) |
| #define | GPC_ISR_ISR1(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) |
| #define | GPC_ISR_ISR2_MASK (0xFFFFFFFFU) |
| #define | GPC_ISR_ISR2_SHIFT (0U) |
| #define | GPC_ISR_ISR2(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) |
| #define | GPC_ISR_ISR3_MASK (0xFFFFFFFFU) |
| #define | GPC_ISR_ISR3_SHIFT (0U) |
| #define | GPC_ISR_ISR3(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) |
| #define | GPC_ISR_ISR4_MASK (0xFFFFFFFFU) |
| #define | GPC_ISR_ISR4_SHIFT (0U) |
| #define | GPC_ISR_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) |
IMR5 - IRQ masking register 5 | |
| #define | GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) |
| #define | GPC_IMR5_IMR5_SHIFT (0U) |
| #define | GPC_IMR5_IMR5(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) |
ISR5 - IRQ status resister 5 | |
| #define | GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) |
| #define | GPC_ISR5_ISR4_SHIFT (0U) |
| #define | GPC_ISR5_ISR4(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) |
Detailed Description
Macro Definition Documentation
◆ GPC_CNTR_MEGA_PDN_REQ
| #define GPC_CNTR_MEGA_PDN_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PDN_REQ_SHIFT)) & GPC_CNTR_MEGA_PDN_REQ_MASK) |
MEGA_PDN_REQ 0b0..No Request 0b1..Request power down sequence
Definition at line 19023 of file MIMXRT1052.h.
◆ GPC_CNTR_MEGA_PDN_REQ_MASK
| #define GPC_CNTR_MEGA_PDN_REQ_MASK (0x4U) |
Definition at line 19017 of file MIMXRT1052.h.
◆ GPC_CNTR_MEGA_PDN_REQ_SHIFT
| #define GPC_CNTR_MEGA_PDN_REQ_SHIFT (2U) |
Definition at line 19018 of file MIMXRT1052.h.
◆ GPC_CNTR_MEGA_PUP_REQ
| #define GPC_CNTR_MEGA_PUP_REQ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_MEGA_PUP_REQ_SHIFT)) & GPC_CNTR_MEGA_PUP_REQ_MASK) |
MEGA_PUP_REQ 0b0..No Request 0b1..Request power up sequence
Definition at line 19030 of file MIMXRT1052.h.
◆ GPC_CNTR_MEGA_PUP_REQ_MASK
| #define GPC_CNTR_MEGA_PUP_REQ_MASK (0x8U) |
Definition at line 19024 of file MIMXRT1052.h.
◆ GPC_CNTR_MEGA_PUP_REQ_SHIFT
| #define GPC_CNTR_MEGA_PUP_REQ_SHIFT (3U) |
Definition at line 19025 of file MIMXRT1052.h.
◆ GPC_CNTR_PDRAM0_PGE
| #define GPC_CNTR_PDRAM0_PGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_CNTR_PDRAM0_PGE_SHIFT)) & GPC_CNTR_PDRAM0_PGE_MASK) |
PDRAM0_PGE 0b1..FlexRAM PDRAM0 domain (bank1-7) will be power down once when CPU core is power down. 0b0..FlexRAM PDRAM0 domain (bank1-7) will keep power on even if CPU core is power down.
Definition at line 19037 of file MIMXRT1052.h.
◆ GPC_CNTR_PDRAM0_PGE_MASK
| #define GPC_CNTR_PDRAM0_PGE_MASK (0x400000U) |
Definition at line 19031 of file MIMXRT1052.h.
◆ GPC_CNTR_PDRAM0_PGE_SHIFT
| #define GPC_CNTR_PDRAM0_PGE_SHIFT (22U) |
Definition at line 19032 of file MIMXRT1052.h.
◆ GPC_IMR5_IMR5
| #define GPC_IMR5_IMR5 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR5_IMR5_SHIFT)) & GPC_IMR5_IMR5_MASK) |
Definition at line 19082 of file MIMXRT1052.h.
◆ GPC_IMR5_IMR5_MASK
| #define GPC_IMR5_IMR5_MASK (0xFFFFFFFFU) |
Definition at line 19080 of file MIMXRT1052.h.
◆ GPC_IMR5_IMR5_SHIFT
| #define GPC_IMR5_IMR5_SHIFT (0U) |
Definition at line 19081 of file MIMXRT1052.h.
◆ GPC_IMR_COUNT
| #define GPC_IMR_COUNT (4U) |
Definition at line 19057 of file MIMXRT1052.h.
◆ GPC_IMR_IMR1
| #define GPC_IMR_IMR1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK) |
Definition at line 19044 of file MIMXRT1052.h.
◆ GPC_IMR_IMR1_MASK
| #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) |
Definition at line 19042 of file MIMXRT1052.h.
◆ GPC_IMR_IMR1_SHIFT
| #define GPC_IMR_IMR1_SHIFT (0U) |
Definition at line 19043 of file MIMXRT1052.h.
◆ GPC_IMR_IMR2
| #define GPC_IMR_IMR2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR2_SHIFT)) & GPC_IMR_IMR2_MASK) |
Definition at line 19047 of file MIMXRT1052.h.
◆ GPC_IMR_IMR2_MASK
| #define GPC_IMR_IMR2_MASK (0xFFFFFFFFU) |
Definition at line 19045 of file MIMXRT1052.h.
◆ GPC_IMR_IMR2_SHIFT
| #define GPC_IMR_IMR2_SHIFT (0U) |
Definition at line 19046 of file MIMXRT1052.h.
◆ GPC_IMR_IMR3
| #define GPC_IMR_IMR3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR3_SHIFT)) & GPC_IMR_IMR3_MASK) |
Definition at line 19050 of file MIMXRT1052.h.
◆ GPC_IMR_IMR3_MASK
| #define GPC_IMR_IMR3_MASK (0xFFFFFFFFU) |
Definition at line 19048 of file MIMXRT1052.h.
◆ GPC_IMR_IMR3_SHIFT
| #define GPC_IMR_IMR3_SHIFT (0U) |
Definition at line 19049 of file MIMXRT1052.h.
◆ GPC_IMR_IMR4
| #define GPC_IMR_IMR4 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK) |
Definition at line 19053 of file MIMXRT1052.h.
◆ GPC_IMR_IMR4_MASK
| #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) |
Definition at line 19051 of file MIMXRT1052.h.
◆ GPC_IMR_IMR4_SHIFT
| #define GPC_IMR_IMR4_SHIFT (0U) |
Definition at line 19052 of file MIMXRT1052.h.
◆ GPC_ISR5_ISR4
| #define GPC_ISR5_ISR4 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR5_ISR4_SHIFT)) & GPC_ISR5_ISR4_MASK) |
Definition at line 19089 of file MIMXRT1052.h.
◆ GPC_ISR5_ISR4_MASK
| #define GPC_ISR5_ISR4_MASK (0xFFFFFFFFU) |
Definition at line 19087 of file MIMXRT1052.h.
◆ GPC_ISR5_ISR4_SHIFT
| #define GPC_ISR5_ISR4_SHIFT (0U) |
Definition at line 19088 of file MIMXRT1052.h.
◆ GPC_ISR_COUNT
| #define GPC_ISR_COUNT (4U) |
Definition at line 19076 of file MIMXRT1052.h.
◆ GPC_ISR_ISR1
| #define GPC_ISR_ISR1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR1_SHIFT)) & GPC_ISR_ISR1_MASK) |
Definition at line 19063 of file MIMXRT1052.h.
◆ GPC_ISR_ISR1_MASK
| #define GPC_ISR_ISR1_MASK (0xFFFFFFFFU) |
Definition at line 19061 of file MIMXRT1052.h.
◆ GPC_ISR_ISR1_SHIFT
| #define GPC_ISR_ISR1_SHIFT (0U) |
Definition at line 19062 of file MIMXRT1052.h.
◆ GPC_ISR_ISR2
| #define GPC_ISR_ISR2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR2_SHIFT)) & GPC_ISR_ISR2_MASK) |
Definition at line 19066 of file MIMXRT1052.h.
◆ GPC_ISR_ISR2_MASK
| #define GPC_ISR_ISR2_MASK (0xFFFFFFFFU) |
Definition at line 19064 of file MIMXRT1052.h.
◆ GPC_ISR_ISR2_SHIFT
| #define GPC_ISR_ISR2_SHIFT (0U) |
Definition at line 19065 of file MIMXRT1052.h.
◆ GPC_ISR_ISR3
| #define GPC_ISR_ISR3 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR3_SHIFT)) & GPC_ISR_ISR3_MASK) |
Definition at line 19069 of file MIMXRT1052.h.
◆ GPC_ISR_ISR3_MASK
| #define GPC_ISR_ISR3_MASK (0xFFFFFFFFU) |
Definition at line 19067 of file MIMXRT1052.h.
◆ GPC_ISR_ISR3_SHIFT
| #define GPC_ISR_ISR3_SHIFT (0U) |
Definition at line 19068 of file MIMXRT1052.h.
◆ GPC_ISR_ISR4
| #define GPC_ISR_ISR4 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << GPC_ISR_ISR4_SHIFT)) & GPC_ISR_ISR4_MASK) |
Definition at line 19072 of file MIMXRT1052.h.
◆ GPC_ISR_ISR4_MASK
| #define GPC_ISR_ISR4_MASK (0xFFFFFFFFU) |
Definition at line 19070 of file MIMXRT1052.h.
◆ GPC_ISR_ISR4_SHIFT
| #define GPC_ISR_ISR4_SHIFT (0U) |
Definition at line 19071 of file MIMXRT1052.h.