sensor_epsonG370PDT0.h
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1 //==============================================================================
2 //
3 // sensor_epsonG370PDT0.h - Epson G370PDT0 sensor specific definitions
4 //
5 //
6 // THE SOFTWARE IS RELEASED INTO THE PUBLIC DOMAIN.
7 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
8 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
9 // NONINFRINGEMENT, SECURITY, SATISFACTORY QUALITY, AND FITNESS FOR A
10 // PARTICULAR PURPOSE. IN NO EVENT SHALL EPSON BE LIABLE FOR ANY LOSS, DAMAGE
11 // OR CLAIM, ARISING FROM OR IN CONNECTION WITH THE SOFTWARE OR THE USE OF THE
12 // SOFTWARE.
13 //
14 //==============================================================================
15 #ifndef EPSONG370PDT0_H_
16 #define EPSONG370PDT0_H_
17 
18 #ifdef ACCL_RANGE_16G
19 #define EPSON_ACCL_SF (.5000) // 16G
20 #else
21 #define EPSON_ACCL_SF (.2500) // 8G
22 #endif // ACCL_RANGE_16G
23 
24 #define EPSON_GYRO_SF (.006666667)
25 #define EPSON_TEMP_SF (0.00390625)
26 #define EPSON_ATTI_SF (0.0)
27 #define EPSON_COUNT_SF (16000)
28 
29 #define EPSON_DA_SF0 (EPSON_GYRO_SF * 500E-06)
30 #define EPSON_DA_SF1 (EPSON_DA_SF0 * 2)
31 #define EPSON_DA_SF2 (EPSON_DA_SF1 * 2)
32 #define EPSON_DA_SF3 (EPSON_DA_SF2 * 2)
33 #define EPSON_DA_SF4 (EPSON_DA_SF3 * 2)
34 #define EPSON_DA_SF5 (EPSON_DA_SF4 * 2)
35 #define EPSON_DA_SF6 (EPSON_DA_SF5 * 2)
36 #define EPSON_DA_SF7 (EPSON_DA_SF6 * 2)
37 #define EPSON_DA_SF8 (EPSON_DA_SF7 * 2)
38 #define EPSON_DA_SF9 (EPSON_DA_SF8 * 2)
39 #define EPSON_DA_SF10 (EPSON_DA_SF9 * 2)
40 #define EPSON_DA_SF11 (EPSON_DA_SF10 * 2)
41 #define EPSON_DA_SF12 (EPSON_DA_SF11 * 2)
42 #define EPSON_DA_SF13 (EPSON_DA_SF12 * 2)
43 #define EPSON_DA_SF14 (EPSON_DA_SF13 * 2)
44 #define EPSON_DA_SF15 (EPSON_DA_SF14 * 2)
45 
46 #define EPSON_DV_SF0 (EPSON_ACCL_SF * 1E-03 * 9.80665 * 500E-06)
47 #define EPSON_DV_SF1 (EPSON_DV_SF0 * 2)
48 #define EPSON_DV_SF2 (EPSON_DV_SF1 * 2)
49 #define EPSON_DV_SF3 (EPSON_DV_SF2 * 2)
50 #define EPSON_DV_SF4 (EPSON_DV_SF3 * 2)
51 #define EPSON_DV_SF5 (EPSON_DV_SF4 * 2)
52 #define EPSON_DV_SF6 (EPSON_DV_SF5 * 2)
53 #define EPSON_DV_SF7 (EPSON_DV_SF6 * 2)
54 #define EPSON_DV_SF8 (EPSON_DV_SF7 * 2)
55 #define EPSON_DV_SF9 (EPSON_DV_SF8 * 2)
56 #define EPSON_DV_SF10 (EPSON_DV_SF9 * 2)
57 #define EPSON_DV_SF11 (EPSON_DV_SF10 * 2)
58 #define EPSON_DV_SF12 (EPSON_DV_SF11 * 2)
59 #define EPSON_DV_SF13 (EPSON_DV_SF12 * 2)
60 #define EPSON_DV_SF14 (EPSON_DV_SF13 * 2)
61 #define EPSON_DV_SF15 (EPSON_DV_SF14 * 2)
62 
63 /* -- Commands --
64 - ADDR_ address byte of transfer to select the register to access
65 - CMD_ data byte of transfer to write to the register selected
66 
67 - All accesses are 16 bit transfers
68 - For SPI IF:
69  - For SPI write accesses - 8-bit address with msb=1b (can be even or
70  odd) + 8-bit write
71 data
72  - No response
73  - For SPI read accesses - 8-bit address with msb=0b(even only) + 8-bit
74  dummy data
75  - Response is
76 transferred on MOSI on next SPI access
77  - Return value is
78 16-bit read data (high byte + low byte)
79 - For UART IF:
80  - For UART write accesses - 8-bit address with msb=1b(can be even or
81  odd) + 8-bit write data + Delimiter Byte
82  - No response
83  - For UART read accesses - 8-bit address with msb=0b(even only) + 8-bit
84  dummy data + Delimiter Byte
85  - Response is
86 transferred immediately
87  - Return value
88 consists of Register Read Address + 16-bit read data (high byte + low byte) +
89 Delimiter Byte
90 
91 - NOTE: Register Address Maps that depend on the WINDOW_ID (page) */
92 
93 // WINDOW_ID 0
94 #define ADDR_MODE_CTRL_LO 0x02 // MODE_CTRL Byte0 (W0)
95 #define ADDR_MODE_CTRL_HI 0x03 // MODE_CTRL Byte1 (W0)
96 #define ADDR_DIAG_STAT 0x04 // DIAG_STAT Byte0 (W0)
97 #define ADDR_FLAG 0x06 // FLAG(ND/EA) (W0)
98 #define ADDR_GPIO 0x08 // GPIO (W0)
99 #define ADDR_COUNT 0x0A // COUNT (W0)
100 #define ADDR_RANGE_OVER 0x0C // RANGE_OVER (W0)
101 #define ADDR_TEMP_HIGH 0x0E // TEMPC HIGH (W0)
102 #define ADDR_TEMP_LOW 0x10 // TEMPC LOW (W0)
103 #define ADDR_XGYRO_HIGH 0x12 // XGYRO HIGH (W0)
104 #define ADDR_XGYRO_LOW 0x14 // XGYRO LOW (W0)
105 #define ADDR_YGYRO_HIGH 0x16 // YGYRO HIGH (W0)
106 #define ADDR_YGYRO_LOW 0x18 // YGYRO LOW (W0)
107 #define ADDR_ZGYRO_HIGH 0x1A // ZGYRO HIGH (W0)
108 #define ADDR_ZGYRO_LOW 0x1C // ZGYRO LOW (W0)
109 #define ADDR_XACCL_HIGH 0x1E // XACCL HIGH (W0)
110 #define ADDR_XACCL_LOW 0x20 // XACCL LOW (W0)
111 #define ADDR_YACCL_HIGH 0x22 // YACCL HIGH (W0)
112 #define ADDR_YACCL_LOW 0x24 // YACCL LOW (W0)
113 #define ADDR_ZACCL_HIGH 0x26 // ZACCL HIGH (W0)
114 #define ADDR_ZACCL_LOW 0x28 // ZACCL LOW (W0)
115 
116 #define ADDR_ID 0x4C // ID LOW (W0)
117 
118 #define ADDR_XDLTA_HIGH 0x64 // XDLTA HIGH (W0)
119 #define ADDR_XDLTA_LOW 0x66 // XDLTA LOW (W0)
120 #define ADDR_YDLTA_HIGH 0x68 // YDLTA HIGH (W0)
121 #define ADDR_YDLTA_LOW 0x6A // YDLTA LOW (W0)
122 #define ADDR_ZDLTA_HIGH 0x6C // ZDLTA HIGH (W0)
123 #define ADDR_ZDLTA_LOW 0x6E // ZDLTA LOW (W0)
124 #define ADDR_XDLTV_HIGH 0x70 // XDLTV HIGH (W0)
125 #define ADDR_XDLTV_LOW 0x72 // XDLTV LOW (W0)
126 #define ADDR_YDLTV_HIGH 0x74 // YDLTV HIGH (W0)
127 #define ADDR_YDLTV_LOW 0x76 // YDLTV LOW (W0)
128 #define ADDR_ZDLTV_HIGH 0x78 // ZDLTV HIGH (W0)
129 #define ADDR_ZDLTV_LOW 0x7A // ZDLTV LOW (W0)
130 
131 // WINDOW_ID 1
132 #define ADDR_SIG_CTRL_LO 0x00 // SIG_CTRL Byte0 (W1)
133 #define ADDR_SIG_CTRL_HI 0x01 // SIG_CTRL Byte1 (W1)
134 #define ADDR_MSC_CTRL_LO 0x02 // MSC_CTRL Byte0 (W1)
135 #define ADDR_MSC_CTRL_HI 0x03 // MSC_CTRL Byte1 (W1)
136 #define ADDR_SMPL_CTRL_LO 0x04 // SMPL_CTRL Byte0 (W1)
137 #define ADDR_SMPL_CTRL_HI 0x05 // SMPL_CTRL Byte1 (W1)
138 #define ADDR_FILTER_CTRL_LO 0x06 // FILTER_CTRL Byte0 (W1)
139 #define ADDR_FILTER_CTRL_HI 0x07 // FILTER_CTRL Byte1 (W1)
140 #define ADDR_UART_CTRL_LO 0x08 // UART_CTRL Byte0 (W1)
141 #define ADDR_UART_CTRL_HI 0x09 // UART_CTRL Byte1 (W1)
142 #define ADDR_GLOB_CMD_LO 0x0A // GLOB_CMD Byte0 (W1)
143 #define ADDR_GLOB_CMD_HI 0x0B // GLOB_CMD Byte1 (W1)
144 #define ADDR_BURST_CTRL1_LO 0x0C // BURST_CTRL1 Byte0 (W1)
145 #define ADDR_BURST_CTRL1_HI 0x0D // BURST_CTRL1 Byte1 (W1)
146 #define ADDR_BURST_CTRL2_LO 0x0E // BURST_CTRL2 Byte0 (W1)
147 #define ADDR_BURST_CTRL2_HI 0x0F // BURST_CTRL2 Byte1 (W1)
148 #define ADDR_POL_CTRL_LO 0x10 // POL_CTRL Byte0 (W1)
149 #define ADDR_POL_CTRL_HI 0x11 // POL_CTRL Byte1 (W1)
150 #define ADDR_DLT_CTRL_LO 0x12 // DLT_CTRL Byte0 (W1)
151 #define ADDR_DLT_CTRL_HI 0x13 // DLT_CTRL Byte1 (W1)
152 #define ADDR_ATTI_CTRL_LO 0x14 // ATTI_CTRL Byte0 (W1)
153 #define ADDR_ATTI_CTRL_HI 0x15 // ATTI_CTRL Byte1 (W1)
154 #define ADDR_GLOB_CMD2_LO 0x16 // ATTI_GLOB_CMD2 Byte0 (W1)
155 #define ADDR_GLOB_CMD2_HI 0x17 // ATTI_GLOB_CMD2 Byte1 (W1)
156 
157 #define R_MATRIX_M11_LO 0x38 // R_MATRIX_M11 Byte0 (W1)
158 #define R_MATRIX_M11_HI 0x39 // R_MATRIX_M11 Byte1 (W1)
159 #define R_MATRIX_M12_LO 0x3A // R_MATRIX_M12 Byte0 (W1)
160 #define R_MATRIX_M12_HI 0x3B // R_MATRIX_M12 Byte1 (W1)
161 #define R_MATRIX_M13_LO 0x3C // R_MATRIX_M13 Byte0 (W1)
162 #define R_MATRIX_M13_HI 0x3D // R_MATRIX_M13 Byte1 (W1)
163 #define R_MATRIX_M21_LO 0x3E // R_MATRIX_M21 Byte0 (W1)
164 #define R_MATRIX_M21_HI 0x3F // R_MATRIX_M21 Byte1 (W1)
165 #define R_MATRIX_M22_LO 0x40 // R_MATRIX_M22 Byte0 (W1)
166 #define R_MATRIX_M22_HI 0x41 // R_MATRIX_M22 Byte1 (W1)
167 #define R_MATRIX_M23_LO 0x42 // R_MATRIX_M23 Byte0 (W1)
168 #define R_MATRIX_M23_HI 0x43 // R_MATRIX_M23 Byte1 (W1)
169 #define R_MATRIX_M31_LO 0x44 // R_MATRIX_M31 Byte0 (W1)
170 #define R_MATRIX_M31_HI 0x45 // R_MATRIX_M31 Byte1 (W1)
171 #define R_MATRIX_M32_LO 0x46 // R_MATRIX_M32 Byte0 (W1)
172 #define R_MATRIX_M32_HI 0x47 // R_MATRIX_M32 Byte1 (W1)
173 #define R_MATRIX_M33_LO 0x48 // R_MATRIX_M33 Byte0 (W1)
174 #define R_MATRIX_M33_HI 0x49 // R_MATRIX_M33 Byte1 (W1)
175 
176 #define ADDR_PROD_ID1 0x6A // PROD_ID1(W1)
177 #define ADDR_PROD_ID2 0x6C // PROD_ID2(W1)
178 #define ADDR_PROD_ID3 0x6E // PROD_ID3(W1)
179 #define ADDR_PROD_ID4 0x70 // PROD_ID4(W1)
180 #define ADDR_VERSION 0x72 // VERSION(W1)
181 #define ADDR_SERIAL_NUM1 0x74 // SERIAL_NUM1(W1)
182 #define ADDR_SERIAL_NUM2 0x76 // SERIAL_NUM2(W1)
183 #define ADDR_SERIAL_NUM3 0x78 // SERIAL_NUM3(W1)
184 #define ADDR_SERIAL_NUM4 0x7A // SERIAL_NUM4(W1)
185 #define ADDR_WIN_CTRL 0x7E // WIN_CTRL(W0 or W1)
186 
187 #define CMD_BURST 0x80 // Write value to Issue Burst Read
188 #define CMD_WINDOW0 0x00 // Write value for WIN_CTRL to change to Window 0
189 #define CMD_WINDOW1 0x01 // Write value for WIN_CTRL to change to Window 1
190 #define CMD_BEGIN_SAMPLING \
191  0x01 // Write value for MODE_CMD_HI to begin sampling
192 #define CMD_END_SAMPLING 0x02 // Write value for MODE_CMD_HI to stop sampling
193 #define CMD_SOFTRESET \
194  0x80 // Write value for GLOB_CMD_LO to issue Software Reset
195 #define CMD_INITIAL_BACKUP \
196  0x10 // Write value for GLOB_CMD_LO to issue Initial_Backup
197 #define CMD_FLASHTEST 0x08 // Write value for MSC_CTRL_HI to issue Flashtest
198 #define CMD_SELFTEST 0x04 // Write value for MSC_CTRL_HI to issue Selftest
199 
200 // Write values for ADDR_SMPL_CTRL_HI to set Output Rate
201 #define CMD_RATE2000 0x00 // TAP>=0
202 #define CMD_RATE1000 0x01 // TAP>=2
203 #define CMD_RATE500 0x02 // TAP>=4
204 #define CMD_RATE250 0x03 // TAP>=8
205 #define CMD_RATE125 0x04 // TAP>=16
206 #define CMD_RATE62_5 0x05 // TAP>=32
207 #define CMD_RATE31_25 0x06 // TAP>=64
208 #define CMD_RATE15_625 0x07 // TAP=128
209 #define CMD_RATE400 0x08 // TAP>=8
210 #define CMD_RATE200 0x09 // TAP>=16
211 #define CMD_RATE100 0x0A // TAP>=32
212 #define CMD_RATE80 0x0B // TAP>=32
213 #define CMD_RATE50 0x0C // TAP>=64
214 #define CMD_RATE40 0x0D // TAP>=64
215 #define CMD_RATE25 0x0E // TAP=128
216 #define CMD_RATE20 0x0F // TAP=128
217 
218 // Write values for FILTER_CTRL_LO to set Filter
219 #define CMD_FLTAP0 0x00
220 #define CMD_FLTAP2 0x01
221 #define CMD_FLTAP4 0x02
222 #define CMD_FLTAP8 0x03
223 #define CMD_FLTAP16 0x04
224 #define CMD_FLTAP32 0x05
225 #define CMD_FLTAP64 0x06
226 #define CMD_FLTAP128 0x07
227 #define CMD_FIRTAP32FC50 0x08
228 #define CMD_FIRTAP32FC100 0x09
229 #define CMD_FIRTAP32FC200 0x0A
230 #define CMD_FIRTAP32FC400 0x0B
231 #define CMD_FIRTAP64FC50 0x0C
232 #define CMD_FIRTAP64FC100 0x0D
233 #define CMD_FIRTAP64FC200 0x0E
234 #define CMD_FIRTAP64FC400 0x0F
235 #define CMD_FIRTAP128FC50 0x10
236 #define CMD_FIRTAP128FC100 0x11
237 #define CMD_FIRTAP128FC200 0x12
238 #define CMD_FIRTAP128FC400 0x13
239 
240 // MODE STAT
241 #define VAL_SAMPLING_MODE 0x00
242 #define VAL_CONFIG_MODE 0x04
243 
244 #endif /* EPSONG370PDT0_H_ */

ess_imu_ros1_uart_driver
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autogenerated on Sun Dec 3 2023 03:11:33