Go to the documentation of this file. 35 #ifndef _SAME70_XDMAC_INSTANCE_ 36 #define _SAME70_XDMAC_INSTANCE_ 39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 #define REG_XDMAC_GTYPE (0x40078000U) 41 #define REG_XDMAC_GCFG (0x40078004U) 42 #define REG_XDMAC_GWAC (0x40078008U) 43 #define REG_XDMAC_GIE (0x4007800CU) 44 #define REG_XDMAC_GID (0x40078010U) 45 #define REG_XDMAC_GIM (0x40078014U) 46 #define REG_XDMAC_GIS (0x40078018U) 47 #define REG_XDMAC_GE (0x4007801CU) 48 #define REG_XDMAC_GD (0x40078020U) 49 #define REG_XDMAC_GS (0x40078024U) 50 #define REG_XDMAC_GRS (0x40078028U) 51 #define REG_XDMAC_GWS (0x4007802CU) 52 #define REG_XDMAC_GRWS (0x40078030U) 53 #define REG_XDMAC_GRWR (0x40078034U) 54 #define REG_XDMAC_GSWR (0x40078038U) 55 #define REG_XDMAC_GSWS (0x4007803CU) 56 #define REG_XDMAC_GSWF (0x40078040U) 57 #define REG_XDMAC_CIE0 (0x40078050U) 58 #define REG_XDMAC_CID0 (0x40078054U) 59 #define REG_XDMAC_CIM0 (0x40078058U) 60 #define REG_XDMAC_CIS0 (0x4007805CU) 61 #define REG_XDMAC_CSA0 (0x40078060U) 62 #define REG_XDMAC_CDA0 (0x40078064U) 63 #define REG_XDMAC_CNDA0 (0x40078068U) 64 #define REG_XDMAC_CNDC0 (0x4007806CU) 65 #define REG_XDMAC_CUBC0 (0x40078070U) 66 #define REG_XDMAC_CBC0 (0x40078074U) 67 #define REG_XDMAC_CC0 (0x40078078U) 68 #define REG_XDMAC_CDS_MSP0 (0x4007807CU) 69 #define REG_XDMAC_CSUS0 (0x40078080U) 70 #define REG_XDMAC_CDUS0 (0x40078084U) 71 #define REG_XDMAC_CIE1 (0x40078090U) 72 #define REG_XDMAC_CID1 (0x40078094U) 73 #define REG_XDMAC_CIM1 (0x40078098U) 74 #define REG_XDMAC_CIS1 (0x4007809CU) 75 #define REG_XDMAC_CSA1 (0x400780A0U) 76 #define REG_XDMAC_CDA1 (0x400780A4U) 77 #define REG_XDMAC_CNDA1 (0x400780A8U) 78 #define REG_XDMAC_CNDC1 (0x400780ACU) 79 #define REG_XDMAC_CUBC1 (0x400780B0U) 80 #define REG_XDMAC_CBC1 (0x400780B4U) 81 #define REG_XDMAC_CC1 (0x400780B8U) 82 #define REG_XDMAC_CDS_MSP1 (0x400780BCU) 83 #define REG_XDMAC_CSUS1 (0x400780C0U) 84 #define REG_XDMAC_CDUS1 (0x400780C4U) 85 #define REG_XDMAC_CIE2 (0x400780D0U) 86 #define REG_XDMAC_CID2 (0x400780D4U) 87 #define REG_XDMAC_CIM2 (0x400780D8U) 88 #define REG_XDMAC_CIS2 (0x400780DCU) 89 #define REG_XDMAC_CSA2 (0x400780E0U) 90 #define REG_XDMAC_CDA2 (0x400780E4U) 91 #define REG_XDMAC_CNDA2 (0x400780E8U) 92 #define REG_XDMAC_CNDC2 (0x400780ECU) 93 #define REG_XDMAC_CUBC2 (0x400780F0U) 94 #define REG_XDMAC_CBC2 (0x400780F4U) 95 #define REG_XDMAC_CC2 (0x400780F8U) 96 #define REG_XDMAC_CDS_MSP2 (0x400780FCU) 97 #define REG_XDMAC_CSUS2 (0x40078100U) 98 #define REG_XDMAC_CDUS2 (0x40078104U) 99 #define REG_XDMAC_CIE3 (0x40078110U) 100 #define REG_XDMAC_CID3 (0x40078114U) 101 #define REG_XDMAC_CIM3 (0x40078118U) 102 #define REG_XDMAC_CIS3 (0x4007811CU) 103 #define REG_XDMAC_CSA3 (0x40078120U) 104 #define REG_XDMAC_CDA3 (0x40078124U) 105 #define REG_XDMAC_CNDA3 (0x40078128U) 106 #define REG_XDMAC_CNDC3 (0x4007812CU) 107 #define REG_XDMAC_CUBC3 (0x40078130U) 108 #define REG_XDMAC_CBC3 (0x40078134U) 109 #define REG_XDMAC_CC3 (0x40078138U) 110 #define REG_XDMAC_CDS_MSP3 (0x4007813CU) 111 #define REG_XDMAC_CSUS3 (0x40078140U) 112 #define REG_XDMAC_CDUS3 (0x40078144U) 113 #define REG_XDMAC_CIE4 (0x40078150U) 114 #define REG_XDMAC_CID4 (0x40078154U) 115 #define REG_XDMAC_CIM4 (0x40078158U) 116 #define REG_XDMAC_CIS4 (0x4007815CU) 117 #define REG_XDMAC_CSA4 (0x40078160U) 118 #define REG_XDMAC_CDA4 (0x40078164U) 119 #define REG_XDMAC_CNDA4 (0x40078168U) 120 #define REG_XDMAC_CNDC4 (0x4007816CU) 121 #define REG_XDMAC_CUBC4 (0x40078170U) 122 #define REG_XDMAC_CBC4 (0x40078174U) 123 #define REG_XDMAC_CC4 (0x40078178U) 124 #define REG_XDMAC_CDS_MSP4 (0x4007817CU) 125 #define REG_XDMAC_CSUS4 (0x40078180U) 126 #define REG_XDMAC_CDUS4 (0x40078184U) 127 #define REG_XDMAC_CIE5 (0x40078190U) 128 #define REG_XDMAC_CID5 (0x40078194U) 129 #define REG_XDMAC_CIM5 (0x40078198U) 130 #define REG_XDMAC_CIS5 (0x4007819CU) 131 #define REG_XDMAC_CSA5 (0x400781A0U) 132 #define REG_XDMAC_CDA5 (0x400781A4U) 133 #define REG_XDMAC_CNDA5 (0x400781A8U) 134 #define REG_XDMAC_CNDC5 (0x400781ACU) 135 #define REG_XDMAC_CUBC5 (0x400781B0U) 136 #define REG_XDMAC_CBC5 (0x400781B4U) 137 #define REG_XDMAC_CC5 (0x400781B8U) 138 #define REG_XDMAC_CDS_MSP5 (0x400781BCU) 139 #define REG_XDMAC_CSUS5 (0x400781C0U) 140 #define REG_XDMAC_CDUS5 (0x400781C4U) 141 #define REG_XDMAC_CIE6 (0x400781D0U) 142 #define REG_XDMAC_CID6 (0x400781D4U) 143 #define REG_XDMAC_CIM6 (0x400781D8U) 144 #define REG_XDMAC_CIS6 (0x400781DCU) 145 #define REG_XDMAC_CSA6 (0x400781E0U) 146 #define REG_XDMAC_CDA6 (0x400781E4U) 147 #define REG_XDMAC_CNDA6 (0x400781E8U) 148 #define REG_XDMAC_CNDC6 (0x400781ECU) 149 #define REG_XDMAC_CUBC6 (0x400781F0U) 150 #define REG_XDMAC_CBC6 (0x400781F4U) 151 #define REG_XDMAC_CC6 (0x400781F8U) 152 #define REG_XDMAC_CDS_MSP6 (0x400781FCU) 153 #define REG_XDMAC_CSUS6 (0x40078200U) 154 #define REG_XDMAC_CDUS6 (0x40078204U) 155 #define REG_XDMAC_CIE7 (0x40078210U) 156 #define REG_XDMAC_CID7 (0x40078214U) 157 #define REG_XDMAC_CIM7 (0x40078218U) 158 #define REG_XDMAC_CIS7 (0x4007821CU) 159 #define REG_XDMAC_CSA7 (0x40078220U) 160 #define REG_XDMAC_CDA7 (0x40078224U) 161 #define REG_XDMAC_CNDA7 (0x40078228U) 162 #define REG_XDMAC_CNDC7 (0x4007822CU) 163 #define REG_XDMAC_CUBC7 (0x40078230U) 164 #define REG_XDMAC_CBC7 (0x40078234U) 165 #define REG_XDMAC_CC7 (0x40078238U) 166 #define REG_XDMAC_CDS_MSP7 (0x4007823CU) 167 #define REG_XDMAC_CSUS7 (0x40078240U) 168 #define REG_XDMAC_CDUS7 (0x40078244U) 169 #define REG_XDMAC_CIE8 (0x40078250U) 170 #define REG_XDMAC_CID8 (0x40078254U) 171 #define REG_XDMAC_CIM8 (0x40078258U) 172 #define REG_XDMAC_CIS8 (0x4007825CU) 173 #define REG_XDMAC_CSA8 (0x40078260U) 174 #define REG_XDMAC_CDA8 (0x40078264U) 175 #define REG_XDMAC_CNDA8 (0x40078268U) 176 #define REG_XDMAC_CNDC8 (0x4007826CU) 177 #define REG_XDMAC_CUBC8 (0x40078270U) 178 #define REG_XDMAC_CBC8 (0x40078274U) 179 #define REG_XDMAC_CC8 (0x40078278U) 180 #define REG_XDMAC_CDS_MSP8 (0x4007827CU) 181 #define REG_XDMAC_CSUS8 (0x40078280U) 182 #define REG_XDMAC_CDUS8 (0x40078284U) 183 #define REG_XDMAC_CIE9 (0x40078290U) 184 #define REG_XDMAC_CID9 (0x40078294U) 185 #define REG_XDMAC_CIM9 (0x40078298U) 186 #define REG_XDMAC_CIS9 (0x4007829CU) 187 #define REG_XDMAC_CSA9 (0x400782A0U) 188 #define REG_XDMAC_CDA9 (0x400782A4U) 189 #define REG_XDMAC_CNDA9 (0x400782A8U) 190 #define REG_XDMAC_CNDC9 (0x400782ACU) 191 #define REG_XDMAC_CUBC9 (0x400782B0U) 192 #define REG_XDMAC_CBC9 (0x400782B4U) 193 #define REG_XDMAC_CC9 (0x400782B8U) 194 #define REG_XDMAC_CDS_MSP9 (0x400782BCU) 195 #define REG_XDMAC_CSUS9 (0x400782C0U) 196 #define REG_XDMAC_CDUS9 (0x400782C4U) 197 #define REG_XDMAC_CIE10 (0x400782D0U) 198 #define REG_XDMAC_CID10 (0x400782D4U) 199 #define REG_XDMAC_CIM10 (0x400782D8U) 200 #define REG_XDMAC_CIS10 (0x400782DCU) 201 #define REG_XDMAC_CSA10 (0x400782E0U) 202 #define REG_XDMAC_CDA10 (0x400782E4U) 203 #define REG_XDMAC_CNDA10 (0x400782E8U) 204 #define REG_XDMAC_CNDC10 (0x400782ECU) 205 #define REG_XDMAC_CUBC10 (0x400782F0U) 206 #define REG_XDMAC_CBC10 (0x400782F4U) 207 #define REG_XDMAC_CC10 (0x400782F8U) 208 #define REG_XDMAC_CDS_MSP10 (0x400782FCU) 209 #define REG_XDMAC_CSUS10 (0x40078300U) 210 #define REG_XDMAC_CDUS10 (0x40078304U) 211 #define REG_XDMAC_CIE11 (0x40078310U) 212 #define REG_XDMAC_CID11 (0x40078314U) 213 #define REG_XDMAC_CIM11 (0x40078318U) 214 #define REG_XDMAC_CIS11 (0x4007831CU) 215 #define REG_XDMAC_CSA11 (0x40078320U) 216 #define REG_XDMAC_CDA11 (0x40078324U) 217 #define REG_XDMAC_CNDA11 (0x40078328U) 218 #define REG_XDMAC_CNDC11 (0x4007832CU) 219 #define REG_XDMAC_CUBC11 (0x40078330U) 220 #define REG_XDMAC_CBC11 (0x40078334U) 221 #define REG_XDMAC_CC11 (0x40078338U) 222 #define REG_XDMAC_CDS_MSP11 (0x4007833CU) 223 #define REG_XDMAC_CSUS11 (0x40078340U) 224 #define REG_XDMAC_CDUS11 (0x40078344U) 225 #define REG_XDMAC_CIE12 (0x40078350U) 226 #define REG_XDMAC_CID12 (0x40078354U) 227 #define REG_XDMAC_CIM12 (0x40078358U) 228 #define REG_XDMAC_CIS12 (0x4007835CU) 229 #define REG_XDMAC_CSA12 (0x40078360U) 230 #define REG_XDMAC_CDA12 (0x40078364U) 231 #define REG_XDMAC_CNDA12 (0x40078368U) 232 #define REG_XDMAC_CNDC12 (0x4007836CU) 233 #define REG_XDMAC_CUBC12 (0x40078370U) 234 #define REG_XDMAC_CBC12 (0x40078374U) 235 #define REG_XDMAC_CC12 (0x40078378U) 236 #define REG_XDMAC_CDS_MSP12 (0x4007837CU) 237 #define REG_XDMAC_CSUS12 (0x40078380U) 238 #define REG_XDMAC_CDUS12 (0x40078384U) 239 #define REG_XDMAC_CIE13 (0x40078390U) 240 #define REG_XDMAC_CID13 (0x40078394U) 241 #define REG_XDMAC_CIM13 (0x40078398U) 242 #define REG_XDMAC_CIS13 (0x4007839CU) 243 #define REG_XDMAC_CSA13 (0x400783A0U) 244 #define REG_XDMAC_CDA13 (0x400783A4U) 245 #define REG_XDMAC_CNDA13 (0x400783A8U) 246 #define REG_XDMAC_CNDC13 (0x400783ACU) 247 #define REG_XDMAC_CUBC13 (0x400783B0U) 248 #define REG_XDMAC_CBC13 (0x400783B4U) 249 #define REG_XDMAC_CC13 (0x400783B8U) 250 #define REG_XDMAC_CDS_MSP13 (0x400783BCU) 251 #define REG_XDMAC_CSUS13 (0x400783C0U) 252 #define REG_XDMAC_CDUS13 (0x400783C4U) 253 #define REG_XDMAC_CIE14 (0x400783D0U) 254 #define REG_XDMAC_CID14 (0x400783D4U) 255 #define REG_XDMAC_CIM14 (0x400783D8U) 256 #define REG_XDMAC_CIS14 (0x400783DCU) 257 #define REG_XDMAC_CSA14 (0x400783E0U) 258 #define REG_XDMAC_CDA14 (0x400783E4U) 259 #define REG_XDMAC_CNDA14 (0x400783E8U) 260 #define REG_XDMAC_CNDC14 (0x400783ECU) 261 #define REG_XDMAC_CUBC14 (0x400783F0U) 262 #define REG_XDMAC_CBC14 (0x400783F4U) 263 #define REG_XDMAC_CC14 (0x400783F8U) 264 #define REG_XDMAC_CDS_MSP14 (0x400783FCU) 265 #define REG_XDMAC_CSUS14 (0x40078400U) 266 #define REG_XDMAC_CDUS14 (0x40078404U) 267 #define REG_XDMAC_CIE15 (0x40078410U) 268 #define REG_XDMAC_CID15 (0x40078414U) 269 #define REG_XDMAC_CIM15 (0x40078418U) 270 #define REG_XDMAC_CIS15 (0x4007841CU) 271 #define REG_XDMAC_CSA15 (0x40078420U) 272 #define REG_XDMAC_CDA15 (0x40078424U) 273 #define REG_XDMAC_CNDA15 (0x40078428U) 274 #define REG_XDMAC_CNDC15 (0x4007842CU) 275 #define REG_XDMAC_CUBC15 (0x40078430U) 276 #define REG_XDMAC_CBC15 (0x40078434U) 277 #define REG_XDMAC_CC15 (0x40078438U) 278 #define REG_XDMAC_CDS_MSP15 (0x4007843CU) 279 #define REG_XDMAC_CSUS15 (0x40078440U) 280 #define REG_XDMAC_CDUS15 (0x40078444U) 281 #define REG_XDMAC_CIE16 (0x40078450U) 282 #define REG_XDMAC_CID16 (0x40078454U) 283 #define REG_XDMAC_CIM16 (0x40078458U) 284 #define REG_XDMAC_CIS16 (0x4007845CU) 285 #define REG_XDMAC_CSA16 (0x40078460U) 286 #define REG_XDMAC_CDA16 (0x40078464U) 287 #define REG_XDMAC_CNDA16 (0x40078468U) 288 #define REG_XDMAC_CNDC16 (0x4007846CU) 289 #define REG_XDMAC_CUBC16 (0x40078470U) 290 #define REG_XDMAC_CBC16 (0x40078474U) 291 #define REG_XDMAC_CC16 (0x40078478U) 292 #define REG_XDMAC_CDS_MSP16 (0x4007847CU) 293 #define REG_XDMAC_CSUS16 (0x40078480U) 294 #define REG_XDMAC_CDUS16 (0x40078484U) 295 #define REG_XDMAC_CIE17 (0x40078490U) 296 #define REG_XDMAC_CID17 (0x40078494U) 297 #define REG_XDMAC_CIM17 (0x40078498U) 298 #define REG_XDMAC_CIS17 (0x4007849CU) 299 #define REG_XDMAC_CSA17 (0x400784A0U) 300 #define REG_XDMAC_CDA17 (0x400784A4U) 301 #define REG_XDMAC_CNDA17 (0x400784A8U) 302 #define REG_XDMAC_CNDC17 (0x400784ACU) 303 #define REG_XDMAC_CUBC17 (0x400784B0U) 304 #define REG_XDMAC_CBC17 (0x400784B4U) 305 #define REG_XDMAC_CC17 (0x400784B8U) 306 #define REG_XDMAC_CDS_MSP17 (0x400784BCU) 307 #define REG_XDMAC_CSUS17 (0x400784C0U) 308 #define REG_XDMAC_CDUS17 (0x400784C4U) 309 #define REG_XDMAC_CIE18 (0x400784D0U) 310 #define REG_XDMAC_CID18 (0x400784D4U) 311 #define REG_XDMAC_CIM18 (0x400784D8U) 312 #define REG_XDMAC_CIS18 (0x400784DCU) 313 #define REG_XDMAC_CSA18 (0x400784E0U) 314 #define REG_XDMAC_CDA18 (0x400784E4U) 315 #define REG_XDMAC_CNDA18 (0x400784E8U) 316 #define REG_XDMAC_CNDC18 (0x400784ECU) 317 #define REG_XDMAC_CUBC18 (0x400784F0U) 318 #define REG_XDMAC_CBC18 (0x400784F4U) 319 #define REG_XDMAC_CC18 (0x400784F8U) 320 #define REG_XDMAC_CDS_MSP18 (0x400784FCU) 321 #define REG_XDMAC_CSUS18 (0x40078500U) 322 #define REG_XDMAC_CDUS18 (0x40078504U) 323 #define REG_XDMAC_CIE19 (0x40078510U) 324 #define REG_XDMAC_CID19 (0x40078514U) 325 #define REG_XDMAC_CIM19 (0x40078518U) 326 #define REG_XDMAC_CIS19 (0x4007851CU) 327 #define REG_XDMAC_CSA19 (0x40078520U) 328 #define REG_XDMAC_CDA19 (0x40078524U) 329 #define REG_XDMAC_CNDA19 (0x40078528U) 330 #define REG_XDMAC_CNDC19 (0x4007852CU) 331 #define REG_XDMAC_CUBC19 (0x40078530U) 332 #define REG_XDMAC_CBC19 (0x40078534U) 333 #define REG_XDMAC_CC19 (0x40078538U) 334 #define REG_XDMAC_CDS_MSP19 (0x4007853CU) 335 #define REG_XDMAC_CSUS19 (0x40078540U) 336 #define REG_XDMAC_CDUS19 (0x40078544U) 337 #define REG_XDMAC_CIE20 (0x40078550U) 338 #define REG_XDMAC_CID20 (0x40078554U) 339 #define REG_XDMAC_CIM20 (0x40078558U) 340 #define REG_XDMAC_CIS20 (0x4007855CU) 341 #define REG_XDMAC_CSA20 (0x40078560U) 342 #define REG_XDMAC_CDA20 (0x40078564U) 343 #define REG_XDMAC_CNDA20 (0x40078568U) 344 #define REG_XDMAC_CNDC20 (0x4007856CU) 345 #define REG_XDMAC_CUBC20 (0x40078570U) 346 #define REG_XDMAC_CBC20 (0x40078574U) 347 #define REG_XDMAC_CC20 (0x40078578U) 348 #define REG_XDMAC_CDS_MSP20 (0x4007857CU) 349 #define REG_XDMAC_CSUS20 (0x40078580U) 350 #define REG_XDMAC_CDUS20 (0x40078584U) 351 #define REG_XDMAC_CIE21 (0x40078590U) 352 #define REG_XDMAC_CID21 (0x40078594U) 353 #define REG_XDMAC_CIM21 (0x40078598U) 354 #define REG_XDMAC_CIS21 (0x4007859CU) 355 #define REG_XDMAC_CSA21 (0x400785A0U) 356 #define REG_XDMAC_CDA21 (0x400785A4U) 357 #define REG_XDMAC_CNDA21 (0x400785A8U) 358 #define REG_XDMAC_CNDC21 (0x400785ACU) 359 #define REG_XDMAC_CUBC21 (0x400785B0U) 360 #define REG_XDMAC_CBC21 (0x400785B4U) 361 #define REG_XDMAC_CC21 (0x400785B8U) 362 #define REG_XDMAC_CDS_MSP21 (0x400785BCU) 363 #define REG_XDMAC_CSUS21 (0x400785C0U) 364 #define REG_XDMAC_CDUS21 (0x400785C4U) 365 #define REG_XDMAC_CIE22 (0x400785D0U) 366 #define REG_XDMAC_CID22 (0x400785D4U) 367 #define REG_XDMAC_CIM22 (0x400785D8U) 368 #define REG_XDMAC_CIS22 (0x400785DCU) 369 #define REG_XDMAC_CSA22 (0x400785E0U) 370 #define REG_XDMAC_CDA22 (0x400785E4U) 371 #define REG_XDMAC_CNDA22 (0x400785E8U) 372 #define REG_XDMAC_CNDC22 (0x400785ECU) 373 #define REG_XDMAC_CUBC22 (0x400785F0U) 374 #define REG_XDMAC_CBC22 (0x400785F4U) 375 #define REG_XDMAC_CC22 (0x400785F8U) 376 #define REG_XDMAC_CDS_MSP22 (0x400785FCU) 377 #define REG_XDMAC_CSUS22 (0x40078600U) 378 #define REG_XDMAC_CDUS22 (0x40078604U) 379 #define REG_XDMAC_CIE23 (0x40078610U) 380 #define REG_XDMAC_CID23 (0x40078614U) 381 #define REG_XDMAC_CIM23 (0x40078618U) 382 #define REG_XDMAC_CIS23 (0x4007861CU) 383 #define REG_XDMAC_CSA23 (0x40078620U) 384 #define REG_XDMAC_CDA23 (0x40078624U) 385 #define REG_XDMAC_CNDA23 (0x40078628U) 386 #define REG_XDMAC_CNDC23 (0x4007862CU) 387 #define REG_XDMAC_CUBC23 (0x40078630U) 388 #define REG_XDMAC_CBC23 (0x40078634U) 389 #define REG_XDMAC_CC23 (0x40078638U) 390 #define REG_XDMAC_CDS_MSP23 (0x4007863CU) 391 #define REG_XDMAC_CSUS23 (0x40078640U) 392 #define REG_XDMAC_CDUS23 (0x40078644U) 393 #define REG_XDMAC_VERSION (0x40078FFCU) 395 #define REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) 396 #define REG_XDMAC_GCFG (*(__IO uint32_t*)0x40078004U) 397 #define REG_XDMAC_GWAC (*(__I uint32_t*)0x40078008U) 398 #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) 399 #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) 400 #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) 401 #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) 402 #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) 403 #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) 404 #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) 405 #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) 406 #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) 407 #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) 408 #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) 409 #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) 410 #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) 411 #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) 412 #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) 413 #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) 414 #define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) 415 #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) 416 #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) 417 #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) 418 #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) 419 #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) 420 #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) 421 #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) 422 #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) 423 #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) 424 #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) 425 #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) 426 #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) 427 #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) 428 #define REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) 429 #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) 430 #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) 431 #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) 432 #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) 433 #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) 434 #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) 435 #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) 436 #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) 437 #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) 438 #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) 439 #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) 440 #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) 441 #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) 442 #define REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) 443 #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) 444 #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) 445 #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) 446 #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) 447 #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) 448 #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) 449 #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) 450 #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) 451 #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) 452 #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) 453 #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) 454 #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) 455 #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) 456 #define REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) 457 #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) 458 #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) 459 #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) 460 #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) 461 #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) 462 #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) 463 #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) 464 #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) 465 #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) 466 #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) 467 #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) 468 #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) 469 #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) 470 #define REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) 471 #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) 472 #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) 473 #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) 474 #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) 475 #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) 476 #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) 477 #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) 478 #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) 479 #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) 480 #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) 481 #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) 482 #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) 483 #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) 484 #define REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) 485 #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) 486 #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) 487 #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) 488 #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) 489 #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) 490 #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) 491 #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) 492 #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) 493 #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) 494 #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) 495 #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) 496 #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) 497 #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) 498 #define REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) 499 #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) 500 #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) 501 #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) 502 #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) 503 #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) 504 #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) 505 #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) 506 #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) 507 #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) 508 #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) 509 #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) 510 #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) 511 #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) 512 #define REG_XDMAC_CIM7 (*(__I uint32_t*)0x40078218U) 513 #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) 514 #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) 515 #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) 516 #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) 517 #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) 518 #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) 519 #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) 520 #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) 521 #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) 522 #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) 523 #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) 524 #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) 525 #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) 526 #define REG_XDMAC_CIM8 (*(__I uint32_t*)0x40078258U) 527 #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) 528 #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) 529 #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) 530 #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) 531 #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) 532 #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) 533 #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) 534 #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) 535 #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) 536 #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) 537 #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) 538 #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) 539 #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) 540 #define REG_XDMAC_CIM9 (*(__I uint32_t*)0x40078298U) 541 #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) 542 #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) 543 #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) 544 #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) 545 #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) 546 #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) 547 #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) 548 #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) 549 #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) 550 #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) 551 #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) 552 #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) 553 #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) 554 #define REG_XDMAC_CIM10 (*(__I uint32_t*)0x400782D8U) 555 #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) 556 #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) 557 #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) 558 #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) 559 #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) 560 #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) 561 #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) 562 #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) 563 #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) 564 #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) 565 #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) 566 #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) 567 #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) 568 #define REG_XDMAC_CIM11 (*(__I uint32_t*)0x40078318U) 569 #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) 570 #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) 571 #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) 572 #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) 573 #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) 574 #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) 575 #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) 576 #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) 577 #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) 578 #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) 579 #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) 580 #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) 581 #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) 582 #define REG_XDMAC_CIM12 (*(__I uint32_t*)0x40078358U) 583 #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) 584 #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) 585 #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) 586 #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) 587 #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) 588 #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) 589 #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) 590 #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) 591 #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) 592 #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) 593 #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) 594 #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) 595 #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) 596 #define REG_XDMAC_CIM13 (*(__I uint32_t*)0x40078398U) 597 #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) 598 #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) 599 #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) 600 #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) 601 #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) 602 #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) 603 #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) 604 #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) 605 #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) 606 #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) 607 #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) 608 #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) 609 #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) 610 #define REG_XDMAC_CIM14 (*(__I uint32_t*)0x400783D8U) 611 #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) 612 #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) 613 #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) 614 #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) 615 #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) 616 #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) 617 #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) 618 #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) 619 #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) 620 #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) 621 #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) 622 #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) 623 #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) 624 #define REG_XDMAC_CIM15 (*(__I uint32_t*)0x40078418U) 625 #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) 626 #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) 627 #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) 628 #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) 629 #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) 630 #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) 631 #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) 632 #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) 633 #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) 634 #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) 635 #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) 636 #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) 637 #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) 638 #define REG_XDMAC_CIM16 (*(__I uint32_t*)0x40078458U) 639 #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) 640 #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) 641 #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) 642 #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) 643 #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) 644 #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) 645 #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) 646 #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) 647 #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) 648 #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) 649 #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) 650 #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) 651 #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) 652 #define REG_XDMAC_CIM17 (*(__I uint32_t*)0x40078498U) 653 #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) 654 #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) 655 #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) 656 #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) 657 #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) 658 #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) 659 #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) 660 #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) 661 #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) 662 #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) 663 #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) 664 #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) 665 #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) 666 #define REG_XDMAC_CIM18 (*(__I uint32_t*)0x400784D8U) 667 #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) 668 #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) 669 #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) 670 #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) 671 #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) 672 #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) 673 #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) 674 #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) 675 #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) 676 #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) 677 #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) 678 #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) 679 #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) 680 #define REG_XDMAC_CIM19 (*(__I uint32_t*)0x40078518U) 681 #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) 682 #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) 683 #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) 684 #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) 685 #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) 686 #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) 687 #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) 688 #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) 689 #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) 690 #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) 691 #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) 692 #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) 693 #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) 694 #define REG_XDMAC_CIM20 (*(__I uint32_t*)0x40078558U) 695 #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) 696 #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) 697 #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) 698 #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) 699 #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) 700 #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) 701 #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) 702 #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) 703 #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) 704 #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) 705 #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) 706 #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) 707 #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) 708 #define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) 709 #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) 710 #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) 711 #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) 712 #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) 713 #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) 714 #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) 715 #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) 716 #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) 717 #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) 718 #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) 719 #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) 720 #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) 721 #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) 722 #define REG_XDMAC_CIM22 (*(__I uint32_t*)0x400785D8U) 723 #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) 724 #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) 725 #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) 726 #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) 727 #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) 728 #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) 729 #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) 730 #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) 731 #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) 732 #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) 733 #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) 734 #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) 735 #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) 736 #define REG_XDMAC_CIM23 (*(__I uint32_t*)0x40078618U) 737 #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) 738 #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) 739 #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) 740 #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) 741 #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) 742 #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) 743 #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) 744 #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) 745 #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) 746 #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) 747 #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) 748 #define REG_XDMAC_VERSION (*(__IO uint32_t*)0x40078FFCU)