Go to the documentation of this file. 35 #ifndef _SAME70_TC3_INSTANCE_ 36 #define _SAME70_TC3_INSTANCE_ 39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 #define REG_TC3_CCR0 (0x40054000U) 41 #define REG_TC3_CMR0 (0x40054004U) 42 #define REG_TC3_SMMR0 (0x40054008U) 43 #define REG_TC3_RAB0 (0x4005400CU) 44 #define REG_TC3_CV0 (0x40054010U) 45 #define REG_TC3_RA0 (0x40054014U) 46 #define REG_TC3_RB0 (0x40054018U) 47 #define REG_TC3_RC0 (0x4005401CU) 48 #define REG_TC3_SR0 (0x40054020U) 49 #define REG_TC3_IER0 (0x40054024U) 50 #define REG_TC3_IDR0 (0x40054028U) 51 #define REG_TC3_IMR0 (0x4005402CU) 52 #define REG_TC3_EMR0 (0x40054030U) 53 #define REG_TC3_CCR1 (0x40054040U) 54 #define REG_TC3_CMR1 (0x40054044U) 55 #define REG_TC3_SMMR1 (0x40054048U) 56 #define REG_TC3_RAB1 (0x4005404CU) 57 #define REG_TC3_CV1 (0x40054050U) 58 #define REG_TC3_RA1 (0x40054054U) 59 #define REG_TC3_RB1 (0x40054058U) 60 #define REG_TC3_RC1 (0x4005405CU) 61 #define REG_TC3_SR1 (0x40054060U) 62 #define REG_TC3_IER1 (0x40054064U) 63 #define REG_TC3_IDR1 (0x40054068U) 64 #define REG_TC3_IMR1 (0x4005406CU) 65 #define REG_TC3_EMR1 (0x40054070U) 66 #define REG_TC3_CCR2 (0x40054080U) 67 #define REG_TC3_CMR2 (0x40054084U) 68 #define REG_TC3_SMMR2 (0x40054088U) 69 #define REG_TC3_RAB2 (0x4005408CU) 70 #define REG_TC3_CV2 (0x40054090U) 71 #define REG_TC3_RA2 (0x40054094U) 72 #define REG_TC3_RB2 (0x40054098U) 73 #define REG_TC3_RC2 (0x4005409CU) 74 #define REG_TC3_SR2 (0x400540A0U) 75 #define REG_TC3_IER2 (0x400540A4U) 76 #define REG_TC3_IDR2 (0x400540A8U) 77 #define REG_TC3_IMR2 (0x400540ACU) 78 #define REG_TC3_EMR2 (0x400540B0U) 79 #define REG_TC3_BCR (0x400540C0U) 80 #define REG_TC3_BMR (0x400540C4U) 81 #define REG_TC3_QIER (0x400540C8U) 82 #define REG_TC3_QIDR (0x400540CCU) 83 #define REG_TC3_QIMR (0x400540D0U) 84 #define REG_TC3_QISR (0x400540D4U) 85 #define REG_TC3_FMR (0x400540D8U) 86 #define REG_TC3_WPMR (0x400540E4U) 87 #define REG_TC3_VER (0x400540FCU) 89 #define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) 90 #define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) 91 #define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) 92 #define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) 93 #define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) 94 #define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) 95 #define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) 96 #define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) 97 #define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) 98 #define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) 99 #define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) 100 #define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) 101 #define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) 102 #define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) 103 #define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) 104 #define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) 105 #define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) 106 #define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) 107 #define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) 108 #define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) 109 #define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) 110 #define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) 111 #define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) 112 #define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) 113 #define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) 114 #define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) 115 #define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) 116 #define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) 117 #define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) 118 #define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) 119 #define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) 120 #define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) 121 #define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) 122 #define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) 123 #define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) 124 #define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) 125 #define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) 126 #define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) 127 #define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) 128 #define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) 129 #define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) 130 #define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) 131 #define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) 132 #define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) 133 #define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) 134 #define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) 135 #define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) 136 #define REG_TC3_VER (*(__I uint32_t*)0x400540FCU)