Advanced use case - Peripheral Bus

Management (SAMV71)

Advanced use case - Peripheral Bus

Clock Management This section will present a more advanced use case for the System Clock Management service. This use case will configure the main system clock to 96MHz, using an internal PLL module to multiply the frequency of a crystal attached to the microcontroller. The USB clock will be configured via the same PLL module.

Prerequisites

• None

Initialization code

Add to the application initialization code:

sysclk_init();

Workflow

1. Configure the system clocks according to the settings in conf_clock.h:

   sysclk_init(); 

Example code

Add or uncomment the following in your conf_clock.h header file, commenting out all other definitions of the same symbol(s):

#define CONFIG_SYSCLK_SOURCE        SYSCLK_SRC_PLLACK

// Fpll0 = (Fclk * PLL_mul) / PLL_div
#define CONFIG_PLL0_SOURCE          PLL_SRC_MAINCK_XTAL
#define CONFIG_PLL0_MUL             (96000000UL / BOARD_FREQ_MAINCK_XTAL)
#define CONFIG_PLL0_DIV             1

// Fbus = Fsys / BUS_div
#define CONFIG_SYSCLK_PRES          SYSCLK_PRES_1

// Fusb = Fsys / USB_div
#define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL0
#define CONFIG_USBCLK_DIV           2

Workflow

1. Configure the main system clock to use the output of the PLL0 module as its source:

   #define CONFIG_SYSCLK_SOURCE          SYSCLK_SRC_PLLACK 

2. Configure the PLL0 module to use the fast external fast crystal oscillator as its source:

   #define CONFIG_PLL0_SOURCE            PLL_SRC_MAINCK_XTAL 

3. Configure the PLL0 module to multiply the external fast crystal oscillator frequency up to 96MHz:

   #define CONFIG_PLL0_MUL             (96000000UL / BOARD_FREQ_MAINCK_XTAL)
   #define CONFIG_PLL0_DIV             1

   Note

   For user boards, BOARD_FREQ_MAINCK_XTAL should be defined in the board conf_board.h configuration file as the frequency of the fast crystal attached to the microcontroller.

4. Configure the main clock to run at the full 96MHz, disable scaling of the main system clock speed:

   #define CONFIG_SYSCLK_PRES         SYSCLK_PRES_1

   Note

   Some dividers are powers of two, while others are integer division factors. Refer to the formulas in the conf_clock.h template commented above each division define.

5. Configure the USB module clock to use the output of the PLL0 module as its source with division 2:

   #define CONFIG_USBCLK_SOURCE        USBCLK_SRC_PLL0
   #define CONFIG_USBCLK_DIV           2