conf_clock.h
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1 
33 /*
34  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
35  */
36 
37 #ifndef CONF_CLOCK_H_INCLUDED
38 #define CONF_CLOCK_H_INCLUDED
39 
40 // ===== System Clock (MCK) Source Options
41 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_RC
42 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_XTAL
43 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_SLCK_BYPASS
44 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_4M_RC
45 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_8M_RC
46 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_12M_RC
47 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_XTAL
48 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_MAINCK_BYPASS
49 #define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_PLLACK
50 //#define CONFIG_SYSCLK_SOURCE SYSCLK_SRC_UPLLCK
51 
52 // ===== Processor Clock (HCLK) Prescaler Options (Fhclk = Fsys / (SYSCLK_PRES))
53 #define CONFIG_SYSCLK_PRES SYSCLK_PRES_1
54 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_2
55 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_4
56 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_8
57 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_16
58 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_32
59 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_64
60 //#define CONFIG_SYSCLK_PRES SYSCLK_PRES_3
61 
62 // ===== System Clock (MCK) Division Options (Fmck = Fhclk / (SYSCLK_DIV))
63 #define CONFIG_SYSCLK_DIV 2
64 
65 #if 1 // HCLK: 300 MHz, MCK: 150 MHz
66 // ===== PLL0 (A) Options (Fpll = (Fclk * PLL_mul) / PLL_div)
67 // Use mul and div effective values here.
68 #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_BYPASS
69 #define CONFIG_PLL0_MUL 25
70 #define CONFIG_PLL0_DIV 1
71 
72 #else // HCLK: 200 MHz, MCK: 100 MHz
73 
74 #define CONFIG_PLL0_SOURCE PLL_SRC_MAINCK_XTAL
75 #define CONFIG_PLL0_MUL 50
76 #define CONFIG_PLL0_DIV 3
77 
78 #endif
79 
80 
81 // ===== UPLL (UTMI) Hardware fixed at 480 MHz.
82 
83 // ===== USB Clock Source Options (Fusb = FpllX / USB_div)
84 // Use div effective value here.
85 //#define CONFIG_USBCLK_SOURCE USBCLK_SRC_PLL0
86 #define CONFIG_USBCLK_SOURCE USBCLK_SRC_UPLL
87 #define CONFIG_USBCLK_DIV 1
88 
89 // ===== Target frequency (Processor clock)
90 // - XTAL frequency: 12MHz
91 // - System clock source: PLLA
92 // - System clock prescaler: 1 (divided by 1)
93 // - System clock divider: 2 (divided by 2)
94 // - PLLA source: XTAL
95 // - PLLA output: XTAL * 25 / 1
96 // - Processor clock: 12 * 25 / 1 / 1 = 300MHz
97 // - System clock: 300 / 2 = 150MHz
98 // ===== Target frequency (USB Clock)
99 // - USB clock source: UPLL
100 // - USB clock divider: 1 (not divided)
101 // - UPLL frequency: 480MHz
102 // - USB clock: 480 / 1 = 480MHz
103 
104 #endif /* CONF_CLOCK_H_INCLUDED */


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autogenerated on Sat Sep 19 2020 03:19:04