RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: More...
#include "stm32h7xx_hal.h"
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RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral:
============================================================================== ##### RCC specific features ##### ============================================================================== [..] After reset the device is running from Internal High Speed oscillator (HSI 64MHz) with Flash 0 wait state,and all peripherals are off except internal SRAM, Flash, JTAG and PWR (+) There is no pre-scaler on High speed (AHB) and Low speed (APB) buses; all peripherals mapped on these buses are running at HSI speed. (+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) All GPIOs are in analogue mode , except the JTAG pins which are assigned to be used for debug purpose. [..] Once the device started from reset, the user application has to: (+) Configure the clock source to be used to drive the System clock (if the application needs higher frequency/performance) (+) Configure the System clock frequency and Flash settings (+) Configure the AHB and APB buses pre-scalers (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock kernel source(s) for peripherals which clocks are not derived from the System clock through :RCC_D1CCIPR,RCC_D2CCIP1R,RCC_D2CCIP2R and RCC_D3CCIPR registers ##### RCC Limitations ##### ============================================================================== [..] A delay between an RCC peripheral clock enable and the effective peripheral enabling should be taken into account in order to manage the peripheral read/write from/to registers. (+) This delay depends on the peripheral mapping. (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle after the clock enable bit is set on the hardware register (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle after the clock enable bit is set on the hardware register [..] Implemented Workaround: (+) For AHB & APB peripherals, a dummy read to the peripheral register has been inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause
Definition in file stm32h735/stm32h735g-dk/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c.