96 #include "stm32h7xx_hal.h"
107 #ifdef HAL_DMA_MODULE_ENABLED
113 __IO uint32_t Reserved0;
115 } DMA_Base_Registers;
121 } BDMA_Base_Registers;
128 #define HAL_TIMEOUT_DMA_ABORT (5U)
130 #define BDMA_PERIPH_TO_MEMORY (0x00000000U)
131 #define BDMA_MEMORY_TO_PERIPH ((uint32_t)BDMA_CCR_DIR)
132 #define BDMA_MEMORY_TO_MEMORY ((uint32_t)BDMA_CCR_MEM2MEM)
135 #define DMA_TO_BDMA_DIRECTION(__DMA_DIRECTION__) (((__DMA_DIRECTION__) == DMA_MEMORY_TO_PERIPH)? BDMA_MEMORY_TO_PERIPH: \
136 ((__DMA_DIRECTION__) == DMA_MEMORY_TO_MEMORY)? BDMA_MEMORY_TO_MEMORY: \
137 BDMA_PERIPH_TO_MEMORY)
139 #define DMA_TO_BDMA_PERIPHERAL_INC(__DMA_PERIPHERAL_INC__) ((__DMA_PERIPHERAL_INC__) >> 3U)
140 #define DMA_TO_BDMA_MEMORY_INC(__DMA_MEMORY_INC__) ((__DMA_MEMORY_INC__) >> 3U)
142 #define DMA_TO_BDMA_PDATA_SIZE(__DMA_PDATA_SIZE__) ((__DMA_PDATA_SIZE__) >> 3U)
143 #define DMA_TO_BDMA_MDATA_SIZE(__DMA_MDATA_SIZE__) ((__DMA_MDATA_SIZE__) >> 3U)
145 #define DMA_TO_BDMA_MODE(__DMA_MODE__) ((__DMA_MODE__) >> 3U)
147 #define DMA_TO_BDMA_PRIORITY(__DMA_PRIORITY__) ((__DMA_PRIORITY__) >> 4U)
150 #define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
151 (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
152 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
153 (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )) || \
154 (((__REQUEST__) >= DMA_REQUEST_UART9_RX) && ((__REQUEST__) <= DMA_REQUEST_USART10_TX )))
156 #define IS_DMA_UART_USART_REQUEST(__REQUEST__) ((((__REQUEST__) >= DMA_REQUEST_USART1_RX) && ((__REQUEST__) <= DMA_REQUEST_USART3_TX)) || \
157 (((__REQUEST__) >= DMA_REQUEST_UART4_RX) && ((__REQUEST__) <= DMA_REQUEST_UART5_TX )) || \
158 (((__REQUEST__) >= DMA_REQUEST_USART6_RX) && ((__REQUEST__) <= DMA_REQUEST_USART6_TX)) || \
159 (((__REQUEST__) >= DMA_REQUEST_UART7_RX) && ((__REQUEST__) <= DMA_REQUEST_UART8_TX )))
170 static void DMA_SetConfig(
DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
213 uint32_t registerValue;
215 DMA_Base_Registers *regs_dma;
216 BDMA_Base_Registers *regs_bdma;
260 if((
HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
296 #if (STM32H7_DEV_ID == 0x450UL)
297 if((
DBGMCU->IDCODE & 0xFFFF0000U) >= 0x20000000U)
300 if(IS_DMA_UART_USART_REQUEST(hdma->
Init.
Request) != 0U)
304 #if (STM32H7_DEV_ID == 0x450UL)
330 if (DMA_CheckFifoParam(hdma) !=
HAL_OK)
348 regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
351 regs_dma->IFCR = 0x3FUL << (hdma->
StreamIndex & 0x1FU);
377 registerValue |= DMA_TO_BDMA_DIRECTION(hdma->
Init.
Direction) |
393 regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
411 DMA_CalcDMAMUXChannelBaseAndMask(hdma);
432 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
465 DMA_Base_Registers *regs_dma;
466 BDMA_Base_Registers *regs_bdma;
498 regs_dma = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
501 regs_dma->IFCR = 0x3FUL << (hdma->
StreamIndex & 0x1FU);
521 regs_bdma = (BDMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
538 DMA_CalcDMAMUXChannelBaseAndMask(hdma);
553 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
648 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
704 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
779 DMA_Base_Registers *regs_dma;
780 BDMA_Base_Registers *regs_bdma;
781 const __IO uint32_t *enableRegister;
833 if((
HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
852 regs_dma->IFCR = 0x3FUL << (hdma->
StreamIndex & 0x1FU);
894 BDMA_Base_Registers *regs_bdma;
979 uint32_t cpltlevel_mask;
983 __IO uint32_t *isr_reg;
985 __IO uint32_t *ifcr_reg;
1051 while(((*isr_reg) & cpltlevel_mask) == 0U)
1115 if(((
HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
1205 uint32_t tmpisr_dma, tmpisr_bdma;
1212 BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->
StreamBaseAddress;
1214 tmpisr_dma = regs_dma->ISR;
1215 tmpisr_bdma = regs_bdma->ISR;
1325 regs_dma->IFCR = 0x3FUL << (hdma->
StreamIndex & 0x1FU);
1397 if (++
count > timeout)
1767 static void DMA_SetConfig(
DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
1771 BDMA_Base_Registers *regs_bdma = (BDMA_Base_Registers *)hdma->
StreamBaseAddress;
1788 regs_dma->IFCR = 0x3FUL << (hdma->
StreamIndex & 0x1FU);
1858 uint32_t stream_number = (((uint32_t)((uint32_t*)hdma->
Instance) & 0xFFU) - 16U) / 24U;
1861 static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
1862 hdma->
StreamIndex = flagBitshiftOffset[stream_number & 0x7U];
1864 if (stream_number > 3U)
1986 uint32_t stream_number;
1987 uint32_t stream_baseaddress = (uint32_t)((uint32_t*)hdma->
Instance);
1992 stream_number = (((uint32_t)((uint32_t*)hdma->
Instance) & 0xFFU) - 8U) / 20U;
2000 stream_number = (((uint32_t)((uint32_t*)hdma->
Instance) & 0xFFU) - 16U) / 24U;
2002 if((stream_baseaddress <= ((uint32_t)
DMA2_Stream7) ) && \
2005 stream_number += 8U;