83 #include "stm32h7xx_hal.h"
94 #ifdef HAL_CORTEX_MODULE_ENABLED
167 uint32_t prioritygroup;
231 return SysTick_Config(TicksNumb);
252 #if (__MPU_PRESENT == 1)
257 void HAL_MPU_Disable(
void)
280 void HAL_MPU_Enable(uint32_t MPU_Control)
283 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
298 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
305 MPU->RNR = MPU_Init->Number;
307 if ((MPU_Init->Enable) != 0UL)
310 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
311 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
313 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
314 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
315 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
316 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
319 MPU->RBAR = MPU_Init->BaseAddress;
320 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
321 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
322 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
323 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
324 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
325 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
326 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
327 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
328 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
486 #if defined(DUAL_CORE)
494 if (((
SCB->CPUID & 0x000000F0U) >> 4 )== 0x7U)