stm32f10x_i2c.h
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1 
23 /* Define to prevent recursive inclusion -------------------------------------*/
24 #ifndef __STM32F10x_I2C_H
25 #define __STM32F10x_I2C_H
26 
27 #ifdef __cplusplus
28  extern "C" {
29 #endif
30 
31 /* Includes ------------------------------------------------------------------*/
32 #include "stm32f10x.h"
33 
50 typedef struct
51 {
52  uint32_t I2C_ClockSpeed;
55  uint16_t I2C_Mode;
58  uint16_t I2C_DutyCycle;
61  uint16_t I2C_OwnAddress1;
64  uint16_t I2C_Ack;
67  uint16_t I2C_AcknowledgedAddress;
69 }I2C_InitTypeDef;
70 
80 #define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
81  ((PERIPH) == I2C2))
82 
86 #define I2C_Mode_I2C ((uint16_t)0x0000)
87 #define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
88 #define I2C_Mode_SMBusHost ((uint16_t)0x000A)
89 #define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
90  ((MODE) == I2C_Mode_SMBusDevice) || \
91  ((MODE) == I2C_Mode_SMBusHost))
92 
100 #define I2C_DutyCycle_16_9 ((uint16_t)0x4000)
101 #define I2C_DutyCycle_2 ((uint16_t)0xBFFF)
102 #define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
103  ((CYCLE) == I2C_DutyCycle_2))
104 
112 #define I2C_Ack_Enable ((uint16_t)0x0400)
113 #define I2C_Ack_Disable ((uint16_t)0x0000)
114 #define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
115  ((STATE) == I2C_Ack_Disable))
116 
124 #define I2C_Direction_Transmitter ((uint8_t)0x00)
125 #define I2C_Direction_Receiver ((uint8_t)0x01)
126 #define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
127  ((DIRECTION) == I2C_Direction_Receiver))
128 
136 #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
137 #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
138 #define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
139  ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
140 
148 #define I2C_Register_CR1 ((uint8_t)0x00)
149 #define I2C_Register_CR2 ((uint8_t)0x04)
150 #define I2C_Register_OAR1 ((uint8_t)0x08)
151 #define I2C_Register_OAR2 ((uint8_t)0x0C)
152 #define I2C_Register_DR ((uint8_t)0x10)
153 #define I2C_Register_SR1 ((uint8_t)0x14)
154 #define I2C_Register_SR2 ((uint8_t)0x18)
155 #define I2C_Register_CCR ((uint8_t)0x1C)
156 #define I2C_Register_TRISE ((uint8_t)0x20)
157 #define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
158  ((REGISTER) == I2C_Register_CR2) || \
159  ((REGISTER) == I2C_Register_OAR1) || \
160  ((REGISTER) == I2C_Register_OAR2) || \
161  ((REGISTER) == I2C_Register_DR) || \
162  ((REGISTER) == I2C_Register_SR1) || \
163  ((REGISTER) == I2C_Register_SR2) || \
164  ((REGISTER) == I2C_Register_CCR) || \
165  ((REGISTER) == I2C_Register_TRISE))
166 
174 #define I2C_SMBusAlert_Low ((uint16_t)0x2000)
175 #define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
176 #define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
177  ((ALERT) == I2C_SMBusAlert_High))
178 
186 #define I2C_PECPosition_Next ((uint16_t)0x0800)
187 #define I2C_PECPosition_Current ((uint16_t)0xF7FF)
188 #define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
189  ((POSITION) == I2C_PECPosition_Current))
190 
198 #define I2C_NACKPosition_Next ((uint16_t)0x0800)
199 #define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
200 #define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
201  ((POSITION) == I2C_NACKPosition_Current))
202 
210 #define I2C_IT_BUF ((uint16_t)0x0400)
211 #define I2C_IT_EVT ((uint16_t)0x0200)
212 #define I2C_IT_ERR ((uint16_t)0x0100)
213 #define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
214 
222 #define I2C_IT_SMBALERT ((uint32_t)0x01008000)
223 #define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
224 #define I2C_IT_PECERR ((uint32_t)0x01001000)
225 #define I2C_IT_OVR ((uint32_t)0x01000800)
226 #define I2C_IT_AF ((uint32_t)0x01000400)
227 #define I2C_IT_ARLO ((uint32_t)0x01000200)
228 #define I2C_IT_BERR ((uint32_t)0x01000100)
229 #define I2C_IT_TXE ((uint32_t)0x06000080)
230 #define I2C_IT_RXNE ((uint32_t)0x06000040)
231 #define I2C_IT_STOPF ((uint32_t)0x02000010)
232 #define I2C_IT_ADD10 ((uint32_t)0x02000008)
233 #define I2C_IT_BTF ((uint32_t)0x02000004)
234 #define I2C_IT_ADDR ((uint32_t)0x02000002)
235 #define I2C_IT_SB ((uint32_t)0x02000001)
236 
237 #define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
238 
239 #define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
240  ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
241  ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
242  ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
243  ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
244  ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
245  ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
246 
258 #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
259 #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
260 #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
261 #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
262 #define I2C_FLAG_TRA ((uint32_t)0x00040000)
263 #define I2C_FLAG_BUSY ((uint32_t)0x00020000)
264 #define I2C_FLAG_MSL ((uint32_t)0x00010000)
265 
270 #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
271 #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
272 #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
273 #define I2C_FLAG_OVR ((uint32_t)0x10000800)
274 #define I2C_FLAG_AF ((uint32_t)0x10000400)
275 #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
276 #define I2C_FLAG_BERR ((uint32_t)0x10000100)
277 #define I2C_FLAG_TXE ((uint32_t)0x10000080)
278 #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
279 #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
280 #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
281 #define I2C_FLAG_BTF ((uint32_t)0x10000004)
282 #define I2C_FLAG_ADDR ((uint32_t)0x10000002)
283 #define I2C_FLAG_SB ((uint32_t)0x10000001)
284 
285 #define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
286 
287 #define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
288  ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
289  ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
290  ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
291  ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
292  ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
293  ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
294  ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
295  ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
296  ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
297  ((FLAG) == I2C_FLAG_SB))
298 
306 /*========================================
307 
308  I2C Master Events (Events grouped in order of communication)
309  ==========================================*/
318 /* --EV5 */
319 #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
320 
346 /* --EV6 */
347 #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
348 #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
349 /* --EV9 */
350 #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
351 
381 /* Master RECEIVER mode -----------------------------*/
382 /* --EV7 */
383 #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
384 
385 /* Master TRANSMITTER mode --------------------------*/
386 /* --EV8 */
387 #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
388 /* --EV8_2 */
389 #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
390 
391 
392 /*========================================
393 
394  I2C Slave Events (Events grouped in order of communication)
395  ==========================================*/
396 
422 /* --EV1 (all the events below are variants of EV1) */
423 /* 1) Case of One Single Address managed by the slave */
424 #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
425 #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
426 
427 /* 2) Case of Dual address managed by the slave */
428 #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
429 #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
430 
431 /* 3) Case of General Call enabled for the slave */
432 #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
433 
461 /* Slave RECEIVER mode --------------------------*/
462 /* --EV2 */
463 #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
464 /* --EV4 */
465 #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
466 
467 /* Slave TRANSMITTER mode -----------------------*/
468 /* --EV3 */
469 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
470 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
471 /* --EV3_2 */
472 #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
473 
474 /*=========================== End of Events Description ==========================================*/
475 
476 #define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
477  ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
478  ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
479  ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
480  ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
481  ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
482  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
483  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
484  ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
485  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
486  ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
487  ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
488  ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
489  ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
490  ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
491  ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
492  ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
493  ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
494  ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
495  ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
496 
504 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
505 
513 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
514 
534 void I2C_DeInit(I2C_TypeDef* I2Cx);
535 void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
536 void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
537 void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
538 void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
539 void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
540 void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
541 void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
542 void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
543 void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
544 void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
545 void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
546 void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
547 void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
548 uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
549 void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
550 uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
551 void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
552 void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
553 void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
554 void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
555 void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
556 void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
557 uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
558 void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
559 void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
560 void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
561 
645 ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
651 uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
657 FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
663 void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
664 ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
665 void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
666 
667 #ifdef __cplusplus
668 }
669 #endif
670 
671 #endif /*__STM32F10x_I2C_H */
672 
684 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
I2C_ReadRegister
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
Reads the specified I2C register and returns its value.
Definition: stm32f4xx_i2c.c:1066
FlagStatus
FlagStatus
Definition: stm32f4xx.h:706
I2C_GenerateSTOP
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication STOP condition.
Definition: stm32f4xx_i2c.c:417
I2C_CheckEvent
ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
I2C State Monitoring Functions.
Definition: stm32f4xx_i2c.c:1152
FunctionalState
FunctionalState
Definition: stm32f4xx.h:708
I2C_SendData
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
Sends a data byte through the I2Cx peripheral.
Definition: stm32f4xx_i2c.c:750
I2C_GetPEC
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx)
Returns the PEC value for the specified I2C.
Definition: stm32f4xx_i2c.c:871
I2C_GetFlagStatus
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Checks whether the specified I2C flag is set or not.
Definition: stm32f4xx_i2c.c:1255
I2C_PECPositionConfig
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
Selects the specified I2C PEC position.
Definition: stm32f4xx_i2c.c:825
I2C_DMALastTransferCmd
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Specifies that the next DMA transfer is the last one.
Definition: stm32f4xx_i2c.c:928
I2C_FastModeDutyCycleConfig
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
Selects the specified I2C fast mode duty cycle.
Definition: stm32f4xx_i2c.c:622
I2C_ITConfig
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
Enables or disables the specified I2C interrupts.
Definition: stm32f4xx_i2c.c:1093
I2C_StretchClockCmd
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C Clock stretching.
Definition: stm32f4xx_i2c.c:596
I2C_DualAddressCmd
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C dual addressing mode.
Definition: stm32f4xx_i2c.c:522
I2Cx
static I2C_TypeDef * I2Cx
Definition: drv_i2c.c:64
I2C_OwnAddress2Config
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address)
Configures the specified I2C own address2.
Definition: stm32f4xx_i2c.c:495
I2C_GeneralCallCmd
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C general call feature.
Definition: stm32f4xx_i2c.c:546
I2C_GenerateSTART
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState)
Generates I2Cx communication START condition.
Definition: stm32f4xx_i2c.c:393
ITStatus
enum FlagStatus ITStatus
I2C_AcknowledgeConfig
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C acknowledge feature.
Definition: stm32f4xx_i2c.c:472
I2C_TransmitPEC
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C PEC transfer.
Definition: stm32f4xx_i2c.c:794
I2C_ClearFlag
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
Clears the I2Cx&#39;s pending flags.
Definition: stm32f4xx_i2c.c:1332
I2C_SMBusAlertConfig
void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
Drives the SMBusAlert pin high or low for the specified I2C.
Definition: stm32f4xx_i2c.c:688
I2C_ARPCmd
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C ARP.
Definition: stm32f4xx_i2c.c:712
I2C_StructInit
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
Fills each I2C_InitStruct member with its default value.
Definition: stm32f4xx_i2c.c:289
I2C_ClearITPendingBit
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Clears the I2Cx&#39;s interrupt pending bits.
Definition: stm32f4xx_i2c.c:1426
I2C_Cmd
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C peripheral.
Definition: stm32f4xx_i2c.c:313
ErrorStatus
ErrorStatus
Definition: stm32f4xx.h:711
I2C_InitTypeDef
I2C Init structure definition.
Definition: stm32f4xx_i2c.h:54
I2C_CalculatePEC
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the PEC value calculation of the transferred bytes.
Definition: stm32f4xx_i2c.c:849
I2C_NACKPositionConfig
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
Selects the specified I2C NACK position in master receiver mode.
Definition: stm32f4xx_i2c.c:660
I2C_GetITStatus
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
Checks whether the specified I2C interrupt has occurred or not.
Definition: stm32f4xx_i2c.c:1366
I2C_Init
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
Initializes the I2Cx peripheral according to the specified parameters in the I2C_InitStruct.
Definition: stm32f4xx_i2c.c:180
I2C_SoftwareResetCmd
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C software reset.
Definition: stm32f4xx_i2c.c:572
I2C_DMACmd
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
Enables or disables the specified I2C DMA requests.
Definition: stm32f4xx_i2c.c:904
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f4xx.h:1320
stm32f10x.h
CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral reg...
I2C_DeInit
void I2C_DeInit(I2C_TypeDef *I2Cx)
Deinitialize the I2Cx peripheral registers to their default reset values.
Definition: stm32f4xx_i2c.c:137
I2C_Send7bitAddress
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
Transmits the address byte to select the slave device.
Definition: stm32f4xx_i2c.c:445
I2C_ReceiveData
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
Returns the most recent received data by the I2Cx peripheral.
Definition: stm32f4xx_i2c.c:763
I2C_GetLastEvent
uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx)
Returns the last I2Cx Event.
Definition: stm32f4xx_i2c.c:1200

rosflight_firmware
Author(s): Daniel Koch , James Jackson
autogenerated on Thu Apr 15 2021 05:07:48