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00057
00058 struct ath5k_hw_rx_ctl {
00059 u32 rx_control_0;
00060 u32 rx_control_1;
00061 } __packed;
00062
00063
00064 #define AR5K_DESC_RX_CTL0 0x00000000
00065
00066
00067 #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff
00068 #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000
00069
00070
00071
00072
00073
00074 struct ath5k_hw_rx_status {
00075 u32 rx_status_0;
00076 u32 rx_status_1;
00077 } __packed;
00078
00079
00080
00081 #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff
00082 #define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000
00083 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000
00084 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S 15
00085 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000
00086 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19
00087 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000
00088 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27
00089
00090
00091 #define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001
00092 #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
00093 #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004
00094 #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008
00095 #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010
00096 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0
00097 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5
00098 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
00099 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00
00100 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9
00101 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
00102 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15
00103 #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000
00104
00105
00106
00107 #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff
00108 #define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000
00109 #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000
00110 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000
00111 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S 15
00112 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000
00113 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20
00114 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000
00115 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28
00116
00117
00118 #define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001
00119 #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
00120 #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004
00121 #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008
00122 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010
00123 #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020
00124 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
00125 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00
00126 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S 9
00127 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000
00128 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16
00129 #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000
00130
00131
00132
00133
00134 struct ath5k_hw_rx_error {
00135 u32 rx_error_0;
00136 u32 rx_error_1;
00137 } __packed;
00138
00139
00140 #define AR5K_RX_DESC_ERROR0 0x00000000
00141
00142
00143 #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00
00144 #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8
00145
00146
00147 #define AR5K_DESC_RX_PHY_ERROR_NONE 0x00
00148 #define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20
00149 #define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40
00150 #define AR5K_DESC_RX_PHY_ERROR_RATE 0x60
00151 #define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80
00152 #define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0
00153 #define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0
00154 #define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0
00155
00156
00157
00158
00159 struct ath5k_hw_2w_tx_ctl {
00160 u32 tx_control_0;
00161 u32 tx_control_1;
00162 } __packed;
00163
00164
00165 #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
00166 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000
00167 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12
00168 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000
00169 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18
00170 #define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000
00171 #define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000
00172 #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000
00173 #define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000
00174 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000
00175 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26
00176 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000
00177 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000
00178
00179 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT \
00180 (ah->ah_version == AR5K_AR5210 ? \
00181 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \
00182 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211)
00183
00184 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
00185 #define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000
00186 #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
00187
00188
00189 #define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff
00190 #define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000
00191 #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000
00192 #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000
00193
00194 #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX \
00195 (ah->ah_version == AR5K_AR5210 ? \
00196 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \
00197 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211)
00198
00199 #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13
00200 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000
00201 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20
00202 #define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000
00203 #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000
00204
00205
00206 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00
00207 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04
00208 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08
00209 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c
00210 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10
00211
00212
00213
00214
00215 struct ath5k_hw_4w_tx_ctl {
00216 u32 tx_control_0;
00217
00218 #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
00219 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000
00220 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16
00221 #define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000
00222 #define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000
00223 #define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000
00224 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000
00225 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
00226 #define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000
00227 #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
00228 #define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000
00229
00230 u32 tx_control_1;
00231
00232 #define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff
00233 #define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000
00234 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000
00235 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13
00236 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000
00237 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20
00238 #define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000
00239 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000
00240 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25
00241 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000
00242 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27
00243 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000
00244 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29
00245
00246 u32 tx_control_2;
00247
00248 #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff
00249 #define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000
00250 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000
00251 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16
00252 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000
00253 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20
00254 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000
00255 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24
00256 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000
00257 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28
00258
00259 u32 tx_control_3;
00260
00261 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f
00262 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0
00263 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5
00264 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00
00265 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10
00266 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000
00267 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15
00268 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000
00269 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20
00270 } __packed;
00271
00272
00273
00274
00275 struct ath5k_hw_tx_status {
00276 u32 tx_status_0;
00277 u32 tx_status_1;
00278 } __packed;
00279
00280
00281 #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001
00282 #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002
00283 #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004
00284 #define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008
00285
00286
00287
00288
00289 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0
00290 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4
00291
00292
00293
00294
00295 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00
00296 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8
00297 #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000
00298 #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12
00299 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000
00300 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16
00301
00302
00303 #define AR5K_DESC_TX_STATUS1_DONE 0x00000001
00304 #define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe
00305 #define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1
00306 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000
00307 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
00308 #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000
00309 #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21
00310 #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000
00311 #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000
00312
00313
00314
00315
00316 struct ath5k_hw_5210_tx_desc {
00317 struct ath5k_hw_2w_tx_ctl tx_ctl;
00318 struct ath5k_hw_tx_status tx_stat;
00319 } __packed;
00320
00321
00322
00323
00324 struct ath5k_hw_5212_tx_desc {
00325 struct ath5k_hw_4w_tx_ctl tx_ctl;
00326 struct ath5k_hw_tx_status tx_stat;
00327 } __packed;
00328
00329
00330
00331
00332 struct ath5k_hw_all_rx_desc {
00333 struct ath5k_hw_rx_ctl rx_ctl;
00334 union {
00335 struct ath5k_hw_rx_status rx_stat;
00336 struct ath5k_hw_rx_error rx_err;
00337 } u;
00338 } __packed;
00339
00340
00341
00342
00343
00344 struct ath5k_desc {
00345 u32 ds_link;
00346 u32 ds_data;
00347
00348 union {
00349 struct ath5k_hw_5210_tx_desc ds_tx5210;
00350 struct ath5k_hw_5212_tx_desc ds_tx5212;
00351 struct ath5k_hw_all_rx_desc ds_rx;
00352 } ud;
00353 } __packed;
00354
00355 #define AR5K_RXDESC_INTREQ 0x0020
00356
00357 #define AR5K_TXDESC_CLRDMASK 0x0001
00358 #define AR5K_TXDESC_NOACK 0x0002
00359 #define AR5K_TXDESC_RTSENA 0x0004
00360 #define AR5K_TXDESC_CTSENA 0x0008
00361 #define AR5K_TXDESC_INTREQ 0x0010
00362 #define AR5K_TXDESC_VEOL 0x0020
00363