ssp.c
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00001 /*
00002 
00003 Copyright (c) 2011, Ascending Technologies GmbH
00004 All rights reserved.
00005 
00006 Redistribution and use in source and binary forms, with or without
00007 modification, are permitted provided that the following conditions are met:
00008 
00009  * Redistributions of source code must retain the above copyright notice,
00010    this list of conditions and the following disclaimer.
00011  * Redistributions in binary form must reproduce the above copyright
00012    notice, this list of conditions and the following disclaimer in the
00013    documentation and/or other materials provided with the distribution.
00014 
00015 THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
00016 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00017 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00018 DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY
00019 DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00020 (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00021 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00022 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
00023 LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
00024 OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
00025 DAMAGE.
00026 
00027  */
00028 
00029 #include "LPC214x.h"                    /* LPC21XX Peripheral Registers */
00030 #include "type.h"
00031 #include "irq.h"
00032 #include "ssp.h"
00033 #include "main.h"
00034 #include "system.h"
00035 #include "LL_HL_comm.h"
00036 #include "sdk.h"
00037 
00038 char SPIWRData[128];
00039 char SPIRDData[128];
00040 int CurrentTxIndex;
00041 int CurrentRxIndex;
00042 unsigned int SPIWR_num_bytes;
00043 
00044 volatile unsigned int SSP_trans_cnt=0;
00045 
00046 unsigned char data_sent_to_LL=1;
00047 
00048 unsigned char SSP_receiption_complete=1;
00049 
00050 char data_sent_to_HL=1;
00051 
00052 inline void SSPReceive(unsigned char);
00053 
00054 void SSPHandler (void) __irq
00055 {
00056     int regValue;
00057     unsigned short input_data;
00058 //    unsigned char timeout=0;
00059 
00060     IENABLE;                            /* handles nested interrupt */
00061 
00062     regValue = SSPMIS;
00063     if ( regValue & SSPMIS_RORMIS )     /* Receive overrun interrupt */
00064     {
00065                 SSPICR = SSPICR_RORIC;          /* clear interrupt */
00066     }
00067     if ( regValue & SSPMIS_RTMIS )      /* Receive timeout interrupt */
00068     {
00069                 SSPICR = SSPICR_RTIC;           /* clear interrupt */
00070     }
00071 
00072     if ( regValue & SSPMIS_RXMIS )      /* Rx at least half full */
00073     {
00074                         /* receive until it's empty */
00075         while ( SSPSR & SSPSR_RNE )
00076         {
00077                 input_data=SSPDR;
00078             //SSPReceive(input_data&0xFF);
00079             //SSPReceive(input_data>>8);
00080 
00081                 SSP_rx_handler_HL(input_data&0xFF);
00082                 SSP_rx_handler_HL(input_data>>8);
00083 
00084                 //SSP_trans_cnt+=2;
00085             /* Wait until the Busy bit is cleared */
00086         //    while ( (!(SSPSR & SSPSR_BSY) )&&(timeout++<50) );
00087         }                               /* interrupt will be cleared when */
00088                                         /* data register is read or written */
00089     }
00090 
00091     if ( regValue & SSPMIS_TXMIS )      /* Tx at least half empty */
00092     {
00093         /* transmit until it's full */
00094         while ( (SSPSR & SSPSR_TNF) )
00095         {
00096             if(CurrentTxIndex<SPIWR_num_bytes)
00097             {
00098                 SSPDR = SPIWRData[CurrentTxIndex]|(SPIWRData[CurrentTxIndex+1]<<8);
00099                 CurrentTxIndex+=2;
00100             }
00101             else
00102             {
00103                 CurrentTxIndex=0;
00104                 SPIWR_num_bytes=0;
00105                 data_sent_to_LL=1;
00106                         SSPDR=0;
00107             }
00108 
00109             /* Wait until the Busy bit is cleared */
00110         //    while ( !(SSPSR & SSPSR_BSY) );
00111         }                               /* interrupt will be cleared when */
00112                                         /* data register is read or written */
00113     }
00114 
00115     IDISABLE;
00116     VICVectAddr = 0;            /* Acknowledge Interrupt */
00117 }
00118 
00119 void LL_write_init(void)
00120 {
00121                 SPIWRData[0]='>';
00122                 SPIWRData[1]='*';
00123                 SPIWRData[2]='>';
00124 }
00125 
00126 int LL_write(unsigned char *data, unsigned short cnt, unsigned char PD )        //write data to high-level processor
00127 {
00128         unsigned int i;
00129 
00130         if(data_sent_to_LL)
00131         {
00132                 SPIWRData[3]=PD;
00133                 for(i=0; i<cnt; i++)
00134                 {
00135                         SPIWRData[i+4]=data[i];
00136                 }
00137                 SPIWRData[cnt+4]=0;
00138                 SPIWR_num_bytes=cnt+5;
00139         }
00140         else if(SPIWR_num_bytes+cnt<127)
00141         {
00142                 SPIWRData[SPIWR_num_bytes-1]='>';
00143                 SPIWRData[0+SPIWR_num_bytes]='*';
00144                 SPIWRData[1+SPIWR_num_bytes]='>';
00145                 SPIWRData[2+SPIWR_num_bytes]=PD;
00146                 for(i=SPIWR_num_bytes; i<cnt+SPIWR_num_bytes; i++)
00147                 {
00148                         SPIWRData[i+3]=data[i-SPIWR_num_bytes];
00149                 }
00150                 SPIWR_num_bytes+=cnt+5;
00151                 SPIWRData[SPIWR_num_bytes-1]=0;
00152         }
00153         else return(0);
00154         data_sent_to_LL=0;
00155 
00156         return(1);
00157 }
00158 
00159 


asctec_hl_firmware
Author(s): Markus Achtelik, Michael Achtelik, Stephan Weiss, Laurent Kneip
autogenerated on Tue Dec 17 2013 11:39:27