lpcUART.h
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00001 /******************************************************************************
00002  *
00003  * $RCSfile: $
00004  * $Revision: $
00005  *
00006  * Header file for Philips LPC ARM Processors.
00007  * Copyright 2004 R O SoftWare
00008  *
00009  * No guarantees, warrantees, or promises, implied or otherwise.
00010  * May be used for hobby or commercial purposes provided copyright
00011  * notice remains intact.
00012  *
00013  *****************************************************************************/
00014 #ifndef INC_LPC_UART_H
00015 #define INC_LPC_UART_H
00016 
00017 // Universal Asynchronous Receiver Transmitter Registers
00018 //typedef struct
00019 //{
00020 //  union
00021 //    {
00022 //    REG_8 rbr;                          // Receive Buffer Register
00023 //    REG_8 thr;                          // Transmit Holding Register
00024 //    REG_8 dll;                          // Divisor Latch Register (LSB)
00025 //    REG_8 _pad0[4];
00026 //    };
00027 //
00028 //  union
00029 //    {
00030 //    REG_8 ier;                          // Interrupt Enable Register
00031 //    REG_8 dlm;                          // Divisor Latch Register (MSB)
00032 //    REG_8 _pad1[4];
00033 //    };
00034 //
00035 //  union
00036 //    {
00037 //    REG_8 iir;                          // Interrupt ID Register
00038 //    REG_8 fcr;                          // FIFO Control Register
00039 //    REG_8 _pad2[4];
00040 //    };
00041 //
00042 //  REG_8 lcr;                            // Line Control Registe
00043 //  REG_8 _pad3[3];
00044 //  REG_8 mcr;                            // MODEM Control Register
00045 //  REG_8 _pad4[3];
00046 //  REG_8 lsr;                            // Line Status Register
00047 //  REG_8 _pad5[3];
00048 //  REG_8 msr;                            // MODEM Status Register
00049 //  REG_8 _pad6[3];
00050 //  REG_8 scr;                            // Scratch Pad Register
00051 //  REG_8 _pad7[3];
00052 //} uartRegs_t;
00053 
00055 // UART defines
00056 
00057 // Interrupt Enable Register bit definitions
00058 #define UIER_ERBFI          (1 << 0)    // Enable Receive Data Available Interrupt
00059 #define UIER_ETBEI          (1 << 1)    // Enable Transmit Holding Register Empty Interrupt
00060 #define UIER_ELSI           (1 << 2)    // Enable Receive Line Status Interrupt
00061 #define UIER_EDSSI          (1 << 3)    // Enable MODEM Status Interrupt
00062 
00063 // Interrupt ID Register bit definitions
00064 #define UIIR_NO_INT         (1 << 0)    // NO INTERRUPTS PENDING
00065 #define UIIR_MS_INT         (0 << 1)    // MODEM Status
00066 #define UIIR_THRE_INT       (1 << 1)    // Transmit Holding Register Empty
00067 #define UIIR_RDA_INT        (2 << 1)    // Receive Data Available
00068 #define UIIR_RLS_INT        (3 << 1)    // Receive Line Status
00069 #define UIIR_CTI_INT        (6 << 1)    // Character Timeout Indicator
00070 #define UIIR_ID_MASK        0x0E
00071 
00072 // FIFO Control Register bit definitions
00073 #define UFCR_FIFO_ENABLE    (1 << 0)    // FIFO Enable
00074 #define UFCR_RX_FIFO_RESET  (1 << 1)    // Reset Receive FIFO
00075 #define UFCR_TX_FIFO_RESET  (1 << 2)    // Reset Transmit FIFO
00076 #define UFCR_FIFO_TRIG1     (0 << 6)    // Trigger @ 1 character in FIFO
00077 #define UFCR_FIFO_TRIG4     (1 << 6)    // Trigger @ 4 characters in FIFO
00078 #define UFCR_FIFO_TRIG8     (2 << 6)    // Trigger @ 8 characters in FIFO
00079 #define UFCR_FIFO_TRIG14    (3 << 6)    // Trigger @ 14 characters in FIFO
00080 
00081 // Line Control Register bit definitions
00082 #define ULCR_CHAR_5         (0 << 0)    // 5-bit character length
00083 #define ULCR_CHAR_6         (1 << 0)    // 6-bit character length
00084 #define ULCR_CHAR_7         (2 << 0)    // 7-bit character length
00085 #define ULCR_CHAR_8         (3 << 0)    // 8-bit character length
00086 #define ULCR_STOP_1         (0 << 2)    // 1 stop bit
00087 #define ULCR_STOP_2         (1 << 2)    // 2 stop bits
00088 #define ULCR_PAR_NO         (0 << 3)    // No Parity
00089 #define ULCR_PAR_ODD        (1 << 3)    // Odd Parity
00090 #define ULCR_PAR_EVEN       (3 << 3)    // Even Parity
00091 #define ULCR_PAR_MARK       (5 << 3)    // MARK "1" Parity
00092 #define ULCR_PAR_SPACE      (7 << 3)    // SPACE "0" Paruty
00093 #define ULCR_BREAK_ENABLE   (1 << 6)    // Output BREAK line condition
00094 #define ULCR_DLAB_ENABLE    (1 << 7)    // Enable Divisor Latch Access
00095 
00096 // Modem Control Register bit definitions
00097 #define UMCR_DTR            (1 << 0)    // Data Terminal Ready
00098 #define UMCR_RTS            (1 << 1)    // Request To Send
00099 #define UMCR_LB             (1 << 4)    // Loopback
00100 
00101 // Line Status Register bit definitions
00102 #define ULSR_RDR            (1 << 0)    // Receive Data Ready
00103 #define ULSR_OE             (1 << 1)    // Overrun Error
00104 #define ULSR_PE             (1 << 2)    // Parity Error
00105 #define ULSR_FE             (1 << 3)    // Framing Error
00106 #define ULSR_BI             (1 << 4)    // Break Interrupt
00107 #define ULSR_THRE           (1 << 5)    // Transmit Holding Register Empty
00108 #define ULSR_TEMT           (1 << 6)    // Transmitter Empty
00109 #define ULSR_RXFE           (1 << 7)    // Error in Receive FIFO
00110 #define ULSR_ERR_MASK       0x1E
00111 
00112 // Modem Status Register bit definitions
00113 #define UMSR_DCTS           (1 << 0)    // Delta Clear To Send
00114 #define UMSR_DDSR           (1 << 1)    // Delta Data Set Ready
00115 #define UMSR_TERI           (1 << 2)    // Trailing Edge Ring Indicator
00116 #define UMSR_DDCD           (1 << 3)    // Delta Data Carrier Detect
00117 #define UMSR_CTS            (1 << 4)    // Clear To Send
00118 #define UMSR_DSR            (1 << 5)    // Data Set Ready
00119 #define UMSR_RI             (1 << 6)    // Ring Indicator
00120 #define UMSR_DCD            (1 << 7)    // Data Carrier Detect
00121 
00122 #endif


ccny_asctec_firmware_2
Author(s): Ivan Dryanovski, Roberto G. Valenti
autogenerated on Tue Jan 7 2014 11:04:17