21 #ifndef STM32F4xx_HAL_DMA2D_H
22 #define STM32F4xx_HAL_DMA2D_H
46 #define MAX_DMA2D_LAYER 2U
55 uint32_t CLUTColorMode;
60 } DMA2D_CLUTCfgTypeDef;
73 uint32_t OutputOffset;
90 uint32_t InputColorMode;
106 } DMA2D_LayerCfgTypeDef;
113 HAL_DMA2D_STATE_RESET = 0x00U,
114 HAL_DMA2D_STATE_READY = 0x01U,
115 HAL_DMA2D_STATE_BUSY = 0x02U,
116 HAL_DMA2D_STATE_TIMEOUT = 0x03U,
117 HAL_DMA2D_STATE_ERROR = 0x04U,
118 HAL_DMA2D_STATE_SUSPEND = 0x05U
119 }HAL_DMA2D_StateTypeDef;
124 typedef struct __DMA2D_HandleTypeDef
128 DMA2D_InitTypeDef
Init;
130 void (* XferCpltCallback)(
struct __DMA2D_HandleTypeDef * hdma2d);
132 void (* XferErrorCallback)(
struct __DMA2D_HandleTypeDef * hdma2d);
134 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
135 void (* LineEventCallback)(
struct __DMA2D_HandleTypeDef * hdma2d);
137 void (* CLUTLoadingCpltCallback)(
struct __DMA2D_HandleTypeDef * hdma2d);
139 void (* MspInitCallback)(
struct __DMA2D_HandleTypeDef * hdma2d);
141 void (* MspDeInitCallback)(
struct __DMA2D_HandleTypeDef * hdma2d);
145 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER];
149 __IO HAL_DMA2D_StateTypeDef State;
151 __IO uint32_t ErrorCode;
152 } DMA2D_HandleTypeDef;
154 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
158 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d);
172 #define HAL_DMA2D_ERROR_NONE 0x00000000U
173 #define HAL_DMA2D_ERROR_TE 0x00000001U
174 #define HAL_DMA2D_ERROR_CE 0x00000002U
175 #define HAL_DMA2D_ERROR_CAE 0x00000004U
176 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U
177 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
178 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U
188 #define DMA2D_M2M 0x00000000U
189 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0
190 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1
191 #define DMA2D_R2M DMA2D_CR_MODE
199 #define DMA2D_OUTPUT_ARGB8888 0x00000000U
200 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0
201 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1
202 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
203 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2
211 #define DMA2D_INPUT_ARGB8888 0x00000000U
212 #define DMA2D_INPUT_RGB888 0x00000001U
213 #define DMA2D_INPUT_RGB565 0x00000002U
214 #define DMA2D_INPUT_ARGB1555 0x00000003U
215 #define DMA2D_INPUT_ARGB4444 0x00000004U
216 #define DMA2D_INPUT_L8 0x00000005U
217 #define DMA2D_INPUT_AL44 0x00000006U
218 #define DMA2D_INPUT_AL88 0x00000007U
219 #define DMA2D_INPUT_L4 0x00000008U
220 #define DMA2D_INPUT_A8 0x00000009U
221 #define DMA2D_INPUT_A4 0x0000000AU
229 #define DMA2D_NO_MODIF_ALPHA 0x00000000U
230 #define DMA2D_REPLACE_ALPHA 0x00000001U
231 #define DMA2D_COMBINE_ALPHA 0x00000002U
245 #define DMA2D_CCM_ARGB8888 0x00000000U
246 #define DMA2D_CCM_RGB888 0x00000001U
254 #define DMA2D_IT_CE DMA2D_CR_CEIE
255 #define DMA2D_IT_CTC DMA2D_CR_CTCIE
256 #define DMA2D_IT_CAE DMA2D_CR_CAEIE
257 #define DMA2D_IT_TW DMA2D_CR_TWIE
258 #define DMA2D_IT_TC DMA2D_CR_TCIE
259 #define DMA2D_IT_TE DMA2D_CR_TEIE
267 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF
268 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
269 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
270 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF
271 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF
272 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF
280 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort
285 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
291 HAL_DMA2D_MSPINIT_CB_ID = 0x00U,
292 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U,
293 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U,
294 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U,
295 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U,
296 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U,
297 }HAL_DMA2D_CallbackIDTypeDef;
313 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
314 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
315 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
316 (__HANDLE__)->MspInitCallback = NULL; \
317 (__HANDLE__)->MspDeInitCallback = NULL; \
320 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
329 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
346 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
361 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
376 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
391 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
406 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
424 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
425 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
427 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
428 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);
429 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
442 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
443 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
444 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
445 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
449 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
450 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
451 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
452 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
453 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
454 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
455 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
456 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
457 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
458 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
459 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
460 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
471 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
472 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
473 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
476 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
487 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
488 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
507 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW
515 #define DMA2D_COLOR_VALUE 0x000000FFU
523 #define DMA2D_MAX_LAYER 2U
531 #define DMA2D_BACKGROUND_LAYER 0x00000000U
532 #define DMA2D_FOREGROUND_LAYER 0x00000001U
540 #define DMA2D_OFFSET DMA2D_FGOR_LO
548 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)
549 #define DMA2D_LINE DMA2D_NLR_NL
557 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U)
571 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
573 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
574 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
576 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
577 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
578 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
580 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
581 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
582 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
583 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
585 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
586 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
587 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
588 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
589 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
590 ((INPUT_CM) == DMA2D_INPUT_A4))
592 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
593 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
594 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
600 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
601 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
602 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
603 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
604 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
605 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
606 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
607 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
608 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))