utils/cmsis/same70/include/instance/hsmci.h
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1 
31 /*
32  * Support and FAQ: visit <a href="https://www.microchip.com/support/">Microchip Support</a>
33  */
34 
35 #ifndef _SAME70_HSMCI_INSTANCE_
36 #define _SAME70_HSMCI_INSTANCE_
37 
38 /* ========== Register definition for HSMCI peripheral ========== */
39 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40  #define REG_HSMCI_CR (0x40000000U)
41  #define REG_HSMCI_MR (0x40000004U)
42  #define REG_HSMCI_DTOR (0x40000008U)
43  #define REG_HSMCI_SDCR (0x4000000CU)
44  #define REG_HSMCI_ARGR (0x40000010U)
45  #define REG_HSMCI_CMDR (0x40000014U)
46  #define REG_HSMCI_BLKR (0x40000018U)
47  #define REG_HSMCI_CSTOR (0x4000001CU)
48  #define REG_HSMCI_RSPR (0x40000020U)
49  #define REG_HSMCI_RDR (0x40000030U)
50  #define REG_HSMCI_TDR (0x40000034U)
51  #define REG_HSMCI_SR (0x40000040U)
52  #define REG_HSMCI_IER (0x40000044U)
53  #define REG_HSMCI_IDR (0x40000048U)
54  #define REG_HSMCI_IMR (0x4000004CU)
55  #define REG_HSMCI_DMA (0x40000050U)
56  #define REG_HSMCI_CFG (0x40000054U)
57  #define REG_HSMCI_WPMR (0x400000E4U)
58  #define REG_HSMCI_WPSR (0x400000E8U)
59  #define REG_HSMCI_VERSION (0x400000FCU)
60  #define REG_HSMCI_FIFO (0x40000200U)
61 #else
62  #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U)
63  #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U)
64  #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U)
65  #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU)
66  #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U)
67  #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U)
68  #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U)
69  #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU)
70  #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U)
71  #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U)
72  #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U)
73  #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U)
74  #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U)
75  #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U)
76  #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU)
77  #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U)
78  #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U)
79  #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U)
80  #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U)
81  #define REG_HSMCI_VERSION (*(__I uint32_t*)0x400000FCU)
82  #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U)
83 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
84 
85 #endif /* _SAME70_HSMCI_INSTANCE_ */


inertial_sense_ros
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autogenerated on Sat Sep 19 2020 03:19:04